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1 /**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
48 */
49
50 #include "hw.h"
51 #include "pci.h"
52 #include "qemu-timer.h"
53 #include "net.h"
54 #include "loader.h"
55 #include "sysemu.h"
56
57 /* debug RTL8139 card */
58 //#define DEBUG_RTL8139 1
59
60 #define PCI_FREQUENCY 33000000L
61
62 /* debug RTL8139 card C+ mode only */
63 //#define DEBUG_RTL8139CP 1
64
65 /* Calculate CRCs properly on Rx packets */
66 #define RTL8139_CALCULATE_RXCRC 1
67
68 #if defined(RTL8139_CALCULATE_RXCRC)
69 /* For crc32 */
70 #include <zlib.h>
71 #endif
72
73 #define SET_MASKED(input, mask, curr) \
74 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
75
76 /* arg % size for size which is a power of 2 */
77 #define MOD2(input, size) \
78 ( ( input ) & ( size - 1 ) )
79
80 #if defined (DEBUG_RTL8139)
81 # define DEBUG_PRINT(x) do { printf x ; } while (0)
82 #else
83 # define DEBUG_PRINT(x)
84 #endif
85
86 /* Symbolic offsets to registers. */
87 enum RTL8139_registers {
88 MAC0 = 0, /* Ethernet hardware address. */
89 MAR0 = 8, /* Multicast filter. */
90 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
91 /* Dump Tally Conter control register(64bit). C+ mode only */
92 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
93 RxBuf = 0x30,
94 ChipCmd = 0x37,
95 RxBufPtr = 0x38,
96 RxBufAddr = 0x3A,
97 IntrMask = 0x3C,
98 IntrStatus = 0x3E,
99 TxConfig = 0x40,
100 RxConfig = 0x44,
101 Timer = 0x48, /* A general-purpose counter. */
102 RxMissed = 0x4C, /* 24 bits valid, write clears. */
103 Cfg9346 = 0x50,
104 Config0 = 0x51,
105 Config1 = 0x52,
106 FlashReg = 0x54,
107 MediaStatus = 0x58,
108 Config3 = 0x59,
109 Config4 = 0x5A, /* absent on RTL-8139A */
110 HltClk = 0x5B,
111 MultiIntr = 0x5C,
112 PCIRevisionID = 0x5E,
113 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
114 BasicModeCtrl = 0x62,
115 BasicModeStatus = 0x64,
116 NWayAdvert = 0x66,
117 NWayLPAR = 0x68,
118 NWayExpansion = 0x6A,
119 /* Undocumented registers, but required for proper operation. */
120 FIFOTMS = 0x70, /* FIFO Control and test. */
121 CSCR = 0x74, /* Chip Status and Configuration Register. */
122 PARA78 = 0x78,
123 PARA7c = 0x7c, /* Magic transceiver parameter register. */
124 Config5 = 0xD8, /* absent on RTL-8139A */
125 /* C+ mode */
126 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
127 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
128 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
129 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
130 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
131 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
132 TxThresh = 0xEC, /* Early Tx threshold */
133 };
134
135 enum ClearBitMasks {
136 MultiIntrClear = 0xF000,
137 ChipCmdClear = 0xE2,
138 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
139 };
140
141 enum ChipCmdBits {
142 CmdReset = 0x10,
143 CmdRxEnb = 0x08,
144 CmdTxEnb = 0x04,
145 RxBufEmpty = 0x01,
146 };
147
148 /* C+ mode */
149 enum CplusCmdBits {
150 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
151 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
152 CPlusRxEnb = 0x0002,
153 CPlusTxEnb = 0x0001,
154 };
155
156 /* Interrupt register bits, using my own meaningful names. */
157 enum IntrStatusBits {
158 PCIErr = 0x8000,
159 PCSTimeout = 0x4000,
160 RxFIFOOver = 0x40,
161 RxUnderrun = 0x20,
162 RxOverflow = 0x10,
163 TxErr = 0x08,
164 TxOK = 0x04,
165 RxErr = 0x02,
166 RxOK = 0x01,
167
168 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
169 };
170
171 enum TxStatusBits {
172 TxHostOwns = 0x2000,
173 TxUnderrun = 0x4000,
174 TxStatOK = 0x8000,
175 TxOutOfWindow = 0x20000000,
176 TxAborted = 0x40000000,
177 TxCarrierLost = 0x80000000,
178 };
179 enum RxStatusBits {
180 RxMulticast = 0x8000,
181 RxPhysical = 0x4000,
182 RxBroadcast = 0x2000,
183 RxBadSymbol = 0x0020,
184 RxRunt = 0x0010,
185 RxTooLong = 0x0008,
186 RxCRCErr = 0x0004,
187 RxBadAlign = 0x0002,
188 RxStatusOK = 0x0001,
189 };
190
191 /* Bits in RxConfig. */
192 enum rx_mode_bits {
193 AcceptErr = 0x20,
194 AcceptRunt = 0x10,
195 AcceptBroadcast = 0x08,
196 AcceptMulticast = 0x04,
197 AcceptMyPhys = 0x02,
198 AcceptAllPhys = 0x01,
199 };
200
201 /* Bits in TxConfig. */
202 enum tx_config_bits {
203
204 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
205 TxIFGShift = 24,
206 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
207 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
208 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
209 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
210
211 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
212 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
213 TxClearAbt = (1 << 0), /* Clear abort (WO) */
214 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
215 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
216
217 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
218 };
219
220
221 /* Transmit Status of All Descriptors (TSAD) Register */
222 enum TSAD_bits {
223 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
224 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
225 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
226 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
227 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
228 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
229 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
230 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
231 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
232 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
233 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
234 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
235 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
236 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
237 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
238 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
239 };
240
241
242 /* Bits in Config1 */
243 enum Config1Bits {
244 Cfg1_PM_Enable = 0x01,
245 Cfg1_VPD_Enable = 0x02,
246 Cfg1_PIO = 0x04,
247 Cfg1_MMIO = 0x08,
248 LWAKE = 0x10, /* not on 8139, 8139A */
249 Cfg1_Driver_Load = 0x20,
250 Cfg1_LED0 = 0x40,
251 Cfg1_LED1 = 0x80,
252 SLEEP = (1 << 1), /* only on 8139, 8139A */
253 PWRDN = (1 << 0), /* only on 8139, 8139A */
254 };
255
256 /* Bits in Config3 */
257 enum Config3Bits {
258 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
259 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
260 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
261 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
262 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
263 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
264 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
265 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
266 };
267
268 /* Bits in Config4 */
269 enum Config4Bits {
270 LWPTN = (1 << 2), /* not on 8139, 8139A */
271 };
272
273 /* Bits in Config5 */
274 enum Config5Bits {
275 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
276 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
277 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
278 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
279 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
280 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
281 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
282 };
283
284 enum RxConfigBits {
285 /* rx fifo threshold */
286 RxCfgFIFOShift = 13,
287 RxCfgFIFONone = (7 << RxCfgFIFOShift),
288
289 /* Max DMA burst */
290 RxCfgDMAShift = 8,
291 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
292
293 /* rx ring buffer length */
294 RxCfgRcv8K = 0,
295 RxCfgRcv16K = (1 << 11),
296 RxCfgRcv32K = (1 << 12),
297 RxCfgRcv64K = (1 << 11) | (1 << 12),
298
299 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
300 RxNoWrap = (1 << 7),
301 };
302
303 /* Twister tuning parameters from RealTek.
304 Completely undocumented, but required to tune bad links on some boards. */
305 /*
306 enum CSCRBits {
307 CSCR_LinkOKBit = 0x0400,
308 CSCR_LinkChangeBit = 0x0800,
309 CSCR_LinkStatusBits = 0x0f000,
310 CSCR_LinkDownOffCmd = 0x003c0,
311 CSCR_LinkDownCmd = 0x0f3c0,
312 */
313 enum CSCRBits {
314 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
315 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
316 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
317 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
318 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
319 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
320 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
321 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
322 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
323 };
324
325 enum Cfg9346Bits {
326 Cfg9346_Lock = 0x00,
327 Cfg9346_Unlock = 0xC0,
328 };
329
330 typedef enum {
331 CH_8139 = 0,
332 CH_8139_K,
333 CH_8139A,
334 CH_8139A_G,
335 CH_8139B,
336 CH_8130,
337 CH_8139C,
338 CH_8100,
339 CH_8100B_8139D,
340 CH_8101,
341 } chip_t;
342
343 enum chip_flags {
344 HasHltClk = (1 << 0),
345 HasLWake = (1 << 1),
346 };
347
348 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
349 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
350 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
351
352 #define RTL8139_PCI_REVID_8139 0x10
353 #define RTL8139_PCI_REVID_8139CPLUS 0x20
354
355 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
356
357 /* Size is 64 * 16bit words */
358 #define EEPROM_9346_ADDR_BITS 6
359 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
360 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
361
362 enum Chip9346Operation
363 {
364 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
365 Chip9346_op_read = 0x80, /* 10 AAAAAA */
366 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
367 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
368 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
369 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
370 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
371 };
372
373 enum Chip9346Mode
374 {
375 Chip9346_none = 0,
376 Chip9346_enter_command_mode,
377 Chip9346_read_command,
378 Chip9346_data_read, /* from output register */
379 Chip9346_data_write, /* to input register, then to contents at specified address */
380 Chip9346_data_write_all, /* to input register, then filling contents */
381 };
382
383 typedef struct EEprom9346
384 {
385 uint16_t contents[EEPROM_9346_SIZE];
386 int mode;
387 uint32_t tick;
388 uint8_t address;
389 uint16_t input;
390 uint16_t output;
391
392 uint8_t eecs;
393 uint8_t eesk;
394 uint8_t eedi;
395 uint8_t eedo;
396 } EEprom9346;
397
398 typedef struct RTL8139TallyCounters
399 {
400 /* Tally counters */
401 uint64_t TxOk;
402 uint64_t RxOk;
403 uint64_t TxERR;
404 uint32_t RxERR;
405 uint16_t MissPkt;
406 uint16_t FAE;
407 uint32_t Tx1Col;
408 uint32_t TxMCol;
409 uint64_t RxOkPhy;
410 uint64_t RxOkBrd;
411 uint32_t RxOkMul;
412 uint16_t TxAbt;
413 uint16_t TxUndrn;
414 } RTL8139TallyCounters;
415
416 /* Clears all tally counters */
417 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
418
419 /* Writes tally counters to specified physical memory address */
420 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
421
422 typedef struct RTL8139State {
423 PCIDevice dev;
424 uint8_t phys[8]; /* mac address */
425 uint8_t mult[8]; /* multicast mask array */
426
427 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
428 uint32_t TxAddr[4]; /* TxAddr0 */
429 uint32_t RxBuf; /* Receive buffer */
430 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
431 uint32_t RxBufPtr;
432 uint32_t RxBufAddr;
433
434 uint16_t IntrStatus;
435 uint16_t IntrMask;
436
437 uint32_t TxConfig;
438 uint32_t RxConfig;
439 uint32_t RxMissed;
440
441 uint16_t CSCR;
442
443 uint8_t Cfg9346;
444 uint8_t Config0;
445 uint8_t Config1;
446 uint8_t Config3;
447 uint8_t Config4;
448 uint8_t Config5;
449
450 uint8_t clock_enabled;
451 uint8_t bChipCmdState;
452
453 uint16_t MultiIntr;
454
455 uint16_t BasicModeCtrl;
456 uint16_t BasicModeStatus;
457 uint16_t NWayAdvert;
458 uint16_t NWayLPAR;
459 uint16_t NWayExpansion;
460
461 uint16_t CpCmd;
462 uint8_t TxThresh;
463
464 NICState *nic;
465 NICConf conf;
466 int rtl8139_mmio_io_addr;
467
468 /* C ring mode */
469 uint32_t currTxDesc;
470
471 /* C+ mode */
472 uint32_t cplus_enabled;
473
474 uint32_t currCPlusRxDesc;
475 uint32_t currCPlusTxDesc;
476
477 uint32_t RxRingAddrLO;
478 uint32_t RxRingAddrHI;
479
480 EEprom9346 eeprom;
481
482 uint32_t TCTR;
483 uint32_t TimerInt;
484 int64_t TCTR_base;
485
486 /* Tally counters */
487 RTL8139TallyCounters tally_counters;
488
489 /* Non-persistent data */
490 uint8_t *cplus_txbuffer;
491 int cplus_txbuffer_len;
492 int cplus_txbuffer_offset;
493
494 /* PCI interrupt timer */
495 QEMUTimer *timer;
496 int64_t TimerExpire;
497
498 /* Support migration to/from old versions */
499 int rtl8139_mmio_io_addr_dummy;
500 } RTL8139State;
501
502 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
503
504 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
505 {
506 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
507
508 switch (command & Chip9346_op_mask)
509 {
510 case Chip9346_op_read:
511 {
512 eeprom->address = command & EEPROM_9346_ADDR_MASK;
513 eeprom->output = eeprom->contents[eeprom->address];
514 eeprom->eedo = 0;
515 eeprom->tick = 0;
516 eeprom->mode = Chip9346_data_read;
517 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
518 eeprom->address, eeprom->output));
519 }
520 break;
521
522 case Chip9346_op_write:
523 {
524 eeprom->address = command & EEPROM_9346_ADDR_MASK;
525 eeprom->input = 0;
526 eeprom->tick = 0;
527 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
528 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
529 eeprom->address));
530 }
531 break;
532 default:
533 eeprom->mode = Chip9346_none;
534 switch (command & Chip9346_op_ext_mask)
535 {
536 case Chip9346_op_write_enable:
537 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
538 break;
539 case Chip9346_op_write_all:
540 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
541 break;
542 case Chip9346_op_write_disable:
543 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
544 break;
545 }
546 break;
547 }
548 }
549
550 static void prom9346_shift_clock(EEprom9346 *eeprom)
551 {
552 int bit = eeprom->eedi?1:0;
553
554 ++ eeprom->tick;
555
556 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
557
558 switch (eeprom->mode)
559 {
560 case Chip9346_enter_command_mode:
561 if (bit)
562 {
563 eeprom->mode = Chip9346_read_command;
564 eeprom->tick = 0;
565 eeprom->input = 0;
566 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
567 }
568 break;
569
570 case Chip9346_read_command:
571 eeprom->input = (eeprom->input << 1) | (bit & 1);
572 if (eeprom->tick == 8)
573 {
574 prom9346_decode_command(eeprom, eeprom->input & 0xff);
575 }
576 break;
577
578 case Chip9346_data_read:
579 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
580 eeprom->output <<= 1;
581 if (eeprom->tick == 16)
582 {
583 #if 1
584 // the FreeBSD drivers (rl and re) don't explicitly toggle
585 // CS between reads (or does setting Cfg9346 to 0 count too?),
586 // so we need to enter wait-for-command state here
587 eeprom->mode = Chip9346_enter_command_mode;
588 eeprom->input = 0;
589 eeprom->tick = 0;
590
591 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
592 #else
593 // original behaviour
594 ++eeprom->address;
595 eeprom->address &= EEPROM_9346_ADDR_MASK;
596 eeprom->output = eeprom->contents[eeprom->address];
597 eeprom->tick = 0;
598
599 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
600 eeprom->address, eeprom->output));
601 #endif
602 }
603 break;
604
605 case Chip9346_data_write:
606 eeprom->input = (eeprom->input << 1) | (bit & 1);
607 if (eeprom->tick == 16)
608 {
609 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
610 eeprom->address, eeprom->input));
611
612 eeprom->contents[eeprom->address] = eeprom->input;
613 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
614 eeprom->tick = 0;
615 eeprom->input = 0;
616 }
617 break;
618
619 case Chip9346_data_write_all:
620 eeprom->input = (eeprom->input << 1) | (bit & 1);
621 if (eeprom->tick == 16)
622 {
623 int i;
624 for (i = 0; i < EEPROM_9346_SIZE; i++)
625 {
626 eeprom->contents[i] = eeprom->input;
627 }
628 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
629 eeprom->input));
630
631 eeprom->mode = Chip9346_enter_command_mode;
632 eeprom->tick = 0;
633 eeprom->input = 0;
634 }
635 break;
636
637 default:
638 break;
639 }
640 }
641
642 static int prom9346_get_wire(RTL8139State *s)
643 {
644 EEprom9346 *eeprom = &s->eeprom;
645 if (!eeprom->eecs)
646 return 0;
647
648 return eeprom->eedo;
649 }
650
651 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
652 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
653 {
654 EEprom9346 *eeprom = &s->eeprom;
655 uint8_t old_eecs = eeprom->eecs;
656 uint8_t old_eesk = eeprom->eesk;
657
658 eeprom->eecs = eecs;
659 eeprom->eesk = eesk;
660 eeprom->eedi = eedi;
661
662 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
663 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
664
665 if (!old_eecs && eecs)
666 {
667 /* Synchronize start */
668 eeprom->tick = 0;
669 eeprom->input = 0;
670 eeprom->output = 0;
671 eeprom->mode = Chip9346_enter_command_mode;
672
673 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
674 }
675
676 if (!eecs)
677 {
678 DEBUG_PRINT(("=== eeprom: end access\n"));
679 return;
680 }
681
682 if (!old_eesk && eesk)
683 {
684 /* SK front rules */
685 prom9346_shift_clock(eeprom);
686 }
687 }
688
689 static void rtl8139_update_irq(RTL8139State *s)
690 {
691 int isr;
692 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
693
694 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
695 isr ? 1 : 0, s->IntrStatus, s->IntrMask));
696
697 qemu_set_irq(s->dev.irq[0], (isr != 0));
698 }
699
700 #define POLYNOMIAL 0x04c11db6
701
702 /* From FreeBSD */
703 /* XXX: optimize */
704 static int compute_mcast_idx(const uint8_t *ep)
705 {
706 uint32_t crc;
707 int carry, i, j;
708 uint8_t b;
709
710 crc = 0xffffffff;
711 for (i = 0; i < 6; i++) {
712 b = *ep++;
713 for (j = 0; j < 8; j++) {
714 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
715 crc <<= 1;
716 b >>= 1;
717 if (carry)
718 crc = ((crc ^ POLYNOMIAL) | carry);
719 }
720 }
721 return (crc >> 26);
722 }
723
724 static int rtl8139_RxWrap(RTL8139State *s)
725 {
726 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
727 return (s->RxConfig & (1 << 7));
728 }
729
730 static int rtl8139_receiver_enabled(RTL8139State *s)
731 {
732 return s->bChipCmdState & CmdRxEnb;
733 }
734
735 static int rtl8139_transmitter_enabled(RTL8139State *s)
736 {
737 return s->bChipCmdState & CmdTxEnb;
738 }
739
740 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
741 {
742 return s->CpCmd & CPlusRxEnb;
743 }
744
745 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
746 {
747 return s->CpCmd & CPlusTxEnb;
748 }
749
750 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
751 {
752 if (s->RxBufAddr + size > s->RxBufferSize)
753 {
754 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
755
756 /* write packet data */
757 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
758 {
759 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
760
761 if (size > wrapped)
762 {
763 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
764 buf, size-wrapped );
765 }
766
767 /* reset buffer pointer */
768 s->RxBufAddr = 0;
769
770 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
771 buf + (size-wrapped), wrapped );
772
773 s->RxBufAddr = wrapped;
774
775 return;
776 }
777 }
778
779 /* non-wrapping path or overwrapping enabled */
780 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
781
782 s->RxBufAddr += size;
783 }
784
785 #define MIN_BUF_SIZE 60
786 static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
787 {
788 #if TARGET_PHYS_ADDR_BITS > 32
789 return low | ((target_phys_addr_t)high << 32);
790 #else
791 return low;
792 #endif
793 }
794
795 static int rtl8139_can_receive(VLANClientState *nc)
796 {
797 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
798 int avail;
799
800 /* Receive (drop) packets if card is disabled. */
801 if (!s->clock_enabled)
802 return 1;
803 if (!rtl8139_receiver_enabled(s))
804 return 1;
805
806 if (rtl8139_cp_receiver_enabled(s)) {
807 /* ??? Flow control not implemented in c+ mode.
808 This is a hack to work around slirp deficiencies anyway. */
809 return 1;
810 } else {
811 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
812 s->RxBufferSize);
813 return (avail == 0 || avail >= 1514);
814 }
815 }
816
817 static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
818 {
819 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
820 int size = size_;
821
822 uint32_t packet_header = 0;
823
824 uint8_t buf1[60];
825 static const uint8_t broadcast_macaddr[6] =
826 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
827
828 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
829
830 /* test if board clock is stopped */
831 if (!s->clock_enabled)
832 {
833 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
834 return -1;
835 }
836
837 /* first check if receiver is enabled */
838
839 if (!rtl8139_receiver_enabled(s))
840 {
841 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
842 return -1;
843 }
844
845 /* XXX: check this */
846 if (s->RxConfig & AcceptAllPhys) {
847 /* promiscuous: receive all */
848 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
849
850 } else {
851 if (!memcmp(buf, broadcast_macaddr, 6)) {
852 /* broadcast address */
853 if (!(s->RxConfig & AcceptBroadcast))
854 {
855 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
856
857 /* update tally counter */
858 ++s->tally_counters.RxERR;
859
860 return size;
861 }
862
863 packet_header |= RxBroadcast;
864
865 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
866
867 /* update tally counter */
868 ++s->tally_counters.RxOkBrd;
869
870 } else if (buf[0] & 0x01) {
871 /* multicast */
872 if (!(s->RxConfig & AcceptMulticast))
873 {
874 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
875
876 /* update tally counter */
877 ++s->tally_counters.RxERR;
878
879 return size;
880 }
881
882 int mcast_idx = compute_mcast_idx(buf);
883
884 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
885 {
886 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
887
888 /* update tally counter */
889 ++s->tally_counters.RxERR;
890
891 return size;
892 }
893
894 packet_header |= RxMulticast;
895
896 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
897
898 /* update tally counter */
899 ++s->tally_counters.RxOkMul;
900
901 } else if (s->phys[0] == buf[0] &&
902 s->phys[1] == buf[1] &&
903 s->phys[2] == buf[2] &&
904 s->phys[3] == buf[3] &&
905 s->phys[4] == buf[4] &&
906 s->phys[5] == buf[5]) {
907 /* match */
908 if (!(s->RxConfig & AcceptMyPhys))
909 {
910 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
911
912 /* update tally counter */
913 ++s->tally_counters.RxERR;
914
915 return size;
916 }
917
918 packet_header |= RxPhysical;
919
920 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
921
922 /* update tally counter */
923 ++s->tally_counters.RxOkPhy;
924
925 } else {
926
927 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
928
929 /* update tally counter */
930 ++s->tally_counters.RxERR;
931
932 return size;
933 }
934 }
935
936 /* if too small buffer, then expand it */
937 if (size < MIN_BUF_SIZE) {
938 memcpy(buf1, buf, size);
939 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
940 buf = buf1;
941 size = MIN_BUF_SIZE;
942 }
943
944 if (rtl8139_cp_receiver_enabled(s))
945 {
946 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
947
948 /* begin C+ receiver mode */
949
950 /* w0 ownership flag */
951 #define CP_RX_OWN (1<<31)
952 /* w0 end of ring flag */
953 #define CP_RX_EOR (1<<30)
954 /* w0 bits 0...12 : buffer size */
955 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
956 /* w1 tag available flag */
957 #define CP_RX_TAVA (1<<16)
958 /* w1 bits 0...15 : VLAN tag */
959 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
960 /* w2 low 32bit of Rx buffer ptr */
961 /* w3 high 32bit of Rx buffer ptr */
962
963 int descriptor = s->currCPlusRxDesc;
964 target_phys_addr_t cplus_rx_ring_desc;
965
966 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
967 cplus_rx_ring_desc += 16 * descriptor;
968
969 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
970 descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
971
972 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
973
974 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
975 rxdw0 = le32_to_cpu(val);
976 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
977 rxdw1 = le32_to_cpu(val);
978 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
979 rxbufLO = le32_to_cpu(val);
980 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
981 rxbufHI = le32_to_cpu(val);
982
983 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
984 descriptor,
985 rxdw0, rxdw1, rxbufLO, rxbufHI));
986
987 if (!(rxdw0 & CP_RX_OWN))
988 {
989 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
990
991 s->IntrStatus |= RxOverflow;
992 ++s->RxMissed;
993
994 /* update tally counter */
995 ++s->tally_counters.RxERR;
996 ++s->tally_counters.MissPkt;
997
998 rtl8139_update_irq(s);
999 return size_;
1000 }
1001
1002 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1003
1004 /* TODO: scatter the packet over available receive ring descriptors space */
1005
1006 if (size+4 > rx_space)
1007 {
1008 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1009 descriptor, rx_space, size));
1010
1011 s->IntrStatus |= RxOverflow;
1012 ++s->RxMissed;
1013
1014 /* update tally counter */
1015 ++s->tally_counters.RxERR;
1016 ++s->tally_counters.MissPkt;
1017
1018 rtl8139_update_irq(s);
1019 return size_;
1020 }
1021
1022 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1023
1024 /* receive/copy to target memory */
1025 cpu_physical_memory_write( rx_addr, buf, size );
1026
1027 if (s->CpCmd & CPlusRxChkSum)
1028 {
1029 /* do some packet checksumming */
1030 }
1031
1032 /* write checksum */
1033 #if defined (RTL8139_CALCULATE_RXCRC)
1034 val = cpu_to_le32(crc32(0, buf, size));
1035 #else
1036 val = 0;
1037 #endif
1038 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1039
1040 /* first segment of received packet flag */
1041 #define CP_RX_STATUS_FS (1<<29)
1042 /* last segment of received packet flag */
1043 #define CP_RX_STATUS_LS (1<<28)
1044 /* multicast packet flag */
1045 #define CP_RX_STATUS_MAR (1<<26)
1046 /* physical-matching packet flag */
1047 #define CP_RX_STATUS_PAM (1<<25)
1048 /* broadcast packet flag */
1049 #define CP_RX_STATUS_BAR (1<<24)
1050 /* runt packet flag */
1051 #define CP_RX_STATUS_RUNT (1<<19)
1052 /* crc error flag */
1053 #define CP_RX_STATUS_CRC (1<<18)
1054 /* IP checksum error flag */
1055 #define CP_RX_STATUS_IPF (1<<15)
1056 /* UDP checksum error flag */
1057 #define CP_RX_STATUS_UDPF (1<<14)
1058 /* TCP checksum error flag */
1059 #define CP_RX_STATUS_TCPF (1<<13)
1060
1061 /* transfer ownership to target */
1062 rxdw0 &= ~CP_RX_OWN;
1063
1064 /* set first segment bit */
1065 rxdw0 |= CP_RX_STATUS_FS;
1066
1067 /* set last segment bit */
1068 rxdw0 |= CP_RX_STATUS_LS;
1069
1070 /* set received packet type flags */
1071 if (packet_header & RxBroadcast)
1072 rxdw0 |= CP_RX_STATUS_BAR;
1073 if (packet_header & RxMulticast)
1074 rxdw0 |= CP_RX_STATUS_MAR;
1075 if (packet_header & RxPhysical)
1076 rxdw0 |= CP_RX_STATUS_PAM;
1077
1078 /* set received size */
1079 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1080 rxdw0 |= (size+4);
1081
1082 /* reset VLAN tag flag */
1083 rxdw1 &= ~CP_RX_TAVA;
1084
1085 /* update ring data */
1086 val = cpu_to_le32(rxdw0);
1087 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1088 val = cpu_to_le32(rxdw1);
1089 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1090
1091 /* update tally counter */
1092 ++s->tally_counters.RxOk;
1093
1094 /* seek to next Rx descriptor */
1095 if (rxdw0 & CP_RX_EOR)
1096 {
1097 s->currCPlusRxDesc = 0;
1098 }
1099 else
1100 {
1101 ++s->currCPlusRxDesc;
1102 }
1103
1104 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
1105
1106 }
1107 else
1108 {
1109 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1110
1111 /* begin ring receiver mode */
1112 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1113
1114 /* if receiver buffer is empty then avail == 0 */
1115
1116 if (avail != 0 && size + 8 >= avail)
1117 {
1118 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1119 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1120
1121 s->IntrStatus |= RxOverflow;
1122 ++s->RxMissed;
1123 rtl8139_update_irq(s);
1124 return size_;
1125 }
1126
1127 packet_header |= RxStatusOK;
1128
1129 packet_header |= (((size+4) << 16) & 0xffff0000);
1130
1131 /* write header */
1132 uint32_t val = cpu_to_le32(packet_header);
1133
1134 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1135
1136 rtl8139_write_buffer(s, buf, size);
1137
1138 /* write checksum */
1139 #if defined (RTL8139_CALCULATE_RXCRC)
1140 val = cpu_to_le32(crc32(0, buf, size));
1141 #else
1142 val = 0;
1143 #endif
1144
1145 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1146
1147 /* correct buffer write pointer */
1148 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1149
1150 /* now we can signal we have received something */
1151
1152 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1153 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
1154 }
1155
1156 s->IntrStatus |= RxOK;
1157
1158 if (do_interrupt)
1159 {
1160 rtl8139_update_irq(s);
1161 }
1162
1163 return size_;
1164 }
1165
1166 static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
1167 {
1168 return rtl8139_do_receive(nc, buf, size, 1);
1169 }
1170
1171 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1172 {
1173 s->RxBufferSize = bufferSize;
1174 s->RxBufPtr = 0;
1175 s->RxBufAddr = 0;
1176 }
1177
1178 static void rtl8139_reset(DeviceState *d)
1179 {
1180 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
1181 int i;
1182
1183 /* restore MAC address */
1184 memcpy(s->phys, s->conf.macaddr.a, 6);
1185
1186 /* reset interrupt mask */
1187 s->IntrStatus = 0;
1188 s->IntrMask = 0;
1189
1190 rtl8139_update_irq(s);
1191
1192 /* mark all status registers as owned by host */
1193 for (i = 0; i < 4; ++i)
1194 {
1195 s->TxStatus[i] = TxHostOwns;
1196 }
1197
1198 s->currTxDesc = 0;
1199 s->currCPlusRxDesc = 0;
1200 s->currCPlusTxDesc = 0;
1201
1202 s->RxRingAddrLO = 0;
1203 s->RxRingAddrHI = 0;
1204
1205 s->RxBuf = 0;
1206
1207 rtl8139_reset_rxring(s, 8192);
1208
1209 /* ACK the reset */
1210 s->TxConfig = 0;
1211
1212 #if 0
1213 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1214 s->clock_enabled = 0;
1215 #else
1216 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1217 s->clock_enabled = 1;
1218 #endif
1219
1220 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1221
1222 /* set initial state data */
1223 s->Config0 = 0x0; /* No boot ROM */
1224 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1225 s->Config3 = 0x1; /* fast back-to-back compatible */
1226 s->Config5 = 0x0;
1227
1228 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1229
1230 s->CpCmd = 0x0; /* reset C+ mode */
1231 s->cplus_enabled = 0;
1232
1233
1234 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1235 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1236 s->BasicModeCtrl = 0x1000; // autonegotiation
1237
1238 s->BasicModeStatus = 0x7809;
1239 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1240 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1241 s->BasicModeStatus |= 0x0004; /* link is up */
1242
1243 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1244 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1245 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1246
1247 /* also reset timer and disable timer interrupt */
1248 s->TCTR = 0;
1249 s->TimerInt = 0;
1250 s->TCTR_base = 0;
1251
1252 /* reset tally counters */
1253 RTL8139TallyCounters_clear(&s->tally_counters);
1254 }
1255
1256 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1257 {
1258 counters->TxOk = 0;
1259 counters->RxOk = 0;
1260 counters->TxERR = 0;
1261 counters->RxERR = 0;
1262 counters->MissPkt = 0;
1263 counters->FAE = 0;
1264 counters->Tx1Col = 0;
1265 counters->TxMCol = 0;
1266 counters->RxOkPhy = 0;
1267 counters->RxOkBrd = 0;
1268 counters->RxOkMul = 0;
1269 counters->TxAbt = 0;
1270 counters->TxUndrn = 0;
1271 }
1272
1273 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
1274 {
1275 uint16_t val16;
1276 uint32_t val32;
1277 uint64_t val64;
1278
1279 val64 = cpu_to_le64(tally_counters->TxOk);
1280 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1281
1282 val64 = cpu_to_le64(tally_counters->RxOk);
1283 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1284
1285 val64 = cpu_to_le64(tally_counters->TxERR);
1286 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1287
1288 val32 = cpu_to_le32(tally_counters->RxERR);
1289 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1290
1291 val16 = cpu_to_le16(tally_counters->MissPkt);
1292 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1293
1294 val16 = cpu_to_le16(tally_counters->FAE);
1295 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1296
1297 val32 = cpu_to_le32(tally_counters->Tx1Col);
1298 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1299
1300 val32 = cpu_to_le32(tally_counters->TxMCol);
1301 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1302
1303 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1304 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1305
1306 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1307 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1308
1309 val32 = cpu_to_le32(tally_counters->RxOkMul);
1310 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1311
1312 val16 = cpu_to_le16(tally_counters->TxAbt);
1313 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1314
1315 val16 = cpu_to_le16(tally_counters->TxUndrn);
1316 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1317 }
1318
1319 /* Loads values of tally counters from VM state file */
1320
1321 static const VMStateDescription vmstate_tally_counters = {
1322 .name = "tally_counters",
1323 .version_id = 1,
1324 .minimum_version_id = 1,
1325 .minimum_version_id_old = 1,
1326 .fields = (VMStateField []) {
1327 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1328 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1329 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1330 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1331 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1332 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1333 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1334 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1335 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1336 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1337 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1338 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1339 VMSTATE_END_OF_LIST()
1340 }
1341 };
1342
1343 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1344 {
1345 val &= 0xff;
1346
1347 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
1348
1349 if (val & CmdReset)
1350 {
1351 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
1352 rtl8139_reset(&s->dev.qdev);
1353 }
1354 if (val & CmdRxEnb)
1355 {
1356 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
1357
1358 s->currCPlusRxDesc = 0;
1359 }
1360 if (val & CmdTxEnb)
1361 {
1362 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
1363
1364 s->currCPlusTxDesc = 0;
1365 }
1366
1367 /* mask unwriteable bits */
1368 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1369
1370 /* Deassert reset pin before next read */
1371 val &= ~CmdReset;
1372
1373 s->bChipCmdState = val;
1374 }
1375
1376 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1377 {
1378 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1379
1380 if (unread != 0)
1381 {
1382 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
1383 return 0;
1384 }
1385
1386 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
1387
1388 return 1;
1389 }
1390
1391 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1392 {
1393 uint32_t ret = s->bChipCmdState;
1394
1395 if (rtl8139_RxBufferEmpty(s))
1396 ret |= RxBufEmpty;
1397
1398 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
1399
1400 return ret;
1401 }
1402
1403 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1404 {
1405 val &= 0xffff;
1406
1407 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
1408
1409 s->cplus_enabled = 1;
1410
1411 /* mask unwriteable bits */
1412 val = SET_MASKED(val, 0xff84, s->CpCmd);
1413
1414 s->CpCmd = val;
1415 }
1416
1417 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1418 {
1419 uint32_t ret = s->CpCmd;
1420
1421 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1422
1423 return ret;
1424 }
1425
1426 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1427 {
1428 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1429 }
1430
1431 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1432 {
1433 uint32_t ret = 0;
1434
1435 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
1436
1437 return ret;
1438 }
1439
1440 static int rtl8139_config_writeable(RTL8139State *s)
1441 {
1442 if (s->Cfg9346 & Cfg9346_Unlock)
1443 {
1444 return 1;
1445 }
1446
1447 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
1448
1449 return 0;
1450 }
1451
1452 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1453 {
1454 val &= 0xffff;
1455
1456 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
1457
1458 /* mask unwriteable bits */
1459 uint32_t mask = 0x4cff;
1460
1461 if (1 || !rtl8139_config_writeable(s))
1462 {
1463 /* Speed setting and autonegotiation enable bits are read-only */
1464 mask |= 0x3000;
1465 /* Duplex mode setting is read-only */
1466 mask |= 0x0100;
1467 }
1468
1469 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1470
1471 s->BasicModeCtrl = val;
1472 }
1473
1474 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1475 {
1476 uint32_t ret = s->BasicModeCtrl;
1477
1478 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
1479
1480 return ret;
1481 }
1482
1483 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1484 {
1485 val &= 0xffff;
1486
1487 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
1488
1489 /* mask unwriteable bits */
1490 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1491
1492 s->BasicModeStatus = val;
1493 }
1494
1495 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1496 {
1497 uint32_t ret = s->BasicModeStatus;
1498
1499 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
1500
1501 return ret;
1502 }
1503
1504 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1505 {
1506 val &= 0xff;
1507
1508 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
1509
1510 /* mask unwriteable bits */
1511 val = SET_MASKED(val, 0x31, s->Cfg9346);
1512
1513 uint32_t opmode = val & 0xc0;
1514 uint32_t eeprom_val = val & 0xf;
1515
1516 if (opmode == 0x80) {
1517 /* eeprom access */
1518 int eecs = (eeprom_val & 0x08)?1:0;
1519 int eesk = (eeprom_val & 0x04)?1:0;
1520 int eedi = (eeprom_val & 0x02)?1:0;
1521 prom9346_set_wire(s, eecs, eesk, eedi);
1522 } else if (opmode == 0x40) {
1523 /* Reset. */
1524 val = 0;
1525 rtl8139_reset(&s->dev.qdev);
1526 }
1527
1528 s->Cfg9346 = val;
1529 }
1530
1531 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1532 {
1533 uint32_t ret = s->Cfg9346;
1534
1535 uint32_t opmode = ret & 0xc0;
1536
1537 if (opmode == 0x80)
1538 {
1539 /* eeprom access */
1540 int eedo = prom9346_get_wire(s);
1541 if (eedo)
1542 {
1543 ret |= 0x01;
1544 }
1545 else
1546 {
1547 ret &= ~0x01;
1548 }
1549 }
1550
1551 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
1552
1553 return ret;
1554 }
1555
1556 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1557 {
1558 val &= 0xff;
1559
1560 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
1561
1562 if (!rtl8139_config_writeable(s))
1563 return;
1564
1565 /* mask unwriteable bits */
1566 val = SET_MASKED(val, 0xf8, s->Config0);
1567
1568 s->Config0 = val;
1569 }
1570
1571 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1572 {
1573 uint32_t ret = s->Config0;
1574
1575 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
1576
1577 return ret;
1578 }
1579
1580 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1581 {
1582 val &= 0xff;
1583
1584 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
1585
1586 if (!rtl8139_config_writeable(s))
1587 return;
1588
1589 /* mask unwriteable bits */
1590 val = SET_MASKED(val, 0xC, s->Config1);
1591
1592 s->Config1 = val;
1593 }
1594
1595 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1596 {
1597 uint32_t ret = s->Config1;
1598
1599 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
1600
1601 return ret;
1602 }
1603
1604 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1605 {
1606 val &= 0xff;
1607
1608 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
1609
1610 if (!rtl8139_config_writeable(s))
1611 return;
1612
1613 /* mask unwriteable bits */
1614 val = SET_MASKED(val, 0x8F, s->Config3);
1615
1616 s->Config3 = val;
1617 }
1618
1619 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1620 {
1621 uint32_t ret = s->Config3;
1622
1623 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
1624
1625 return ret;
1626 }
1627
1628 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1629 {
1630 val &= 0xff;
1631
1632 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
1633
1634 if (!rtl8139_config_writeable(s))
1635 return;
1636
1637 /* mask unwriteable bits */
1638 val = SET_MASKED(val, 0x0a, s->Config4);
1639
1640 s->Config4 = val;
1641 }
1642
1643 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1644 {
1645 uint32_t ret = s->Config4;
1646
1647 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
1648
1649 return ret;
1650 }
1651
1652 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1653 {
1654 val &= 0xff;
1655
1656 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
1657
1658 /* mask unwriteable bits */
1659 val = SET_MASKED(val, 0x80, s->Config5);
1660
1661 s->Config5 = val;
1662 }
1663
1664 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1665 {
1666 uint32_t ret = s->Config5;
1667
1668 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
1669
1670 return ret;
1671 }
1672
1673 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1674 {
1675 if (!rtl8139_transmitter_enabled(s))
1676 {
1677 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
1678 return;
1679 }
1680
1681 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
1682
1683 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1684
1685 s->TxConfig = val;
1686 }
1687
1688 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1689 {
1690 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1691
1692 uint32_t tc = s->TxConfig;
1693 tc &= 0xFFFFFF00;
1694 tc |= (val & 0x000000FF);
1695 rtl8139_TxConfig_write(s, tc);
1696 }
1697
1698 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1699 {
1700 uint32_t ret = s->TxConfig;
1701
1702 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
1703
1704 return ret;
1705 }
1706
1707 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1708 {
1709 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
1710
1711 /* mask unwriteable bits */
1712 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1713
1714 s->RxConfig = val;
1715
1716 /* reset buffer size and read/write pointers */
1717 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1718
1719 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
1720 }
1721
1722 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1723 {
1724 uint32_t ret = s->RxConfig;
1725
1726 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
1727
1728 return ret;
1729 }
1730
1731 static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
1732 {
1733 if (!size)
1734 {
1735 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1736 return;
1737 }
1738
1739 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1740 {
1741 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1742 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
1743 }
1744 else
1745 {
1746 qemu_send_packet(&s->nic->nc, buf, size);
1747 }
1748 }
1749
1750 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1751 {
1752 if (!rtl8139_transmitter_enabled(s))
1753 {
1754 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1755 descriptor));
1756 return 0;
1757 }
1758
1759 if (s->TxStatus[descriptor] & TxHostOwns)
1760 {
1761 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1762 descriptor, s->TxStatus[descriptor]));
1763 return 0;
1764 }
1765
1766 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
1767
1768 int txsize = s->TxStatus[descriptor] & 0x1fff;
1769 uint8_t txbuffer[0x2000];
1770
1771 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1772 txsize, s->TxAddr[descriptor]));
1773
1774 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
1775
1776 /* Mark descriptor as transferred */
1777 s->TxStatus[descriptor] |= TxHostOwns;
1778 s->TxStatus[descriptor] |= TxStatOK;
1779
1780 rtl8139_transfer_frame(s, txbuffer, txsize, 0);
1781
1782 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
1783
1784 /* update interrupt */
1785 s->IntrStatus |= TxOK;
1786 rtl8139_update_irq(s);
1787
1788 return 1;
1789 }
1790
1791 /* structures and macros for task offloading */
1792 typedef struct ip_header
1793 {
1794 uint8_t ip_ver_len; /* version and header length */
1795 uint8_t ip_tos; /* type of service */
1796 uint16_t ip_len; /* total length */
1797 uint16_t ip_id; /* identification */
1798 uint16_t ip_off; /* fragment offset field */
1799 uint8_t ip_ttl; /* time to live */
1800 uint8_t ip_p; /* protocol */
1801 uint16_t ip_sum; /* checksum */
1802 uint32_t ip_src,ip_dst; /* source and dest address */
1803 } ip_header;
1804
1805 #define IP_HEADER_VERSION_4 4
1806 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1807 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1808
1809 typedef struct tcp_header
1810 {
1811 uint16_t th_sport; /* source port */
1812 uint16_t th_dport; /* destination port */
1813 uint32_t th_seq; /* sequence number */
1814 uint32_t th_ack; /* acknowledgement number */
1815 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1816 uint16_t th_win; /* window */
1817 uint16_t th_sum; /* checksum */
1818 uint16_t th_urp; /* urgent pointer */
1819 } tcp_header;
1820
1821 typedef struct udp_header
1822 {
1823 uint16_t uh_sport; /* source port */
1824 uint16_t uh_dport; /* destination port */
1825 uint16_t uh_ulen; /* udp length */
1826 uint16_t uh_sum; /* udp checksum */
1827 } udp_header;
1828
1829 typedef struct ip_pseudo_header
1830 {
1831 uint32_t ip_src;
1832 uint32_t ip_dst;
1833 uint8_t zeros;
1834 uint8_t ip_proto;
1835 uint16_t ip_payload;
1836 } ip_pseudo_header;
1837
1838 #define IP_PROTO_TCP 6
1839 #define IP_PROTO_UDP 17
1840
1841 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1842 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1843 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1844
1845 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1846
1847 #define TCP_FLAG_FIN 0x01
1848 #define TCP_FLAG_PUSH 0x08
1849
1850 /* produces ones' complement sum of data */
1851 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1852 {
1853 uint32_t result = 0;
1854
1855 for (; len > 1; data+=2, len-=2)
1856 {
1857 result += *(uint16_t*)data;
1858 }
1859
1860 /* add the remainder byte */
1861 if (len)
1862 {
1863 uint8_t odd[2] = {*data, 0};
1864 result += *(uint16_t*)odd;
1865 }
1866
1867 while (result>>16)
1868 result = (result & 0xffff) + (result >> 16);
1869
1870 return result;
1871 }
1872
1873 static uint16_t ip_checksum(void *data, size_t len)
1874 {
1875 return ~ones_complement_sum((uint8_t*)data, len);
1876 }
1877
1878 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1879 {
1880 if (!rtl8139_transmitter_enabled(s))
1881 {
1882 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
1883 return 0;
1884 }
1885
1886 if (!rtl8139_cp_transmitter_enabled(s))
1887 {
1888 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
1889 return 0 ;
1890 }
1891
1892 int descriptor = s->currCPlusTxDesc;
1893
1894 target_phys_addr_t cplus_tx_ring_desc =
1895 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1896
1897 /* Normal priority ring */
1898 cplus_tx_ring_desc += 16 * descriptor;
1899
1900 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1901 descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
1902
1903 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1904
1905 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1906 txdw0 = le32_to_cpu(val);
1907 /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
1908 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1909 txdw1 = le32_to_cpu(val);
1910 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1911 txbufLO = le32_to_cpu(val);
1912 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1913 txbufHI = le32_to_cpu(val);
1914
1915 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
1916 descriptor,
1917 txdw0, txdw1, txbufLO, txbufHI));
1918
1919 /* TODO: the following discard cast should clean clang analyzer output */
1920 (void)txdw1;
1921
1922 /* w0 ownership flag */
1923 #define CP_TX_OWN (1<<31)
1924 /* w0 end of ring flag */
1925 #define CP_TX_EOR (1<<30)
1926 /* first segment of received packet flag */
1927 #define CP_TX_FS (1<<29)
1928 /* last segment of received packet flag */
1929 #define CP_TX_LS (1<<28)
1930 /* large send packet flag */
1931 #define CP_TX_LGSEN (1<<27)
1932 /* large send MSS mask, bits 16...25 */
1933 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1934
1935 /* IP checksum offload flag */
1936 #define CP_TX_IPCS (1<<18)
1937 /* UDP checksum offload flag */
1938 #define CP_TX_UDPCS (1<<17)
1939 /* TCP checksum offload flag */
1940 #define CP_TX_TCPCS (1<<16)
1941
1942 /* w0 bits 0...15 : buffer size */
1943 #define CP_TX_BUFFER_SIZE (1<<16)
1944 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1945 /* w1 tag available flag */
1946 #define CP_RX_TAGC (1<<17)
1947 /* w1 bits 0...15 : VLAN tag */
1948 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1949 /* w2 low 32bit of Rx buffer ptr */
1950 /* w3 high 32bit of Rx buffer ptr */
1951
1952 /* set after transmission */
1953 /* FIFO underrun flag */
1954 #define CP_TX_STATUS_UNF (1<<25)
1955 /* transmit error summary flag, valid if set any of three below */
1956 #define CP_TX_STATUS_TES (1<<23)
1957 /* out-of-window collision flag */
1958 #define CP_TX_STATUS_OWC (1<<22)
1959 /* link failure flag */
1960 #define CP_TX_STATUS_LNKF (1<<21)
1961 /* excessive collisions flag */
1962 #define CP_TX_STATUS_EXC (1<<20)
1963
1964 if (!(txdw0 & CP_TX_OWN))
1965 {
1966 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
1967 return 0 ;
1968 }
1969
1970 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
1971
1972 if (txdw0 & CP_TX_FS)
1973 {
1974 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
1975
1976 /* reset internal buffer offset */
1977 s->cplus_txbuffer_offset = 0;
1978 }
1979
1980 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
1981 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
1982
1983 /* make sure we have enough space to assemble the packet */
1984 if (!s->cplus_txbuffer)
1985 {
1986 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
1987 s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len);
1988 s->cplus_txbuffer_offset = 0;
1989
1990 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
1991 }
1992
1993 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
1994 {
1995 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
1996 s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
1997
1998 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
1999 }
2000
2001 if (!s->cplus_txbuffer)
2002 {
2003 /* out of memory */
2004
2005 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2006
2007 /* update tally counter */
2008 ++s->tally_counters.TxERR;
2009 ++s->tally_counters.TxAbt;
2010
2011 return 0;
2012 }
2013
2014 /* append more data to the packet */
2015
2016 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
2017 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
2018
2019 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2020 s->cplus_txbuffer_offset += txsize;
2021
2022 /* seek to next Rx descriptor */
2023 if (txdw0 & CP_TX_EOR)
2024 {
2025 s->currCPlusTxDesc = 0;
2026 }
2027 else
2028 {
2029 ++s->currCPlusTxDesc;
2030 if (s->currCPlusTxDesc >= 64)
2031 s->currCPlusTxDesc = 0;
2032 }
2033
2034 /* transfer ownership to target */
2035 txdw0 &= ~CP_RX_OWN;
2036
2037 /* reset error indicator bits */
2038 txdw0 &= ~CP_TX_STATUS_UNF;
2039 txdw0 &= ~CP_TX_STATUS_TES;
2040 txdw0 &= ~CP_TX_STATUS_OWC;
2041 txdw0 &= ~CP_TX_STATUS_LNKF;
2042 txdw0 &= ~CP_TX_STATUS_EXC;
2043
2044 /* update ring data */
2045 val = cpu_to_le32(txdw0);
2046 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
2047 /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
2048 // val = cpu_to_le32(txdw1);
2049 // cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2050
2051 /* Now decide if descriptor being processed is holding the last segment of packet */
2052 if (txdw0 & CP_TX_LS)
2053 {
2054 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2055
2056 /* can transfer fully assembled packet */
2057
2058 uint8_t *saved_buffer = s->cplus_txbuffer;
2059 int saved_size = s->cplus_txbuffer_offset;
2060 int saved_buffer_len = s->cplus_txbuffer_len;
2061
2062 /* reset the card space to protect from recursive call */
2063 s->cplus_txbuffer = NULL;
2064 s->cplus_txbuffer_offset = 0;
2065 s->cplus_txbuffer_len = 0;
2066
2067 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2068 {
2069 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2070
2071 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2072 #define ETH_HLEN 14
2073 #define ETH_MTU 1500
2074
2075 /* ip packet header */
2076 ip_header *ip = NULL;
2077 int hlen = 0;
2078 uint8_t ip_protocol = 0;
2079 uint16_t ip_data_len = 0;
2080
2081 uint8_t *eth_payload_data = NULL;
2082 size_t eth_payload_len = 0;
2083
2084 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2085 if (proto == ETH_P_IP)
2086 {
2087 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2088
2089 /* not aligned */
2090 eth_payload_data = saved_buffer + ETH_HLEN;
2091 eth_payload_len = saved_size - ETH_HLEN;
2092
2093 ip = (ip_header*)eth_payload_data;
2094
2095 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2096 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
2097 ip = NULL;
2098 } else {
2099 hlen = IP_HEADER_LENGTH(ip);
2100 ip_protocol = ip->ip_p;
2101 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
2102 }
2103 }
2104
2105 if (ip)
2106 {
2107 if (txdw0 & CP_TX_IPCS)
2108 {
2109 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2110
2111 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
2112 /* bad packet header len */
2113 /* or packet too short */
2114 }
2115 else
2116 {
2117 ip->ip_sum = 0;
2118 ip->ip_sum = ip_checksum(ip, hlen);
2119 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2120 }
2121 }
2122
2123 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2124 {
2125 #if defined (DEBUG_RTL8139)
2126 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2127 #endif
2128 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2129 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
2130
2131 int tcp_send_offset = 0;
2132 int send_count = 0;
2133
2134 /* maximum IP header length is 60 bytes */
2135 uint8_t saved_ip_header[60];
2136
2137 /* save IP header template; data area is used in tcp checksum calculation */
2138 memcpy(saved_ip_header, eth_payload_data, hlen);
2139
2140 /* a placeholder for checksum calculation routine in tcp case */
2141 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2142 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2143
2144 /* pointer to TCP header */
2145 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2146
2147 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2148
2149 /* ETH_MTU = ip header len + tcp header len + payload */
2150 int tcp_data_len = ip_data_len - tcp_hlen;
2151 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2152
2153 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2154 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2155
2156 /* note the cycle below overwrites IP header data,
2157 but restores it from saved_ip_header before sending packet */
2158
2159 int is_last_frame = 0;
2160
2161 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2162 {
2163 uint16_t chunk_size = tcp_chunk_size;
2164
2165 /* check if this is the last frame */
2166 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2167 {
2168 is_last_frame = 1;
2169 chunk_size = tcp_data_len - tcp_send_offset;
2170 }
2171
2172 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2173
2174 /* add 4 TCP pseudoheader fields */
2175 /* copy IP source and destination fields */
2176 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2177
2178 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2179
2180 if (tcp_send_offset)
2181 {
2182 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2183 }
2184
2185 /* keep PUSH and FIN flags only for the last frame */
2186 if (!is_last_frame)
2187 {
2188 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2189 }
2190
2191 /* recalculate TCP checksum */
2192 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2193 p_tcpip_hdr->zeros = 0;
2194 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2195 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2196
2197 p_tcp_hdr->th_sum = 0;
2198
2199 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2200 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2201
2202 p_tcp_hdr->th_sum = tcp_checksum;
2203
2204 /* restore IP header */
2205 memcpy(eth_payload_data, saved_ip_header, hlen);
2206
2207 /* set IP data length and recalculate IP checksum */
2208 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2209
2210 /* increment IP id for subsequent frames */
2211 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2212
2213 ip->ip_sum = 0;
2214 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2215 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2216
2217 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2218 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
2219 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
2220
2221 /* add transferred count to TCP sequence number */
2222 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2223 ++send_count;
2224 }
2225
2226 /* Stop sending this frame */
2227 saved_size = 0;
2228 }
2229 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2230 {
2231 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2232
2233 /* maximum IP header length is 60 bytes */
2234 uint8_t saved_ip_header[60];
2235 memcpy(saved_ip_header, eth_payload_data, hlen);
2236
2237 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2238 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2239
2240 /* add 4 TCP pseudoheader fields */
2241 /* copy IP source and destination fields */
2242 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2243
2244 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2245 {
2246 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2247
2248 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2249 p_tcpip_hdr->zeros = 0;
2250 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2251 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2252
2253 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2254
2255 p_tcp_hdr->th_sum = 0;
2256
2257 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2258 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2259
2260 p_tcp_hdr->th_sum = tcp_checksum;
2261 }
2262 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2263 {
2264 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2265
2266 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2267 p_udpip_hdr->zeros = 0;
2268 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2269 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2270
2271 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2272
2273 p_udp_hdr->uh_sum = 0;
2274
2275 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2276 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2277
2278 p_udp_hdr->uh_sum = udp_checksum;
2279 }
2280
2281 /* restore IP header */
2282 memcpy(eth_payload_data, saved_ip_header, hlen);
2283 }
2284 }
2285 }
2286
2287 /* update tally counter */
2288 ++s->tally_counters.TxOk;
2289
2290 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2291
2292 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
2293
2294 /* restore card space if there was no recursion and reset offset */
2295 if (!s->cplus_txbuffer)
2296 {
2297 s->cplus_txbuffer = saved_buffer;
2298 s->cplus_txbuffer_len = saved_buffer_len;
2299 s->cplus_txbuffer_offset = 0;
2300 }
2301 else
2302 {
2303 qemu_free(saved_buffer);
2304 }
2305 }
2306 else
2307 {
2308 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
2309 }
2310
2311 return 1;
2312 }
2313
2314 static void rtl8139_cplus_transmit(RTL8139State *s)
2315 {
2316 int txcount = 0;
2317
2318 while (rtl8139_cplus_transmit_one(s))
2319 {
2320 ++txcount;
2321 }
2322
2323 /* Mark transfer completed */
2324 if (!txcount)
2325 {
2326 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2327 s->currCPlusTxDesc));
2328 }
2329 else
2330 {
2331 /* update interrupt status */
2332 s->IntrStatus |= TxOK;
2333 rtl8139_update_irq(s);
2334 }
2335 }
2336
2337 static void rtl8139_transmit(RTL8139State *s)
2338 {
2339 int descriptor = s->currTxDesc, txcount = 0;
2340
2341 /*while*/
2342 if (rtl8139_transmit_one(s, descriptor))
2343 {
2344 ++s->currTxDesc;
2345 s->currTxDesc %= 4;
2346 ++txcount;
2347 }
2348
2349 /* Mark transfer completed */
2350 if (!txcount)
2351 {
2352 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
2353 }
2354 }
2355
2356 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2357 {
2358
2359 int descriptor = txRegOffset/4;
2360
2361 /* handle C+ transmit mode register configuration */
2362
2363 if (s->cplus_enabled)
2364 {
2365 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2366
2367 /* handle Dump Tally Counters command */
2368 s->TxStatus[descriptor] = val;
2369
2370 if (descriptor == 0 && (val & 0x8))
2371 {
2372 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2373
2374 /* dump tally counters to specified memory location */
2375 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2376
2377 /* mark dump completed */
2378 s->TxStatus[0] &= ~0x8;
2379 }
2380
2381 return;
2382 }
2383
2384 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2385
2386 /* mask only reserved bits */
2387 val &= ~0xff00c000; /* these bits are reset on write */
2388 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2389
2390 s->TxStatus[descriptor] = val;
2391
2392 /* attempt to start transmission */
2393 rtl8139_transmit(s);
2394 }
2395
2396 static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2397 {
2398 uint32_t ret = s->TxStatus[txRegOffset/4];
2399
2400 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
2401
2402 return ret;
2403 }
2404
2405 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2406 {
2407 uint16_t ret = 0;
2408
2409 /* Simulate TSAD, it is read only anyway */
2410
2411 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2412 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2413 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2414 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2415
2416 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2417 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2418 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2419 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2420
2421 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2422 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2423 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2424 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2425
2426 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2427 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2428 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2429 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2430
2431
2432 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
2433
2434 return ret;
2435 }
2436
2437 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2438 {
2439 uint16_t ret = s->CSCR;
2440
2441 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
2442
2443 return ret;
2444 }
2445
2446 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2447 {
2448 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
2449
2450 s->TxAddr[txAddrOffset/4] = val;
2451 }
2452
2453 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2454 {
2455 uint32_t ret = s->TxAddr[txAddrOffset/4];
2456
2457 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
2458
2459 return ret;
2460 }
2461
2462 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2463 {
2464 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
2465
2466 /* this value is off by 16 */
2467 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2468
2469 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2470 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
2471 }
2472
2473 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2474 {
2475 /* this value is off by 16 */
2476 uint32_t ret = s->RxBufPtr - 0x10;
2477
2478 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2479
2480 return ret;
2481 }
2482
2483 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2484 {
2485 /* this value is NOT off by 16 */
2486 uint32_t ret = s->RxBufAddr;
2487
2488 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
2489
2490 return ret;
2491 }
2492
2493 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2494 {
2495 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
2496
2497 s->RxBuf = val;
2498
2499 /* may need to reset rxring here */
2500 }
2501
2502 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2503 {
2504 uint32_t ret = s->RxBuf;
2505
2506 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
2507
2508 return ret;
2509 }
2510
2511 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2512 {
2513 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
2514
2515 /* mask unwriteable bits */
2516 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2517
2518 s->IntrMask = val;
2519
2520 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2521 rtl8139_update_irq(s);
2522
2523 }
2524
2525 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2526 {
2527 uint32_t ret = s->IntrMask;
2528
2529 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
2530
2531 return ret;
2532 }
2533
2534 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2535 {
2536 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
2537
2538 #if 0
2539
2540 /* writing to ISR has no effect */
2541
2542 return;
2543
2544 #else
2545 uint16_t newStatus = s->IntrStatus & ~val;
2546
2547 /* mask unwriteable bits */
2548 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2549
2550 /* writing 1 to interrupt status register bit clears it */
2551 s->IntrStatus = 0;
2552 rtl8139_update_irq(s);
2553
2554 s->IntrStatus = newStatus;
2555 /*
2556 * Computing if we miss an interrupt here is not that correct but
2557 * considered that we should have had already an interrupt
2558 * and probably emulated is slower is better to assume this resetting was
2559 * done before testing on previous rtl8139_update_irq lead to IRQ loosing
2560 */
2561 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2562 rtl8139_update_irq(s);
2563
2564 #endif
2565 }
2566
2567 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2568 {
2569 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2570
2571 uint32_t ret = s->IntrStatus;
2572
2573 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
2574
2575 #if 0
2576
2577 /* reading ISR clears all interrupts */
2578 s->IntrStatus = 0;
2579
2580 rtl8139_update_irq(s);
2581
2582 #endif
2583
2584 return ret;
2585 }
2586
2587 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2588 {
2589 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
2590
2591 /* mask unwriteable bits */
2592 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2593
2594 s->MultiIntr = val;
2595 }
2596
2597 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2598 {
2599 uint32_t ret = s->MultiIntr;
2600
2601 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
2602
2603 return ret;
2604 }
2605
2606 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2607 {
2608 RTL8139State *s = opaque;
2609
2610 addr &= 0xff;
2611
2612 switch (addr)
2613 {
2614 case MAC0 ... MAC0+5:
2615 s->phys[addr - MAC0] = val;
2616 break;
2617 case MAC0+6 ... MAC0+7:
2618 /* reserved */
2619 break;
2620 case MAR0 ... MAR0+7:
2621 s->mult[addr - MAR0] = val;
2622 break;
2623 case ChipCmd:
2624 rtl8139_ChipCmd_write(s, val);
2625 break;
2626 case Cfg9346:
2627 rtl8139_Cfg9346_write(s, val);
2628 break;
2629 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2630 rtl8139_TxConfig_writeb(s, val);
2631 break;
2632 case Config0:
2633 rtl8139_Config0_write(s, val);
2634 break;
2635 case Config1:
2636 rtl8139_Config1_write(s, val);
2637 break;
2638 case Config3:
2639 rtl8139_Config3_write(s, val);
2640 break;
2641 case Config4:
2642 rtl8139_Config4_write(s, val);
2643 break;
2644 case Config5:
2645 rtl8139_Config5_write(s, val);
2646 break;
2647 case MediaStatus:
2648 /* ignore */
2649 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
2650 break;
2651
2652 case HltClk:
2653 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
2654 if (val == 'R')
2655 {
2656 s->clock_enabled = 1;
2657 }
2658 else if (val == 'H')
2659 {
2660 s->clock_enabled = 0;
2661 }
2662 break;
2663
2664 case TxThresh:
2665 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
2666 s->TxThresh = val;
2667 break;
2668
2669 case TxPoll:
2670 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
2671 if (val & (1 << 7))
2672 {
2673 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
2674 //rtl8139_cplus_transmit(s);
2675 }
2676 if (val & (1 << 6))
2677 {
2678 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
2679 rtl8139_cplus_transmit(s);
2680 }
2681
2682 break;
2683
2684 default:
2685 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
2686 break;
2687 }
2688 }
2689
2690 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2691 {
2692 RTL8139State *s = opaque;
2693
2694 addr &= 0xfe;
2695
2696 switch (addr)
2697 {
2698 case IntrMask:
2699 rtl8139_IntrMask_write(s, val);
2700 break;
2701
2702 case IntrStatus:
2703 rtl8139_IntrStatus_write(s, val);
2704 break;
2705
2706 case MultiIntr:
2707 rtl8139_MultiIntr_write(s, val);
2708 break;
2709
2710 case RxBufPtr:
2711 rtl8139_RxBufPtr_write(s, val);
2712 break;
2713
2714 case BasicModeCtrl:
2715 rtl8139_BasicModeCtrl_write(s, val);
2716 break;
2717 case BasicModeStatus:
2718 rtl8139_BasicModeStatus_write(s, val);
2719 break;
2720 case NWayAdvert:
2721 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
2722 s->NWayAdvert = val;
2723 break;
2724 case NWayLPAR:
2725 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
2726 break;
2727 case NWayExpansion:
2728 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
2729 s->NWayExpansion = val;
2730 break;
2731
2732 case CpCmd:
2733 rtl8139_CpCmd_write(s, val);
2734 break;
2735
2736 case IntrMitigate:
2737 rtl8139_IntrMitigate_write(s, val);
2738 break;
2739
2740 default:
2741 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
2742
2743 rtl8139_io_writeb(opaque, addr, val & 0xff);
2744 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2745 break;
2746 }
2747 }
2748
2749 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2750 {
2751 int64_t pci_time, next_time;
2752 uint32_t low_pci;
2753
2754 DEBUG_PRINT(("RTL8139: entered rtl8139_set_next_tctr_time\n"));
2755
2756 if (s->TimerExpire && current_time >= s->TimerExpire) {
2757 s->IntrStatus |= PCSTimeout;
2758 rtl8139_update_irq(s);
2759 }
2760
2761 /* Set QEMU timer only if needed that is
2762 * - TimerInt <> 0 (we have a timer)
2763 * - mask = 1 (we want an interrupt timer)
2764 * - irq = 0 (irq is not already active)
2765 * If any of above change we need to compute timer again
2766 * Also we must check if timer is passed without QEMU timer
2767 */
2768 s->TimerExpire = 0;
2769 if (!s->TimerInt) {
2770 return;
2771 }
2772
2773 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2774 get_ticks_per_sec());
2775 low_pci = pci_time & 0xffffffff;
2776 pci_time = pci_time - low_pci + s->TimerInt;
2777 if (low_pci >= s->TimerInt) {
2778 pci_time += 0x100000000LL;
2779 }
2780 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2781 PCI_FREQUENCY);
2782 s->TimerExpire = next_time;
2783
2784 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2785 qemu_mod_timer(s->timer, next_time);
2786 }
2787 }
2788
2789 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2790 {
2791 RTL8139State *s = opaque;
2792
2793 addr &= 0xfc;
2794
2795 switch (addr)
2796 {
2797 case RxMissed:
2798 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
2799 s->RxMissed = 0;
2800 break;
2801
2802 case TxConfig:
2803 rtl8139_TxConfig_write(s, val);
2804 break;
2805
2806 case RxConfig:
2807 rtl8139_RxConfig_write(s, val);
2808 break;
2809
2810 case TxStatus0 ... TxStatus0+4*4-1:
2811 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2812 break;
2813
2814 case TxAddr0 ... TxAddr0+4*4-1:
2815 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2816 break;
2817
2818 case RxBuf:
2819 rtl8139_RxBuf_write(s, val);
2820 break;
2821
2822 case RxRingAddrLO:
2823 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
2824 s->RxRingAddrLO = val;
2825 break;
2826
2827 case RxRingAddrHI:
2828 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
2829 s->RxRingAddrHI = val;
2830 break;
2831
2832 case Timer:
2833 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2834 s->TCTR_base = qemu_get_clock_ns(vm_clock);
2835 rtl8139_set_next_tctr_time(s, s->TCTR_base);
2836 break;
2837
2838 case FlashReg:
2839 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
2840 if (s->TimerInt != val) {
2841 s->TimerInt = val;
2842 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2843 }
2844 break;
2845
2846 default:
2847 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
2848 rtl8139_io_writeb(opaque, addr, val & 0xff);
2849 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2850 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2851 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2852 break;
2853 }
2854 }
2855
2856 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2857 {
2858 RTL8139State *s = opaque;
2859 int ret;
2860
2861 addr &= 0xff;
2862
2863 switch (addr)
2864 {
2865 case MAC0 ... MAC0+5:
2866 ret = s->phys[addr - MAC0];
2867 break;
2868 case MAC0+6 ... MAC0+7:
2869 ret = 0;
2870 break;
2871 case MAR0 ... MAR0+7:
2872 ret = s->mult[addr - MAR0];
2873 break;
2874 case ChipCmd:
2875 ret = rtl8139_ChipCmd_read(s);
2876 break;
2877 case Cfg9346:
2878 ret = rtl8139_Cfg9346_read(s);
2879 break;
2880 case Config0:
2881 ret = rtl8139_Config0_read(s);
2882 break;
2883 case Config1:
2884 ret = rtl8139_Config1_read(s);
2885 break;
2886 case Config3:
2887 ret = rtl8139_Config3_read(s);
2888 break;
2889 case Config4:
2890 ret = rtl8139_Config4_read(s);
2891 break;
2892 case Config5:
2893 ret = rtl8139_Config5_read(s);
2894 break;
2895
2896 case MediaStatus:
2897 ret = 0xd0;
2898 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
2899 break;
2900
2901 case HltClk:
2902 ret = s->clock_enabled;
2903 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
2904 break;
2905
2906 case PCIRevisionID:
2907 ret = RTL8139_PCI_REVID;
2908 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
2909 break;
2910
2911 case TxThresh:
2912 ret = s->TxThresh;
2913 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
2914 break;
2915
2916 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2917 ret = s->TxConfig >> 24;
2918 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
2919 break;
2920
2921 default:
2922 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
2923 ret = 0;
2924 break;
2925 }
2926
2927 return ret;
2928 }
2929
2930 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2931 {
2932 RTL8139State *s = opaque;
2933 uint32_t ret;
2934
2935 addr &= 0xfe; /* mask lower bit */
2936
2937 switch (addr)
2938 {
2939 case IntrMask:
2940 ret = rtl8139_IntrMask_read(s);
2941 break;
2942
2943 case IntrStatus:
2944 ret = rtl8139_IntrStatus_read(s);
2945 break;
2946
2947 case MultiIntr:
2948 ret = rtl8139_MultiIntr_read(s);
2949 break;
2950
2951 case RxBufPtr:
2952 ret = rtl8139_RxBufPtr_read(s);
2953 break;
2954
2955 case RxBufAddr:
2956 ret = rtl8139_RxBufAddr_read(s);
2957 break;
2958
2959 case BasicModeCtrl:
2960 ret = rtl8139_BasicModeCtrl_read(s);
2961 break;
2962 case BasicModeStatus:
2963 ret = rtl8139_BasicModeStatus_read(s);
2964 break;
2965 case NWayAdvert:
2966 ret = s->NWayAdvert;
2967 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
2968 break;
2969 case NWayLPAR:
2970 ret = s->NWayLPAR;
2971 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
2972 break;
2973 case NWayExpansion:
2974 ret = s->NWayExpansion;
2975 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
2976 break;
2977
2978 case CpCmd:
2979 ret = rtl8139_CpCmd_read(s);
2980 break;
2981
2982 case IntrMitigate:
2983 ret = rtl8139_IntrMitigate_read(s);
2984 break;
2985
2986 case TxSummary:
2987 ret = rtl8139_TSAD_read(s);
2988 break;
2989
2990 case CSCR:
2991 ret = rtl8139_CSCR_read(s);
2992 break;
2993
2994 default:
2995 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
2996
2997 ret = rtl8139_io_readb(opaque, addr);
2998 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
2999
3000 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
3001 break;
3002 }
3003
3004 return ret;
3005 }
3006
3007 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3008 {
3009 RTL8139State *s = opaque;
3010 uint32_t ret;
3011
3012 addr &= 0xfc; /* also mask low 2 bits */
3013
3014 switch (addr)
3015 {
3016 case RxMissed:
3017 ret = s->RxMissed;
3018
3019 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
3020 break;
3021
3022 case TxConfig:
3023 ret = rtl8139_TxConfig_read(s);
3024 break;
3025
3026 case RxConfig:
3027 ret = rtl8139_RxConfig_read(s);
3028 break;
3029
3030 case TxStatus0 ... TxStatus0+4*4-1:
3031 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
3032 break;
3033
3034 case TxAddr0 ... TxAddr0+4*4-1:
3035 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3036 break;
3037
3038 case RxBuf:
3039 ret = rtl8139_RxBuf_read(s);
3040 break;
3041
3042 case RxRingAddrLO:
3043 ret = s->RxRingAddrLO;
3044 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
3045 break;
3046
3047 case RxRingAddrHI:
3048 ret = s->RxRingAddrHI;
3049 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3050 break;
3051
3052 case Timer:
3053 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
3054 PCI_FREQUENCY, get_ticks_per_sec());
3055 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3056 break;
3057
3058 case FlashReg:
3059 ret = s->TimerInt;
3060 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
3061 break;
3062
3063 default:
3064 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
3065
3066 ret = rtl8139_io_readb(opaque, addr);
3067 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3068 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3069 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3070
3071 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
3072 break;
3073 }
3074
3075 return ret;
3076 }
3077
3078 /* */
3079
3080 static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3081 {
3082 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3083 }
3084
3085 static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3086 {
3087 rtl8139_io_writew(opaque, addr & 0xFF, val);
3088 }
3089
3090 static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3091 {
3092 rtl8139_io_writel(opaque, addr & 0xFF, val);
3093 }
3094
3095 static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3096 {
3097 return rtl8139_io_readb(opaque, addr & 0xFF);
3098 }
3099
3100 static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3101 {
3102 return rtl8139_io_readw(opaque, addr & 0xFF);
3103 }
3104
3105 static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3106 {
3107 return rtl8139_io_readl(opaque, addr & 0xFF);
3108 }
3109
3110 /* */
3111
3112 static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3113 {
3114 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3115 }
3116
3117 static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3118 {
3119 rtl8139_io_writew(opaque, addr & 0xFF, val);
3120 }
3121
3122 static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3123 {
3124 rtl8139_io_writel(opaque, addr & 0xFF, val);
3125 }
3126
3127 static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3128 {
3129 return rtl8139_io_readb(opaque, addr & 0xFF);
3130 }
3131
3132 static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3133 {
3134 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
3135 return val;
3136 }
3137
3138 static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3139 {
3140 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
3141 return val;
3142 }
3143
3144 static int rtl8139_post_load(void *opaque, int version_id)
3145 {
3146 RTL8139State* s = opaque;
3147 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3148 if (version_id < 4) {
3149 s->cplus_enabled = s->CpCmd != 0;
3150 }
3151
3152 return 0;
3153 }
3154
3155 static bool rtl8139_hotplug_ready_needed(void *opaque)
3156 {
3157 return qdev_machine_modified();
3158 }
3159
3160 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3161 .name = "rtl8139/hotplug_ready",
3162 .version_id = 1,
3163 .minimum_version_id = 1,
3164 .minimum_version_id_old = 1,
3165 .fields = (VMStateField []) {
3166 VMSTATE_END_OF_LIST()
3167 }
3168 };
3169
3170 static void rtl8139_pre_save(void *opaque)
3171 {
3172 RTL8139State* s = opaque;
3173 int64_t current_time = qemu_get_clock_ns(vm_clock);
3174
3175 /* set IntrStatus correctly */
3176 rtl8139_set_next_tctr_time(s, current_time);
3177 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3178 get_ticks_per_sec());
3179 s->rtl8139_mmio_io_addr_dummy = s->rtl8139_mmio_io_addr;
3180 }
3181
3182 static const VMStateDescription vmstate_rtl8139 = {
3183 .name = "rtl8139",
3184 .version_id = 4,
3185 .minimum_version_id = 3,
3186 .minimum_version_id_old = 3,
3187 .post_load = rtl8139_post_load,
3188 .pre_save = rtl8139_pre_save,
3189 .fields = (VMStateField []) {
3190 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3191 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3192 VMSTATE_BUFFER(mult, RTL8139State),
3193 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3194 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3195
3196 VMSTATE_UINT32(RxBuf, RTL8139State),
3197 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3198 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3199 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3200
3201 VMSTATE_UINT16(IntrStatus, RTL8139State),
3202 VMSTATE_UINT16(IntrMask, RTL8139State),
3203
3204 VMSTATE_UINT32(TxConfig, RTL8139State),
3205 VMSTATE_UINT32(RxConfig, RTL8139State),
3206 VMSTATE_UINT32(RxMissed, RTL8139State),
3207 VMSTATE_UINT16(CSCR, RTL8139State),
3208
3209 VMSTATE_UINT8(Cfg9346, RTL8139State),
3210 VMSTATE_UINT8(Config0, RTL8139State),
3211 VMSTATE_UINT8(Config1, RTL8139State),
3212 VMSTATE_UINT8(Config3, RTL8139State),
3213 VMSTATE_UINT8(Config4, RTL8139State),
3214 VMSTATE_UINT8(Config5, RTL8139State),
3215
3216 VMSTATE_UINT8(clock_enabled, RTL8139State),
3217 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3218
3219 VMSTATE_UINT16(MultiIntr, RTL8139State),
3220
3221 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3222 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3223 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3224 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3225 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3226
3227 VMSTATE_UINT16(CpCmd, RTL8139State),
3228 VMSTATE_UINT8(TxThresh, RTL8139State),
3229
3230 VMSTATE_UNUSED(4),
3231 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
3232 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
3233
3234 VMSTATE_UINT32(currTxDesc, RTL8139State),
3235 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3236 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3237 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3238 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3239
3240 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3241 VMSTATE_INT32(eeprom.mode, RTL8139State),
3242 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3243 VMSTATE_UINT8(eeprom.address, RTL8139State),
3244 VMSTATE_UINT16(eeprom.input, RTL8139State),
3245 VMSTATE_UINT16(eeprom.output, RTL8139State),
3246
3247 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3248 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3249 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3250 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3251
3252 VMSTATE_UINT32(TCTR, RTL8139State),
3253 VMSTATE_UINT32(TimerInt, RTL8139State),
3254 VMSTATE_INT64(TCTR_base, RTL8139State),
3255
3256 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3257 vmstate_tally_counters, RTL8139TallyCounters),
3258
3259 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3260 VMSTATE_END_OF_LIST()
3261 },
3262 .subsections = (VMStateSubsection []) {
3263 {
3264 .vmsd = &vmstate_rtl8139_hotplug_ready,
3265 .needed = rtl8139_hotplug_ready_needed,
3266 }, {
3267 /* empty */
3268 }
3269 }
3270 };
3271
3272 /***********************************************************/
3273 /* PCI RTL8139 definitions */
3274
3275 static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
3276 pcibus_t addr, pcibus_t size, int type)
3277 {
3278 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
3279
3280 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3281 }
3282
3283 static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
3284 pcibus_t addr, pcibus_t size, int type)
3285 {
3286 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
3287
3288 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3289 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3290
3291 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3292 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3293
3294 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3295 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3296 }
3297
3298 static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
3299 rtl8139_mmio_readb,
3300 rtl8139_mmio_readw,
3301 rtl8139_mmio_readl,
3302 };
3303
3304 static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
3305 rtl8139_mmio_writeb,
3306 rtl8139_mmio_writew,
3307 rtl8139_mmio_writel,
3308 };
3309
3310 static void rtl8139_timer(void *opaque)
3311 {
3312 RTL8139State *s = opaque;
3313
3314 if (!s->clock_enabled)
3315 {
3316 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3317 return;
3318 }
3319
3320 s->IntrStatus |= PCSTimeout;
3321 rtl8139_update_irq(s);
3322 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3323 }
3324
3325 static void rtl8139_cleanup(VLANClientState *nc)
3326 {
3327 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
3328
3329 s->nic = NULL;
3330 }
3331
3332 static int pci_rtl8139_uninit(PCIDevice *dev)
3333 {
3334 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3335
3336 cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
3337 if (s->cplus_txbuffer) {
3338 qemu_free(s->cplus_txbuffer);
3339 s->cplus_txbuffer = NULL;
3340 }
3341 qemu_del_timer(s->timer);
3342 qemu_free_timer(s->timer);
3343 qemu_del_vlan_client(&s->nic->nc);
3344 return 0;
3345 }
3346
3347 static NetClientInfo net_rtl8139_info = {
3348 .type = NET_CLIENT_TYPE_NIC,
3349 .size = sizeof(NICState),
3350 .can_receive = rtl8139_can_receive,
3351 .receive = rtl8139_receive,
3352 .cleanup = rtl8139_cleanup,
3353 };
3354
3355 static int pci_rtl8139_init(PCIDevice *dev)
3356 {
3357 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
3358 uint8_t *pci_conf;
3359
3360 pci_conf = s->dev.config;
3361 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
3362 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
3363 pci_conf[PCI_REVISION_ID] = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3364 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
3365 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
3366 /* TODO: start of capability list, but no capability
3367 * list bit in status register, and offset 0xdc seems unused. */
3368 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
3369
3370 /* I/O handler for memory-mapped I/O */
3371 s->rtl8139_mmio_io_addr =
3372 cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s,
3373 DEVICE_LITTLE_ENDIAN);
3374
3375 pci_register_bar(&s->dev, 0, 0x100,
3376 PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map);
3377
3378 pci_register_bar(&s->dev, 1, 0x100,
3379 PCI_BASE_ADDRESS_SPACE_MEMORY, rtl8139_mmio_map);
3380
3381 qemu_macaddr_default_if_unset(&s->conf.macaddr);
3382
3383 /* prepare eeprom */
3384 s->eeprom.contents[0] = 0x8129;
3385 #if 1
3386 /* PCI vendor and device ID should be mirrored here */
3387 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3388 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3389 #endif
3390 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3391 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3392 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3393
3394 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3395 dev->qdev.info->name, dev->qdev.id, s);
3396 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
3397
3398 s->cplus_txbuffer = NULL;
3399 s->cplus_txbuffer_len = 0;
3400 s->cplus_txbuffer_offset = 0;
3401
3402 s->TimerExpire = 0;
3403 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
3404 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3405
3406 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3407
3408 return 0;
3409 }
3410
3411 static PCIDeviceInfo rtl8139_info = {
3412 .qdev.name = "rtl8139",
3413 .qdev.size = sizeof(RTL8139State),
3414 .qdev.reset = rtl8139_reset,
3415 .qdev.vmsd = &vmstate_rtl8139,
3416 .init = pci_rtl8139_init,
3417 .exit = pci_rtl8139_uninit,
3418 .romfile = "pxe-rtl8139.bin",
3419 .qdev.props = (Property[]) {
3420 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3421 DEFINE_PROP_END_OF_LIST(),
3422 }
3423 };
3424
3425 static void rtl8139_register_devices(void)
3426 {
3427 pci_qdev_register(&rtl8139_info);
3428 }
3429
3430 device_init(rtl8139_register_devices)
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