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1 /**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
49 */
50
51 /* For crc32 */
52 #include <zlib.h>
53
54 #include "hw.h"
55 #include "pci.h"
56 #include "qemu-timer.h"
57 #include "net.h"
58 #include "loader.h"
59 #include "sysemu.h"
60 #include "iov.h"
61
62 /* debug RTL8139 card */
63 //#define DEBUG_RTL8139 1
64
65 #define PCI_FREQUENCY 33000000L
66
67 /* debug RTL8139 card C+ mode only */
68 //#define DEBUG_RTL8139CP 1
69
70 #define SET_MASKED(input, mask, curr) \
71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
72
73 /* arg % size for size which is a power of 2 */
74 #define MOD2(input, size) \
75 ( ( input ) & ( size - 1 ) )
76
77 #define ETHER_ADDR_LEN 6
78 #define ETHER_TYPE_LEN 2
79 #define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
80 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
81 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
82 #define ETH_MTU 1500
83
84 #define VLAN_TCI_LEN 2
85 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
86
87 #if defined (DEBUG_RTL8139)
88 # define DEBUG_PRINT(x) do { printf x ; } while (0)
89 #else
90 # define DEBUG_PRINT(x)
91 #endif
92
93 /* Symbolic offsets to registers. */
94 enum RTL8139_registers {
95 MAC0 = 0, /* Ethernet hardware address. */
96 MAR0 = 8, /* Multicast filter. */
97 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
98 /* Dump Tally Conter control register(64bit). C+ mode only */
99 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
100 RxBuf = 0x30,
101 ChipCmd = 0x37,
102 RxBufPtr = 0x38,
103 RxBufAddr = 0x3A,
104 IntrMask = 0x3C,
105 IntrStatus = 0x3E,
106 TxConfig = 0x40,
107 RxConfig = 0x44,
108 Timer = 0x48, /* A general-purpose counter. */
109 RxMissed = 0x4C, /* 24 bits valid, write clears. */
110 Cfg9346 = 0x50,
111 Config0 = 0x51,
112 Config1 = 0x52,
113 FlashReg = 0x54,
114 MediaStatus = 0x58,
115 Config3 = 0x59,
116 Config4 = 0x5A, /* absent on RTL-8139A */
117 HltClk = 0x5B,
118 MultiIntr = 0x5C,
119 PCIRevisionID = 0x5E,
120 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
121 BasicModeCtrl = 0x62,
122 BasicModeStatus = 0x64,
123 NWayAdvert = 0x66,
124 NWayLPAR = 0x68,
125 NWayExpansion = 0x6A,
126 /* Undocumented registers, but required for proper operation. */
127 FIFOTMS = 0x70, /* FIFO Control and test. */
128 CSCR = 0x74, /* Chip Status and Configuration Register. */
129 PARA78 = 0x78,
130 PARA7c = 0x7c, /* Magic transceiver parameter register. */
131 Config5 = 0xD8, /* absent on RTL-8139A */
132 /* C+ mode */
133 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
134 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
135 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
136 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
137 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
138 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
139 TxThresh = 0xEC, /* Early Tx threshold */
140 };
141
142 enum ClearBitMasks {
143 MultiIntrClear = 0xF000,
144 ChipCmdClear = 0xE2,
145 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
146 };
147
148 enum ChipCmdBits {
149 CmdReset = 0x10,
150 CmdRxEnb = 0x08,
151 CmdTxEnb = 0x04,
152 RxBufEmpty = 0x01,
153 };
154
155 /* C+ mode */
156 enum CplusCmdBits {
157 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
158 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
159 CPlusRxEnb = 0x0002,
160 CPlusTxEnb = 0x0001,
161 };
162
163 /* Interrupt register bits, using my own meaningful names. */
164 enum IntrStatusBits {
165 PCIErr = 0x8000,
166 PCSTimeout = 0x4000,
167 RxFIFOOver = 0x40,
168 RxUnderrun = 0x20,
169 RxOverflow = 0x10,
170 TxErr = 0x08,
171 TxOK = 0x04,
172 RxErr = 0x02,
173 RxOK = 0x01,
174
175 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
176 };
177
178 enum TxStatusBits {
179 TxHostOwns = 0x2000,
180 TxUnderrun = 0x4000,
181 TxStatOK = 0x8000,
182 TxOutOfWindow = 0x20000000,
183 TxAborted = 0x40000000,
184 TxCarrierLost = 0x80000000,
185 };
186 enum RxStatusBits {
187 RxMulticast = 0x8000,
188 RxPhysical = 0x4000,
189 RxBroadcast = 0x2000,
190 RxBadSymbol = 0x0020,
191 RxRunt = 0x0010,
192 RxTooLong = 0x0008,
193 RxCRCErr = 0x0004,
194 RxBadAlign = 0x0002,
195 RxStatusOK = 0x0001,
196 };
197
198 /* Bits in RxConfig. */
199 enum rx_mode_bits {
200 AcceptErr = 0x20,
201 AcceptRunt = 0x10,
202 AcceptBroadcast = 0x08,
203 AcceptMulticast = 0x04,
204 AcceptMyPhys = 0x02,
205 AcceptAllPhys = 0x01,
206 };
207
208 /* Bits in TxConfig. */
209 enum tx_config_bits {
210
211 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
212 TxIFGShift = 24,
213 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
214 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
215 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
216 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
217
218 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
219 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
220 TxClearAbt = (1 << 0), /* Clear abort (WO) */
221 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
222 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
223
224 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
225 };
226
227
228 /* Transmit Status of All Descriptors (TSAD) Register */
229 enum TSAD_bits {
230 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
231 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
232 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
233 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
234 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
235 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
236 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
237 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
238 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
239 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
240 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
241 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
242 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
243 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
244 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
245 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
246 };
247
248
249 /* Bits in Config1 */
250 enum Config1Bits {
251 Cfg1_PM_Enable = 0x01,
252 Cfg1_VPD_Enable = 0x02,
253 Cfg1_PIO = 0x04,
254 Cfg1_MMIO = 0x08,
255 LWAKE = 0x10, /* not on 8139, 8139A */
256 Cfg1_Driver_Load = 0x20,
257 Cfg1_LED0 = 0x40,
258 Cfg1_LED1 = 0x80,
259 SLEEP = (1 << 1), /* only on 8139, 8139A */
260 PWRDN = (1 << 0), /* only on 8139, 8139A */
261 };
262
263 /* Bits in Config3 */
264 enum Config3Bits {
265 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
266 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
267 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
268 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
269 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
270 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
271 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
272 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
273 };
274
275 /* Bits in Config4 */
276 enum Config4Bits {
277 LWPTN = (1 << 2), /* not on 8139, 8139A */
278 };
279
280 /* Bits in Config5 */
281 enum Config5Bits {
282 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
283 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
284 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
285 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
286 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
287 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
288 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
289 };
290
291 enum RxConfigBits {
292 /* rx fifo threshold */
293 RxCfgFIFOShift = 13,
294 RxCfgFIFONone = (7 << RxCfgFIFOShift),
295
296 /* Max DMA burst */
297 RxCfgDMAShift = 8,
298 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
299
300 /* rx ring buffer length */
301 RxCfgRcv8K = 0,
302 RxCfgRcv16K = (1 << 11),
303 RxCfgRcv32K = (1 << 12),
304 RxCfgRcv64K = (1 << 11) | (1 << 12),
305
306 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
307 RxNoWrap = (1 << 7),
308 };
309
310 /* Twister tuning parameters from RealTek.
311 Completely undocumented, but required to tune bad links on some boards. */
312 /*
313 enum CSCRBits {
314 CSCR_LinkOKBit = 0x0400,
315 CSCR_LinkChangeBit = 0x0800,
316 CSCR_LinkStatusBits = 0x0f000,
317 CSCR_LinkDownOffCmd = 0x003c0,
318 CSCR_LinkDownCmd = 0x0f3c0,
319 */
320 enum CSCRBits {
321 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
322 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
323 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
324 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
325 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
326 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
327 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
328 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
329 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
330 };
331
332 enum Cfg9346Bits {
333 Cfg9346_Lock = 0x00,
334 Cfg9346_Unlock = 0xC0,
335 };
336
337 typedef enum {
338 CH_8139 = 0,
339 CH_8139_K,
340 CH_8139A,
341 CH_8139A_G,
342 CH_8139B,
343 CH_8130,
344 CH_8139C,
345 CH_8100,
346 CH_8100B_8139D,
347 CH_8101,
348 } chip_t;
349
350 enum chip_flags {
351 HasHltClk = (1 << 0),
352 HasLWake = (1 << 1),
353 };
354
355 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
356 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
357 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
358
359 #define RTL8139_PCI_REVID_8139 0x10
360 #define RTL8139_PCI_REVID_8139CPLUS 0x20
361
362 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
363
364 /* Size is 64 * 16bit words */
365 #define EEPROM_9346_ADDR_BITS 6
366 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
367 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
368
369 enum Chip9346Operation
370 {
371 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
372 Chip9346_op_read = 0x80, /* 10 AAAAAA */
373 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
374 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
375 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
376 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
377 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
378 };
379
380 enum Chip9346Mode
381 {
382 Chip9346_none = 0,
383 Chip9346_enter_command_mode,
384 Chip9346_read_command,
385 Chip9346_data_read, /* from output register */
386 Chip9346_data_write, /* to input register, then to contents at specified address */
387 Chip9346_data_write_all, /* to input register, then filling contents */
388 };
389
390 typedef struct EEprom9346
391 {
392 uint16_t contents[EEPROM_9346_SIZE];
393 int mode;
394 uint32_t tick;
395 uint8_t address;
396 uint16_t input;
397 uint16_t output;
398
399 uint8_t eecs;
400 uint8_t eesk;
401 uint8_t eedi;
402 uint8_t eedo;
403 } EEprom9346;
404
405 typedef struct RTL8139TallyCounters
406 {
407 /* Tally counters */
408 uint64_t TxOk;
409 uint64_t RxOk;
410 uint64_t TxERR;
411 uint32_t RxERR;
412 uint16_t MissPkt;
413 uint16_t FAE;
414 uint32_t Tx1Col;
415 uint32_t TxMCol;
416 uint64_t RxOkPhy;
417 uint64_t RxOkBrd;
418 uint32_t RxOkMul;
419 uint16_t TxAbt;
420 uint16_t TxUndrn;
421 } RTL8139TallyCounters;
422
423 /* Clears all tally counters */
424 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
425
426 /* Writes tally counters to specified physical memory address */
427 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
428
429 typedef struct RTL8139State {
430 PCIDevice dev;
431 uint8_t phys[8]; /* mac address */
432 uint8_t mult[8]; /* multicast mask array */
433
434 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
435 uint32_t TxAddr[4]; /* TxAddr0 */
436 uint32_t RxBuf; /* Receive buffer */
437 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
438 uint32_t RxBufPtr;
439 uint32_t RxBufAddr;
440
441 uint16_t IntrStatus;
442 uint16_t IntrMask;
443
444 uint32_t TxConfig;
445 uint32_t RxConfig;
446 uint32_t RxMissed;
447
448 uint16_t CSCR;
449
450 uint8_t Cfg9346;
451 uint8_t Config0;
452 uint8_t Config1;
453 uint8_t Config3;
454 uint8_t Config4;
455 uint8_t Config5;
456
457 uint8_t clock_enabled;
458 uint8_t bChipCmdState;
459
460 uint16_t MultiIntr;
461
462 uint16_t BasicModeCtrl;
463 uint16_t BasicModeStatus;
464 uint16_t NWayAdvert;
465 uint16_t NWayLPAR;
466 uint16_t NWayExpansion;
467
468 uint16_t CpCmd;
469 uint8_t TxThresh;
470
471 NICState *nic;
472 NICConf conf;
473 int rtl8139_mmio_io_addr;
474
475 /* C ring mode */
476 uint32_t currTxDesc;
477
478 /* C+ mode */
479 uint32_t cplus_enabled;
480
481 uint32_t currCPlusRxDesc;
482 uint32_t currCPlusTxDesc;
483
484 uint32_t RxRingAddrLO;
485 uint32_t RxRingAddrHI;
486
487 EEprom9346 eeprom;
488
489 uint32_t TCTR;
490 uint32_t TimerInt;
491 int64_t TCTR_base;
492
493 /* Tally counters */
494 RTL8139TallyCounters tally_counters;
495
496 /* Non-persistent data */
497 uint8_t *cplus_txbuffer;
498 int cplus_txbuffer_len;
499 int cplus_txbuffer_offset;
500
501 /* PCI interrupt timer */
502 QEMUTimer *timer;
503 int64_t TimerExpire;
504
505 /* Support migration to/from old versions */
506 int rtl8139_mmio_io_addr_dummy;
507 } RTL8139State;
508
509 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
510
511 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
512 {
513 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
514
515 switch (command & Chip9346_op_mask)
516 {
517 case Chip9346_op_read:
518 {
519 eeprom->address = command & EEPROM_9346_ADDR_MASK;
520 eeprom->output = eeprom->contents[eeprom->address];
521 eeprom->eedo = 0;
522 eeprom->tick = 0;
523 eeprom->mode = Chip9346_data_read;
524 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
525 eeprom->address, eeprom->output));
526 }
527 break;
528
529 case Chip9346_op_write:
530 {
531 eeprom->address = command & EEPROM_9346_ADDR_MASK;
532 eeprom->input = 0;
533 eeprom->tick = 0;
534 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
535 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
536 eeprom->address));
537 }
538 break;
539 default:
540 eeprom->mode = Chip9346_none;
541 switch (command & Chip9346_op_ext_mask)
542 {
543 case Chip9346_op_write_enable:
544 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
545 break;
546 case Chip9346_op_write_all:
547 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
548 break;
549 case Chip9346_op_write_disable:
550 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
551 break;
552 }
553 break;
554 }
555 }
556
557 static void prom9346_shift_clock(EEprom9346 *eeprom)
558 {
559 int bit = eeprom->eedi?1:0;
560
561 ++ eeprom->tick;
562
563 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
564
565 switch (eeprom->mode)
566 {
567 case Chip9346_enter_command_mode:
568 if (bit)
569 {
570 eeprom->mode = Chip9346_read_command;
571 eeprom->tick = 0;
572 eeprom->input = 0;
573 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
574 }
575 break;
576
577 case Chip9346_read_command:
578 eeprom->input = (eeprom->input << 1) | (bit & 1);
579 if (eeprom->tick == 8)
580 {
581 prom9346_decode_command(eeprom, eeprom->input & 0xff);
582 }
583 break;
584
585 case Chip9346_data_read:
586 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
587 eeprom->output <<= 1;
588 if (eeprom->tick == 16)
589 {
590 #if 1
591 // the FreeBSD drivers (rl and re) don't explicitly toggle
592 // CS between reads (or does setting Cfg9346 to 0 count too?),
593 // so we need to enter wait-for-command state here
594 eeprom->mode = Chip9346_enter_command_mode;
595 eeprom->input = 0;
596 eeprom->tick = 0;
597
598 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
599 #else
600 // original behaviour
601 ++eeprom->address;
602 eeprom->address &= EEPROM_9346_ADDR_MASK;
603 eeprom->output = eeprom->contents[eeprom->address];
604 eeprom->tick = 0;
605
606 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
607 eeprom->address, eeprom->output));
608 #endif
609 }
610 break;
611
612 case Chip9346_data_write:
613 eeprom->input = (eeprom->input << 1) | (bit & 1);
614 if (eeprom->tick == 16)
615 {
616 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
617 eeprom->address, eeprom->input));
618
619 eeprom->contents[eeprom->address] = eeprom->input;
620 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
621 eeprom->tick = 0;
622 eeprom->input = 0;
623 }
624 break;
625
626 case Chip9346_data_write_all:
627 eeprom->input = (eeprom->input << 1) | (bit & 1);
628 if (eeprom->tick == 16)
629 {
630 int i;
631 for (i = 0; i < EEPROM_9346_SIZE; i++)
632 {
633 eeprom->contents[i] = eeprom->input;
634 }
635 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
636 eeprom->input));
637
638 eeprom->mode = Chip9346_enter_command_mode;
639 eeprom->tick = 0;
640 eeprom->input = 0;
641 }
642 break;
643
644 default:
645 break;
646 }
647 }
648
649 static int prom9346_get_wire(RTL8139State *s)
650 {
651 EEprom9346 *eeprom = &s->eeprom;
652 if (!eeprom->eecs)
653 return 0;
654
655 return eeprom->eedo;
656 }
657
658 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
659 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
660 {
661 EEprom9346 *eeprom = &s->eeprom;
662 uint8_t old_eecs = eeprom->eecs;
663 uint8_t old_eesk = eeprom->eesk;
664
665 eeprom->eecs = eecs;
666 eeprom->eesk = eesk;
667 eeprom->eedi = eedi;
668
669 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
670 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
671
672 if (!old_eecs && eecs)
673 {
674 /* Synchronize start */
675 eeprom->tick = 0;
676 eeprom->input = 0;
677 eeprom->output = 0;
678 eeprom->mode = Chip9346_enter_command_mode;
679
680 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
681 }
682
683 if (!eecs)
684 {
685 DEBUG_PRINT(("=== eeprom: end access\n"));
686 return;
687 }
688
689 if (!old_eesk && eesk)
690 {
691 /* SK front rules */
692 prom9346_shift_clock(eeprom);
693 }
694 }
695
696 static void rtl8139_update_irq(RTL8139State *s)
697 {
698 int isr;
699 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
700
701 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
702 isr ? 1 : 0, s->IntrStatus, s->IntrMask));
703
704 qemu_set_irq(s->dev.irq[0], (isr != 0));
705 }
706
707 #define POLYNOMIAL 0x04c11db6
708
709 /* From FreeBSD */
710 /* XXX: optimize */
711 static int compute_mcast_idx(const uint8_t *ep)
712 {
713 uint32_t crc;
714 int carry, i, j;
715 uint8_t b;
716
717 crc = 0xffffffff;
718 for (i = 0; i < 6; i++) {
719 b = *ep++;
720 for (j = 0; j < 8; j++) {
721 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
722 crc <<= 1;
723 b >>= 1;
724 if (carry)
725 crc = ((crc ^ POLYNOMIAL) | carry);
726 }
727 }
728 return (crc >> 26);
729 }
730
731 static int rtl8139_RxWrap(RTL8139State *s)
732 {
733 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
734 return (s->RxConfig & (1 << 7));
735 }
736
737 static int rtl8139_receiver_enabled(RTL8139State *s)
738 {
739 return s->bChipCmdState & CmdRxEnb;
740 }
741
742 static int rtl8139_transmitter_enabled(RTL8139State *s)
743 {
744 return s->bChipCmdState & CmdTxEnb;
745 }
746
747 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
748 {
749 return s->CpCmd & CPlusRxEnb;
750 }
751
752 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
753 {
754 return s->CpCmd & CPlusTxEnb;
755 }
756
757 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
758 {
759 if (s->RxBufAddr + size > s->RxBufferSize)
760 {
761 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
762
763 /* write packet data */
764 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
765 {
766 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
767
768 if (size > wrapped)
769 {
770 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
771 buf, size-wrapped );
772 }
773
774 /* reset buffer pointer */
775 s->RxBufAddr = 0;
776
777 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
778 buf + (size-wrapped), wrapped );
779
780 s->RxBufAddr = wrapped;
781
782 return;
783 }
784 }
785
786 /* non-wrapping path or overwrapping enabled */
787 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
788
789 s->RxBufAddr += size;
790 }
791
792 #define MIN_BUF_SIZE 60
793 static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
794 {
795 #if TARGET_PHYS_ADDR_BITS > 32
796 return low | ((target_phys_addr_t)high << 32);
797 #else
798 return low;
799 #endif
800 }
801
802 static int rtl8139_can_receive(VLANClientState *nc)
803 {
804 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
805 int avail;
806
807 /* Receive (drop) packets if card is disabled. */
808 if (!s->clock_enabled)
809 return 1;
810 if (!rtl8139_receiver_enabled(s))
811 return 1;
812
813 if (rtl8139_cp_receiver_enabled(s)) {
814 /* ??? Flow control not implemented in c+ mode.
815 This is a hack to work around slirp deficiencies anyway. */
816 return 1;
817 } else {
818 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
819 s->RxBufferSize);
820 return (avail == 0 || avail >= 1514);
821 }
822 }
823
824 static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
825 {
826 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
827 /* size is the length of the buffer passed to the driver */
828 int size = size_;
829 const uint8_t *dot1q_buf = NULL;
830
831 uint32_t packet_header = 0;
832
833 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
834 static const uint8_t broadcast_macaddr[6] =
835 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
836
837 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
838
839 /* test if board clock is stopped */
840 if (!s->clock_enabled)
841 {
842 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
843 return -1;
844 }
845
846 /* first check if receiver is enabled */
847
848 if (!rtl8139_receiver_enabled(s))
849 {
850 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
851 return -1;
852 }
853
854 /* XXX: check this */
855 if (s->RxConfig & AcceptAllPhys) {
856 /* promiscuous: receive all */
857 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
858
859 } else {
860 if (!memcmp(buf, broadcast_macaddr, 6)) {
861 /* broadcast address */
862 if (!(s->RxConfig & AcceptBroadcast))
863 {
864 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
865
866 /* update tally counter */
867 ++s->tally_counters.RxERR;
868
869 return size;
870 }
871
872 packet_header |= RxBroadcast;
873
874 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
875
876 /* update tally counter */
877 ++s->tally_counters.RxOkBrd;
878
879 } else if (buf[0] & 0x01) {
880 /* multicast */
881 if (!(s->RxConfig & AcceptMulticast))
882 {
883 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
884
885 /* update tally counter */
886 ++s->tally_counters.RxERR;
887
888 return size;
889 }
890
891 int mcast_idx = compute_mcast_idx(buf);
892
893 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
894 {
895 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
896
897 /* update tally counter */
898 ++s->tally_counters.RxERR;
899
900 return size;
901 }
902
903 packet_header |= RxMulticast;
904
905 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
906
907 /* update tally counter */
908 ++s->tally_counters.RxOkMul;
909
910 } else if (s->phys[0] == buf[0] &&
911 s->phys[1] == buf[1] &&
912 s->phys[2] == buf[2] &&
913 s->phys[3] == buf[3] &&
914 s->phys[4] == buf[4] &&
915 s->phys[5] == buf[5]) {
916 /* match */
917 if (!(s->RxConfig & AcceptMyPhys))
918 {
919 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
920
921 /* update tally counter */
922 ++s->tally_counters.RxERR;
923
924 return size;
925 }
926
927 packet_header |= RxPhysical;
928
929 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
930
931 /* update tally counter */
932 ++s->tally_counters.RxOkPhy;
933
934 } else {
935
936 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
937
938 /* update tally counter */
939 ++s->tally_counters.RxERR;
940
941 return size;
942 }
943 }
944
945 /* if too small buffer, then expand it
946 * Include some tailroom in case a vlan tag is later removed. */
947 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
948 memcpy(buf1, buf, size);
949 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
950 buf = buf1;
951 if (size < MIN_BUF_SIZE) {
952 size = MIN_BUF_SIZE;
953 }
954 }
955
956 if (rtl8139_cp_receiver_enabled(s))
957 {
958 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
959
960 /* begin C+ receiver mode */
961
962 /* w0 ownership flag */
963 #define CP_RX_OWN (1<<31)
964 /* w0 end of ring flag */
965 #define CP_RX_EOR (1<<30)
966 /* w0 bits 0...12 : buffer size */
967 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
968 /* w1 tag available flag */
969 #define CP_RX_TAVA (1<<16)
970 /* w1 bits 0...15 : VLAN tag */
971 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
972 /* w2 low 32bit of Rx buffer ptr */
973 /* w3 high 32bit of Rx buffer ptr */
974
975 int descriptor = s->currCPlusRxDesc;
976 target_phys_addr_t cplus_rx_ring_desc;
977
978 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
979 cplus_rx_ring_desc += 16 * descriptor;
980
981 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from "
982 "host memory at %08x %08x = " TARGET_FMT_plx "\n", descriptor,
983 s->RxRingAddrHI, s->RxRingAddrLO, cplus_rx_ring_desc));
984
985 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
986
987 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
988 rxdw0 = le32_to_cpu(val);
989 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
990 rxdw1 = le32_to_cpu(val);
991 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
992 rxbufLO = le32_to_cpu(val);
993 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
994 rxbufHI = le32_to_cpu(val);
995
996 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
997 descriptor,
998 rxdw0, rxdw1, rxbufLO, rxbufHI));
999
1000 if (!(rxdw0 & CP_RX_OWN))
1001 {
1002 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
1003
1004 s->IntrStatus |= RxOverflow;
1005 ++s->RxMissed;
1006
1007 /* update tally counter */
1008 ++s->tally_counters.RxERR;
1009 ++s->tally_counters.MissPkt;
1010
1011 rtl8139_update_irq(s);
1012 return size_;
1013 }
1014
1015 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1016
1017 /* write VLAN info to descriptor variables. */
1018 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1019 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1020 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1021 size -= VLAN_HLEN;
1022 /* if too small buffer, use the tailroom added duing expansion */
1023 if (size < MIN_BUF_SIZE) {
1024 size = MIN_BUF_SIZE;
1025 }
1026
1027 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1028 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1029 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1030 &dot1q_buf[ETHER_TYPE_LEN]);
1031
1032 DEBUG_PRINT(("RTL8139: C+ Rx mode : extracted vlan tag with tci: "
1033 "%u\n", be16_to_cpup((uint16_t *)
1034 &dot1q_buf[ETHER_TYPE_LEN])));
1035 } else {
1036 /* reset VLAN tag flag */
1037 rxdw1 &= ~CP_RX_TAVA;
1038 }
1039
1040 /* TODO: scatter the packet over available receive ring descriptors space */
1041
1042 if (size+4 > rx_space)
1043 {
1044 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1045 descriptor, rx_space, size));
1046
1047 s->IntrStatus |= RxOverflow;
1048 ++s->RxMissed;
1049
1050 /* update tally counter */
1051 ++s->tally_counters.RxERR;
1052 ++s->tally_counters.MissPkt;
1053
1054 rtl8139_update_irq(s);
1055 return size_;
1056 }
1057
1058 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1059
1060 /* receive/copy to target memory */
1061 if (dot1q_buf) {
1062 cpu_physical_memory_write(rx_addr, buf, 2 * ETHER_ADDR_LEN);
1063 cpu_physical_memory_write(rx_addr + 2 * ETHER_ADDR_LEN,
1064 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1065 size - 2 * ETHER_ADDR_LEN);
1066 } else {
1067 cpu_physical_memory_write(rx_addr, buf, size);
1068 }
1069
1070 if (s->CpCmd & CPlusRxChkSum)
1071 {
1072 /* do some packet checksumming */
1073 }
1074
1075 /* write checksum */
1076 val = cpu_to_le32(crc32(0, buf, size_));
1077 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1078
1079 /* first segment of received packet flag */
1080 #define CP_RX_STATUS_FS (1<<29)
1081 /* last segment of received packet flag */
1082 #define CP_RX_STATUS_LS (1<<28)
1083 /* multicast packet flag */
1084 #define CP_RX_STATUS_MAR (1<<26)
1085 /* physical-matching packet flag */
1086 #define CP_RX_STATUS_PAM (1<<25)
1087 /* broadcast packet flag */
1088 #define CP_RX_STATUS_BAR (1<<24)
1089 /* runt packet flag */
1090 #define CP_RX_STATUS_RUNT (1<<19)
1091 /* crc error flag */
1092 #define CP_RX_STATUS_CRC (1<<18)
1093 /* IP checksum error flag */
1094 #define CP_RX_STATUS_IPF (1<<15)
1095 /* UDP checksum error flag */
1096 #define CP_RX_STATUS_UDPF (1<<14)
1097 /* TCP checksum error flag */
1098 #define CP_RX_STATUS_TCPF (1<<13)
1099
1100 /* transfer ownership to target */
1101 rxdw0 &= ~CP_RX_OWN;
1102
1103 /* set first segment bit */
1104 rxdw0 |= CP_RX_STATUS_FS;
1105
1106 /* set last segment bit */
1107 rxdw0 |= CP_RX_STATUS_LS;
1108
1109 /* set received packet type flags */
1110 if (packet_header & RxBroadcast)
1111 rxdw0 |= CP_RX_STATUS_BAR;
1112 if (packet_header & RxMulticast)
1113 rxdw0 |= CP_RX_STATUS_MAR;
1114 if (packet_header & RxPhysical)
1115 rxdw0 |= CP_RX_STATUS_PAM;
1116
1117 /* set received size */
1118 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1119 rxdw0 |= (size+4);
1120
1121 /* update ring data */
1122 val = cpu_to_le32(rxdw0);
1123 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1124 val = cpu_to_le32(rxdw1);
1125 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1126
1127 /* update tally counter */
1128 ++s->tally_counters.RxOk;
1129
1130 /* seek to next Rx descriptor */
1131 if (rxdw0 & CP_RX_EOR)
1132 {
1133 s->currCPlusRxDesc = 0;
1134 }
1135 else
1136 {
1137 ++s->currCPlusRxDesc;
1138 }
1139
1140 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
1141
1142 }
1143 else
1144 {
1145 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1146
1147 /* begin ring receiver mode */
1148 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1149
1150 /* if receiver buffer is empty then avail == 0 */
1151
1152 if (avail != 0 && size + 8 >= avail)
1153 {
1154 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1155 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1156
1157 s->IntrStatus |= RxOverflow;
1158 ++s->RxMissed;
1159 rtl8139_update_irq(s);
1160 return size_;
1161 }
1162
1163 packet_header |= RxStatusOK;
1164
1165 packet_header |= (((size+4) << 16) & 0xffff0000);
1166
1167 /* write header */
1168 uint32_t val = cpu_to_le32(packet_header);
1169
1170 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1171
1172 rtl8139_write_buffer(s, buf, size);
1173
1174 /* write checksum */
1175 val = cpu_to_le32(crc32(0, buf, size));
1176 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1177
1178 /* correct buffer write pointer */
1179 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1180
1181 /* now we can signal we have received something */
1182
1183 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1184 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
1185 }
1186
1187 s->IntrStatus |= RxOK;
1188
1189 if (do_interrupt)
1190 {
1191 rtl8139_update_irq(s);
1192 }
1193
1194 return size_;
1195 }
1196
1197 static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
1198 {
1199 return rtl8139_do_receive(nc, buf, size, 1);
1200 }
1201
1202 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1203 {
1204 s->RxBufferSize = bufferSize;
1205 s->RxBufPtr = 0;
1206 s->RxBufAddr = 0;
1207 }
1208
1209 static void rtl8139_reset(DeviceState *d)
1210 {
1211 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
1212 int i;
1213
1214 /* restore MAC address */
1215 memcpy(s->phys, s->conf.macaddr.a, 6);
1216
1217 /* reset interrupt mask */
1218 s->IntrStatus = 0;
1219 s->IntrMask = 0;
1220
1221 rtl8139_update_irq(s);
1222
1223 /* mark all status registers as owned by host */
1224 for (i = 0; i < 4; ++i)
1225 {
1226 s->TxStatus[i] = TxHostOwns;
1227 }
1228
1229 s->currTxDesc = 0;
1230 s->currCPlusRxDesc = 0;
1231 s->currCPlusTxDesc = 0;
1232
1233 s->RxRingAddrLO = 0;
1234 s->RxRingAddrHI = 0;
1235
1236 s->RxBuf = 0;
1237
1238 rtl8139_reset_rxring(s, 8192);
1239
1240 /* ACK the reset */
1241 s->TxConfig = 0;
1242
1243 #if 0
1244 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1245 s->clock_enabled = 0;
1246 #else
1247 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1248 s->clock_enabled = 1;
1249 #endif
1250
1251 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1252
1253 /* set initial state data */
1254 s->Config0 = 0x0; /* No boot ROM */
1255 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1256 s->Config3 = 0x1; /* fast back-to-back compatible */
1257 s->Config5 = 0x0;
1258
1259 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1260
1261 s->CpCmd = 0x0; /* reset C+ mode */
1262 s->cplus_enabled = 0;
1263
1264
1265 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1266 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1267 s->BasicModeCtrl = 0x1000; // autonegotiation
1268
1269 s->BasicModeStatus = 0x7809;
1270 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1271 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1272 s->BasicModeStatus |= 0x0004; /* link is up */
1273
1274 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1275 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1276 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1277
1278 /* also reset timer and disable timer interrupt */
1279 s->TCTR = 0;
1280 s->TimerInt = 0;
1281 s->TCTR_base = 0;
1282
1283 /* reset tally counters */
1284 RTL8139TallyCounters_clear(&s->tally_counters);
1285 }
1286
1287 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1288 {
1289 counters->TxOk = 0;
1290 counters->RxOk = 0;
1291 counters->TxERR = 0;
1292 counters->RxERR = 0;
1293 counters->MissPkt = 0;
1294 counters->FAE = 0;
1295 counters->Tx1Col = 0;
1296 counters->TxMCol = 0;
1297 counters->RxOkPhy = 0;
1298 counters->RxOkBrd = 0;
1299 counters->RxOkMul = 0;
1300 counters->TxAbt = 0;
1301 counters->TxUndrn = 0;
1302 }
1303
1304 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
1305 {
1306 uint16_t val16;
1307 uint32_t val32;
1308 uint64_t val64;
1309
1310 val64 = cpu_to_le64(tally_counters->TxOk);
1311 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1312
1313 val64 = cpu_to_le64(tally_counters->RxOk);
1314 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1315
1316 val64 = cpu_to_le64(tally_counters->TxERR);
1317 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1318
1319 val32 = cpu_to_le32(tally_counters->RxERR);
1320 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1321
1322 val16 = cpu_to_le16(tally_counters->MissPkt);
1323 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1324
1325 val16 = cpu_to_le16(tally_counters->FAE);
1326 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1327
1328 val32 = cpu_to_le32(tally_counters->Tx1Col);
1329 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1330
1331 val32 = cpu_to_le32(tally_counters->TxMCol);
1332 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1333
1334 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1335 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1336
1337 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1338 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1339
1340 val32 = cpu_to_le32(tally_counters->RxOkMul);
1341 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1342
1343 val16 = cpu_to_le16(tally_counters->TxAbt);
1344 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1345
1346 val16 = cpu_to_le16(tally_counters->TxUndrn);
1347 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1348 }
1349
1350 /* Loads values of tally counters from VM state file */
1351
1352 static const VMStateDescription vmstate_tally_counters = {
1353 .name = "tally_counters",
1354 .version_id = 1,
1355 .minimum_version_id = 1,
1356 .minimum_version_id_old = 1,
1357 .fields = (VMStateField []) {
1358 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1359 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1360 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1361 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1362 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1363 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1364 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1365 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1366 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1367 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1368 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1369 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1370 VMSTATE_END_OF_LIST()
1371 }
1372 };
1373
1374 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1375 {
1376 val &= 0xff;
1377
1378 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
1379
1380 if (val & CmdReset)
1381 {
1382 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
1383 rtl8139_reset(&s->dev.qdev);
1384 }
1385 if (val & CmdRxEnb)
1386 {
1387 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
1388
1389 s->currCPlusRxDesc = 0;
1390 }
1391 if (val & CmdTxEnb)
1392 {
1393 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
1394
1395 s->currCPlusTxDesc = 0;
1396 }
1397
1398 /* mask unwriteable bits */
1399 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1400
1401 /* Deassert reset pin before next read */
1402 val &= ~CmdReset;
1403
1404 s->bChipCmdState = val;
1405 }
1406
1407 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1408 {
1409 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1410
1411 if (unread != 0)
1412 {
1413 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
1414 return 0;
1415 }
1416
1417 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
1418
1419 return 1;
1420 }
1421
1422 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1423 {
1424 uint32_t ret = s->bChipCmdState;
1425
1426 if (rtl8139_RxBufferEmpty(s))
1427 ret |= RxBufEmpty;
1428
1429 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
1430
1431 return ret;
1432 }
1433
1434 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1435 {
1436 val &= 0xffff;
1437
1438 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
1439
1440 s->cplus_enabled = 1;
1441
1442 /* mask unwriteable bits */
1443 val = SET_MASKED(val, 0xff84, s->CpCmd);
1444
1445 s->CpCmd = val;
1446 }
1447
1448 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1449 {
1450 uint32_t ret = s->CpCmd;
1451
1452 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1453
1454 return ret;
1455 }
1456
1457 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1458 {
1459 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1460 }
1461
1462 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1463 {
1464 uint32_t ret = 0;
1465
1466 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
1467
1468 return ret;
1469 }
1470
1471 static int rtl8139_config_writeable(RTL8139State *s)
1472 {
1473 if (s->Cfg9346 & Cfg9346_Unlock)
1474 {
1475 return 1;
1476 }
1477
1478 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
1479
1480 return 0;
1481 }
1482
1483 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1484 {
1485 val &= 0xffff;
1486
1487 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
1488
1489 /* mask unwriteable bits */
1490 uint32_t mask = 0x4cff;
1491
1492 if (1 || !rtl8139_config_writeable(s))
1493 {
1494 /* Speed setting and autonegotiation enable bits are read-only */
1495 mask |= 0x3000;
1496 /* Duplex mode setting is read-only */
1497 mask |= 0x0100;
1498 }
1499
1500 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1501
1502 s->BasicModeCtrl = val;
1503 }
1504
1505 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1506 {
1507 uint32_t ret = s->BasicModeCtrl;
1508
1509 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
1510
1511 return ret;
1512 }
1513
1514 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1515 {
1516 val &= 0xffff;
1517
1518 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
1519
1520 /* mask unwriteable bits */
1521 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1522
1523 s->BasicModeStatus = val;
1524 }
1525
1526 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1527 {
1528 uint32_t ret = s->BasicModeStatus;
1529
1530 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
1531
1532 return ret;
1533 }
1534
1535 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1536 {
1537 val &= 0xff;
1538
1539 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
1540
1541 /* mask unwriteable bits */
1542 val = SET_MASKED(val, 0x31, s->Cfg9346);
1543
1544 uint32_t opmode = val & 0xc0;
1545 uint32_t eeprom_val = val & 0xf;
1546
1547 if (opmode == 0x80) {
1548 /* eeprom access */
1549 int eecs = (eeprom_val & 0x08)?1:0;
1550 int eesk = (eeprom_val & 0x04)?1:0;
1551 int eedi = (eeprom_val & 0x02)?1:0;
1552 prom9346_set_wire(s, eecs, eesk, eedi);
1553 } else if (opmode == 0x40) {
1554 /* Reset. */
1555 val = 0;
1556 rtl8139_reset(&s->dev.qdev);
1557 }
1558
1559 s->Cfg9346 = val;
1560 }
1561
1562 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1563 {
1564 uint32_t ret = s->Cfg9346;
1565
1566 uint32_t opmode = ret & 0xc0;
1567
1568 if (opmode == 0x80)
1569 {
1570 /* eeprom access */
1571 int eedo = prom9346_get_wire(s);
1572 if (eedo)
1573 {
1574 ret |= 0x01;
1575 }
1576 else
1577 {
1578 ret &= ~0x01;
1579 }
1580 }
1581
1582 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
1583
1584 return ret;
1585 }
1586
1587 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1588 {
1589 val &= 0xff;
1590
1591 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
1592
1593 if (!rtl8139_config_writeable(s))
1594 return;
1595
1596 /* mask unwriteable bits */
1597 val = SET_MASKED(val, 0xf8, s->Config0);
1598
1599 s->Config0 = val;
1600 }
1601
1602 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1603 {
1604 uint32_t ret = s->Config0;
1605
1606 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
1607
1608 return ret;
1609 }
1610
1611 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1612 {
1613 val &= 0xff;
1614
1615 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
1616
1617 if (!rtl8139_config_writeable(s))
1618 return;
1619
1620 /* mask unwriteable bits */
1621 val = SET_MASKED(val, 0xC, s->Config1);
1622
1623 s->Config1 = val;
1624 }
1625
1626 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1627 {
1628 uint32_t ret = s->Config1;
1629
1630 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
1631
1632 return ret;
1633 }
1634
1635 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1636 {
1637 val &= 0xff;
1638
1639 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
1640
1641 if (!rtl8139_config_writeable(s))
1642 return;
1643
1644 /* mask unwriteable bits */
1645 val = SET_MASKED(val, 0x8F, s->Config3);
1646
1647 s->Config3 = val;
1648 }
1649
1650 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1651 {
1652 uint32_t ret = s->Config3;
1653
1654 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
1655
1656 return ret;
1657 }
1658
1659 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1660 {
1661 val &= 0xff;
1662
1663 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
1664
1665 if (!rtl8139_config_writeable(s))
1666 return;
1667
1668 /* mask unwriteable bits */
1669 val = SET_MASKED(val, 0x0a, s->Config4);
1670
1671 s->Config4 = val;
1672 }
1673
1674 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1675 {
1676 uint32_t ret = s->Config4;
1677
1678 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
1679
1680 return ret;
1681 }
1682
1683 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1684 {
1685 val &= 0xff;
1686
1687 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
1688
1689 /* mask unwriteable bits */
1690 val = SET_MASKED(val, 0x80, s->Config5);
1691
1692 s->Config5 = val;
1693 }
1694
1695 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1696 {
1697 uint32_t ret = s->Config5;
1698
1699 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
1700
1701 return ret;
1702 }
1703
1704 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1705 {
1706 if (!rtl8139_transmitter_enabled(s))
1707 {
1708 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
1709 return;
1710 }
1711
1712 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
1713
1714 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1715
1716 s->TxConfig = val;
1717 }
1718
1719 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1720 {
1721 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1722
1723 uint32_t tc = s->TxConfig;
1724 tc &= 0xFFFFFF00;
1725 tc |= (val & 0x000000FF);
1726 rtl8139_TxConfig_write(s, tc);
1727 }
1728
1729 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1730 {
1731 uint32_t ret = s->TxConfig;
1732
1733 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
1734
1735 return ret;
1736 }
1737
1738 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1739 {
1740 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
1741
1742 /* mask unwriteable bits */
1743 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1744
1745 s->RxConfig = val;
1746
1747 /* reset buffer size and read/write pointers */
1748 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1749
1750 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
1751 }
1752
1753 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1754 {
1755 uint32_t ret = s->RxConfig;
1756
1757 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
1758
1759 return ret;
1760 }
1761
1762 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1763 int do_interrupt, const uint8_t *dot1q_buf)
1764 {
1765 struct iovec *iov = NULL;
1766
1767 if (!size)
1768 {
1769 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1770 return;
1771 }
1772
1773 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1774 iov = (struct iovec[3]) {
1775 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1776 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1777 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1778 .iov_len = size - ETHER_ADDR_LEN * 2 },
1779 };
1780 }
1781
1782 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1783 {
1784 size_t buf2_size;
1785 uint8_t *buf2;
1786
1787 if (iov) {
1788 buf2_size = iov_size(iov, 3);
1789 buf2 = qemu_malloc(buf2_size);
1790 iov_to_buf(iov, 3, buf2, 0, buf2_size);
1791 buf = buf2;
1792 }
1793
1794 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1795 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
1796
1797 if (iov) {
1798 qemu_free(buf2);
1799 }
1800 }
1801 else
1802 {
1803 if (iov) {
1804 qemu_sendv_packet(&s->nic->nc, iov, 3);
1805 } else {
1806 qemu_send_packet(&s->nic->nc, buf, size);
1807 }
1808 }
1809 }
1810
1811 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1812 {
1813 if (!rtl8139_transmitter_enabled(s))
1814 {
1815 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1816 descriptor));
1817 return 0;
1818 }
1819
1820 if (s->TxStatus[descriptor] & TxHostOwns)
1821 {
1822 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1823 descriptor, s->TxStatus[descriptor]));
1824 return 0;
1825 }
1826
1827 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
1828
1829 int txsize = s->TxStatus[descriptor] & 0x1fff;
1830 uint8_t txbuffer[0x2000];
1831
1832 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1833 txsize, s->TxAddr[descriptor]));
1834
1835 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
1836
1837 /* Mark descriptor as transferred */
1838 s->TxStatus[descriptor] |= TxHostOwns;
1839 s->TxStatus[descriptor] |= TxStatOK;
1840
1841 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
1842
1843 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
1844
1845 /* update interrupt */
1846 s->IntrStatus |= TxOK;
1847 rtl8139_update_irq(s);
1848
1849 return 1;
1850 }
1851
1852 /* structures and macros for task offloading */
1853 typedef struct ip_header
1854 {
1855 uint8_t ip_ver_len; /* version and header length */
1856 uint8_t ip_tos; /* type of service */
1857 uint16_t ip_len; /* total length */
1858 uint16_t ip_id; /* identification */
1859 uint16_t ip_off; /* fragment offset field */
1860 uint8_t ip_ttl; /* time to live */
1861 uint8_t ip_p; /* protocol */
1862 uint16_t ip_sum; /* checksum */
1863 uint32_t ip_src,ip_dst; /* source and dest address */
1864 } ip_header;
1865
1866 #define IP_HEADER_VERSION_4 4
1867 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1868 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1869
1870 typedef struct tcp_header
1871 {
1872 uint16_t th_sport; /* source port */
1873 uint16_t th_dport; /* destination port */
1874 uint32_t th_seq; /* sequence number */
1875 uint32_t th_ack; /* acknowledgement number */
1876 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1877 uint16_t th_win; /* window */
1878 uint16_t th_sum; /* checksum */
1879 uint16_t th_urp; /* urgent pointer */
1880 } tcp_header;
1881
1882 typedef struct udp_header
1883 {
1884 uint16_t uh_sport; /* source port */
1885 uint16_t uh_dport; /* destination port */
1886 uint16_t uh_ulen; /* udp length */
1887 uint16_t uh_sum; /* udp checksum */
1888 } udp_header;
1889
1890 typedef struct ip_pseudo_header
1891 {
1892 uint32_t ip_src;
1893 uint32_t ip_dst;
1894 uint8_t zeros;
1895 uint8_t ip_proto;
1896 uint16_t ip_payload;
1897 } ip_pseudo_header;
1898
1899 #define IP_PROTO_TCP 6
1900 #define IP_PROTO_UDP 17
1901
1902 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1903 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1904 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1905
1906 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1907
1908 #define TCP_FLAG_FIN 0x01
1909 #define TCP_FLAG_PUSH 0x08
1910
1911 /* produces ones' complement sum of data */
1912 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1913 {
1914 uint32_t result = 0;
1915
1916 for (; len > 1; data+=2, len-=2)
1917 {
1918 result += *(uint16_t*)data;
1919 }
1920
1921 /* add the remainder byte */
1922 if (len)
1923 {
1924 uint8_t odd[2] = {*data, 0};
1925 result += *(uint16_t*)odd;
1926 }
1927
1928 while (result>>16)
1929 result = (result & 0xffff) + (result >> 16);
1930
1931 return result;
1932 }
1933
1934 static uint16_t ip_checksum(void *data, size_t len)
1935 {
1936 return ~ones_complement_sum((uint8_t*)data, len);
1937 }
1938
1939 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1940 {
1941 if (!rtl8139_transmitter_enabled(s))
1942 {
1943 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
1944 return 0;
1945 }
1946
1947 if (!rtl8139_cp_transmitter_enabled(s))
1948 {
1949 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
1950 return 0 ;
1951 }
1952
1953 int descriptor = s->currCPlusTxDesc;
1954
1955 target_phys_addr_t cplus_tx_ring_desc =
1956 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1957
1958 /* Normal priority ring */
1959 cplus_tx_ring_desc += 16 * descriptor;
1960
1961 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host "
1962 "memory at %08x0x%08x = 0x" TARGET_FMT_plx "\n", descriptor,
1963 s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
1964
1965 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1966
1967 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1968 txdw0 = le32_to_cpu(val);
1969 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1970 txdw1 = le32_to_cpu(val);
1971 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1972 txbufLO = le32_to_cpu(val);
1973 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1974 txbufHI = le32_to_cpu(val);
1975
1976 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
1977 descriptor,
1978 txdw0, txdw1, txbufLO, txbufHI));
1979
1980 /* w0 ownership flag */
1981 #define CP_TX_OWN (1<<31)
1982 /* w0 end of ring flag */
1983 #define CP_TX_EOR (1<<30)
1984 /* first segment of received packet flag */
1985 #define CP_TX_FS (1<<29)
1986 /* last segment of received packet flag */
1987 #define CP_TX_LS (1<<28)
1988 /* large send packet flag */
1989 #define CP_TX_LGSEN (1<<27)
1990 /* large send MSS mask, bits 16...25 */
1991 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1992
1993 /* IP checksum offload flag */
1994 #define CP_TX_IPCS (1<<18)
1995 /* UDP checksum offload flag */
1996 #define CP_TX_UDPCS (1<<17)
1997 /* TCP checksum offload flag */
1998 #define CP_TX_TCPCS (1<<16)
1999
2000 /* w0 bits 0...15 : buffer size */
2001 #define CP_TX_BUFFER_SIZE (1<<16)
2002 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
2003 /* w1 add tag flag */
2004 #define CP_TX_TAGC (1<<17)
2005 /* w1 bits 0...15 : VLAN tag (big endian) */
2006 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
2007 /* w2 low 32bit of Rx buffer ptr */
2008 /* w3 high 32bit of Rx buffer ptr */
2009
2010 /* set after transmission */
2011 /* FIFO underrun flag */
2012 #define CP_TX_STATUS_UNF (1<<25)
2013 /* transmit error summary flag, valid if set any of three below */
2014 #define CP_TX_STATUS_TES (1<<23)
2015 /* out-of-window collision flag */
2016 #define CP_TX_STATUS_OWC (1<<22)
2017 /* link failure flag */
2018 #define CP_TX_STATUS_LNKF (1<<21)
2019 /* excessive collisions flag */
2020 #define CP_TX_STATUS_EXC (1<<20)
2021
2022 if (!(txdw0 & CP_TX_OWN))
2023 {
2024 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
2025 return 0 ;
2026 }
2027
2028 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
2029
2030 if (txdw0 & CP_TX_FS)
2031 {
2032 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
2033
2034 /* reset internal buffer offset */
2035 s->cplus_txbuffer_offset = 0;
2036 }
2037
2038 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
2039 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
2040
2041 /* make sure we have enough space to assemble the packet */
2042 if (!s->cplus_txbuffer)
2043 {
2044 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2045 s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len);
2046 s->cplus_txbuffer_offset = 0;
2047
2048 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
2049 }
2050
2051 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2052 {
2053 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2054 s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
2055
2056 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
2057 }
2058
2059 if (!s->cplus_txbuffer)
2060 {
2061 /* out of memory */
2062
2063 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2064
2065 /* update tally counter */
2066 ++s->tally_counters.TxERR;
2067 ++s->tally_counters.TxAbt;
2068
2069 return 0;
2070 }
2071
2072 /* append more data to the packet */
2073
2074 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host "
2075 "memory at " TARGET_FMT_plx " to offset %d\n", txsize, tx_addr,
2076 s->cplus_txbuffer_offset));
2077
2078 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2079 s->cplus_txbuffer_offset += txsize;
2080
2081 /* seek to next Rx descriptor */
2082 if (txdw0 & CP_TX_EOR)
2083 {
2084 s->currCPlusTxDesc = 0;
2085 }
2086 else
2087 {
2088 ++s->currCPlusTxDesc;
2089 if (s->currCPlusTxDesc >= 64)
2090 s->currCPlusTxDesc = 0;
2091 }
2092
2093 /* transfer ownership to target */
2094 txdw0 &= ~CP_RX_OWN;
2095
2096 /* reset error indicator bits */
2097 txdw0 &= ~CP_TX_STATUS_UNF;
2098 txdw0 &= ~CP_TX_STATUS_TES;
2099 txdw0 &= ~CP_TX_STATUS_OWC;
2100 txdw0 &= ~CP_TX_STATUS_LNKF;
2101 txdw0 &= ~CP_TX_STATUS_EXC;
2102
2103 /* update ring data */
2104 val = cpu_to_le32(txdw0);
2105 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
2106
2107 /* Now decide if descriptor being processed is holding the last segment of packet */
2108 if (txdw0 & CP_TX_LS)
2109 {
2110 uint8_t dot1q_buffer_space[VLAN_HLEN];
2111 uint16_t *dot1q_buffer;
2112
2113 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2114
2115 /* can transfer fully assembled packet */
2116
2117 uint8_t *saved_buffer = s->cplus_txbuffer;
2118 int saved_size = s->cplus_txbuffer_offset;
2119 int saved_buffer_len = s->cplus_txbuffer_len;
2120
2121 /* create vlan tag */
2122 if (txdw1 & CP_TX_TAGC) {
2123 /* the vlan tag is in BE byte order in the descriptor
2124 * BE + le_to_cpu() + ~swap()~ = cpu */
2125 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : inserting vlan tag with "
2126 "tci: %u\n", bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)));
2127
2128 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2129 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2130 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2131 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2132 } else {
2133 dot1q_buffer = NULL;
2134 }
2135
2136 /* reset the card space to protect from recursive call */
2137 s->cplus_txbuffer = NULL;
2138 s->cplus_txbuffer_offset = 0;
2139 s->cplus_txbuffer_len = 0;
2140
2141 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2142 {
2143 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2144
2145 /* ip packet header */
2146 ip_header *ip = NULL;
2147 int hlen = 0;
2148 uint8_t ip_protocol = 0;
2149 uint16_t ip_data_len = 0;
2150
2151 uint8_t *eth_payload_data = NULL;
2152 size_t eth_payload_len = 0;
2153
2154 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2155 if (proto == ETH_P_IP)
2156 {
2157 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2158
2159 /* not aligned */
2160 eth_payload_data = saved_buffer + ETH_HLEN;
2161 eth_payload_len = saved_size - ETH_HLEN;
2162
2163 ip = (ip_header*)eth_payload_data;
2164
2165 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2166 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
2167 ip = NULL;
2168 } else {
2169 hlen = IP_HEADER_LENGTH(ip);
2170 ip_protocol = ip->ip_p;
2171 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
2172 }
2173 }
2174
2175 if (ip)
2176 {
2177 if (txdw0 & CP_TX_IPCS)
2178 {
2179 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2180
2181 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
2182 /* bad packet header len */
2183 /* or packet too short */
2184 }
2185 else
2186 {
2187 ip->ip_sum = 0;
2188 ip->ip_sum = ip_checksum(ip, hlen);
2189 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2190 }
2191 }
2192
2193 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2194 {
2195 #if defined (DEBUG_RTL8139)
2196 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2197 #endif
2198 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2199 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
2200
2201 int tcp_send_offset = 0;
2202 int send_count = 0;
2203
2204 /* maximum IP header length is 60 bytes */
2205 uint8_t saved_ip_header[60];
2206
2207 /* save IP header template; data area is used in tcp checksum calculation */
2208 memcpy(saved_ip_header, eth_payload_data, hlen);
2209
2210 /* a placeholder for checksum calculation routine in tcp case */
2211 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2212 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2213
2214 /* pointer to TCP header */
2215 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2216
2217 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2218
2219 /* ETH_MTU = ip header len + tcp header len + payload */
2220 int tcp_data_len = ip_data_len - tcp_hlen;
2221 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2222
2223 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2224 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2225
2226 /* note the cycle below overwrites IP header data,
2227 but restores it from saved_ip_header before sending packet */
2228
2229 int is_last_frame = 0;
2230
2231 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2232 {
2233 uint16_t chunk_size = tcp_chunk_size;
2234
2235 /* check if this is the last frame */
2236 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2237 {
2238 is_last_frame = 1;
2239 chunk_size = tcp_data_len - tcp_send_offset;
2240 }
2241
2242 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2243
2244 /* add 4 TCP pseudoheader fields */
2245 /* copy IP source and destination fields */
2246 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2247
2248 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2249
2250 if (tcp_send_offset)
2251 {
2252 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2253 }
2254
2255 /* keep PUSH and FIN flags only for the last frame */
2256 if (!is_last_frame)
2257 {
2258 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2259 }
2260
2261 /* recalculate TCP checksum */
2262 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2263 p_tcpip_hdr->zeros = 0;
2264 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2265 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2266
2267 p_tcp_hdr->th_sum = 0;
2268
2269 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2270 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2271
2272 p_tcp_hdr->th_sum = tcp_checksum;
2273
2274 /* restore IP header */
2275 memcpy(eth_payload_data, saved_ip_header, hlen);
2276
2277 /* set IP data length and recalculate IP checksum */
2278 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2279
2280 /* increment IP id for subsequent frames */
2281 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2282
2283 ip->ip_sum = 0;
2284 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2285 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2286
2287 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2288 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
2289 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2290 0, (uint8_t *) dot1q_buffer);
2291
2292 /* add transferred count to TCP sequence number */
2293 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2294 ++send_count;
2295 }
2296
2297 /* Stop sending this frame */
2298 saved_size = 0;
2299 }
2300 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2301 {
2302 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2303
2304 /* maximum IP header length is 60 bytes */
2305 uint8_t saved_ip_header[60];
2306 memcpy(saved_ip_header, eth_payload_data, hlen);
2307
2308 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2309 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2310
2311 /* add 4 TCP pseudoheader fields */
2312 /* copy IP source and destination fields */
2313 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2314
2315 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2316 {
2317 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2318
2319 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2320 p_tcpip_hdr->zeros = 0;
2321 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2322 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2323
2324 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2325
2326 p_tcp_hdr->th_sum = 0;
2327
2328 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2329 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2330
2331 p_tcp_hdr->th_sum = tcp_checksum;
2332 }
2333 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2334 {
2335 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2336
2337 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2338 p_udpip_hdr->zeros = 0;
2339 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2340 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2341
2342 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2343
2344 p_udp_hdr->uh_sum = 0;
2345
2346 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2347 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2348
2349 p_udp_hdr->uh_sum = udp_checksum;
2350 }
2351
2352 /* restore IP header */
2353 memcpy(eth_payload_data, saved_ip_header, hlen);
2354 }
2355 }
2356 }
2357
2358 /* update tally counter */
2359 ++s->tally_counters.TxOk;
2360
2361 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2362
2363 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2364 (uint8_t *) dot1q_buffer);
2365
2366 /* restore card space if there was no recursion and reset offset */
2367 if (!s->cplus_txbuffer)
2368 {
2369 s->cplus_txbuffer = saved_buffer;
2370 s->cplus_txbuffer_len = saved_buffer_len;
2371 s->cplus_txbuffer_offset = 0;
2372 }
2373 else
2374 {
2375 qemu_free(saved_buffer);
2376 }
2377 }
2378 else
2379 {
2380 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
2381 }
2382
2383 return 1;
2384 }
2385
2386 static void rtl8139_cplus_transmit(RTL8139State *s)
2387 {
2388 int txcount = 0;
2389
2390 while (rtl8139_cplus_transmit_one(s))
2391 {
2392 ++txcount;
2393 }
2394
2395 /* Mark transfer completed */
2396 if (!txcount)
2397 {
2398 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2399 s->currCPlusTxDesc));
2400 }
2401 else
2402 {
2403 /* update interrupt status */
2404 s->IntrStatus |= TxOK;
2405 rtl8139_update_irq(s);
2406 }
2407 }
2408
2409 static void rtl8139_transmit(RTL8139State *s)
2410 {
2411 int descriptor = s->currTxDesc, txcount = 0;
2412
2413 /*while*/
2414 if (rtl8139_transmit_one(s, descriptor))
2415 {
2416 ++s->currTxDesc;
2417 s->currTxDesc %= 4;
2418 ++txcount;
2419 }
2420
2421 /* Mark transfer completed */
2422 if (!txcount)
2423 {
2424 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
2425 }
2426 }
2427
2428 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2429 {
2430
2431 int descriptor = txRegOffset/4;
2432
2433 /* handle C+ transmit mode register configuration */
2434
2435 if (s->cplus_enabled)
2436 {
2437 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2438
2439 /* handle Dump Tally Counters command */
2440 s->TxStatus[descriptor] = val;
2441
2442 if (descriptor == 0 && (val & 0x8))
2443 {
2444 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2445
2446 /* dump tally counters to specified memory location */
2447 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2448
2449 /* mark dump completed */
2450 s->TxStatus[0] &= ~0x8;
2451 }
2452
2453 return;
2454 }
2455
2456 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2457
2458 /* mask only reserved bits */
2459 val &= ~0xff00c000; /* these bits are reset on write */
2460 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2461
2462 s->TxStatus[descriptor] = val;
2463
2464 /* attempt to start transmission */
2465 rtl8139_transmit(s);
2466 }
2467
2468 static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2469 {
2470 uint32_t ret = s->TxStatus[txRegOffset/4];
2471
2472 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
2473
2474 return ret;
2475 }
2476
2477 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2478 {
2479 uint16_t ret = 0;
2480
2481 /* Simulate TSAD, it is read only anyway */
2482
2483 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2484 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2485 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2486 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2487
2488 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2489 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2490 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2491 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2492
2493 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2494 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2495 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2496 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2497
2498 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2499 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2500 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2501 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2502
2503
2504 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
2505
2506 return ret;
2507 }
2508
2509 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2510 {
2511 uint16_t ret = s->CSCR;
2512
2513 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
2514
2515 return ret;
2516 }
2517
2518 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2519 {
2520 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
2521
2522 s->TxAddr[txAddrOffset/4] = val;
2523 }
2524
2525 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2526 {
2527 uint32_t ret = s->TxAddr[txAddrOffset/4];
2528
2529 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
2530
2531 return ret;
2532 }
2533
2534 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2535 {
2536 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
2537
2538 /* this value is off by 16 */
2539 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2540
2541 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2542 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
2543 }
2544
2545 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2546 {
2547 /* this value is off by 16 */
2548 uint32_t ret = s->RxBufPtr - 0x10;
2549
2550 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2551
2552 return ret;
2553 }
2554
2555 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2556 {
2557 /* this value is NOT off by 16 */
2558 uint32_t ret = s->RxBufAddr;
2559
2560 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
2561
2562 return ret;
2563 }
2564
2565 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2566 {
2567 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
2568
2569 s->RxBuf = val;
2570
2571 /* may need to reset rxring here */
2572 }
2573
2574 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2575 {
2576 uint32_t ret = s->RxBuf;
2577
2578 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
2579
2580 return ret;
2581 }
2582
2583 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2584 {
2585 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
2586
2587 /* mask unwriteable bits */
2588 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2589
2590 s->IntrMask = val;
2591
2592 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2593 rtl8139_update_irq(s);
2594
2595 }
2596
2597 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2598 {
2599 uint32_t ret = s->IntrMask;
2600
2601 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
2602
2603 return ret;
2604 }
2605
2606 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2607 {
2608 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
2609
2610 #if 0
2611
2612 /* writing to ISR has no effect */
2613
2614 return;
2615
2616 #else
2617 uint16_t newStatus = s->IntrStatus & ~val;
2618
2619 /* mask unwriteable bits */
2620 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2621
2622 /* writing 1 to interrupt status register bit clears it */
2623 s->IntrStatus = 0;
2624 rtl8139_update_irq(s);
2625
2626 s->IntrStatus = newStatus;
2627 /*
2628 * Computing if we miss an interrupt here is not that correct but
2629 * considered that we should have had already an interrupt
2630 * and probably emulated is slower is better to assume this resetting was
2631 * done before testing on previous rtl8139_update_irq lead to IRQ loosing
2632 */
2633 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2634 rtl8139_update_irq(s);
2635
2636 #endif
2637 }
2638
2639 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2640 {
2641 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2642
2643 uint32_t ret = s->IntrStatus;
2644
2645 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
2646
2647 #if 0
2648
2649 /* reading ISR clears all interrupts */
2650 s->IntrStatus = 0;
2651
2652 rtl8139_update_irq(s);
2653
2654 #endif
2655
2656 return ret;
2657 }
2658
2659 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2660 {
2661 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
2662
2663 /* mask unwriteable bits */
2664 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2665
2666 s->MultiIntr = val;
2667 }
2668
2669 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2670 {
2671 uint32_t ret = s->MultiIntr;
2672
2673 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
2674
2675 return ret;
2676 }
2677
2678 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2679 {
2680 RTL8139State *s = opaque;
2681
2682 addr &= 0xff;
2683
2684 switch (addr)
2685 {
2686 case MAC0 ... MAC0+5:
2687 s->phys[addr - MAC0] = val;
2688 break;
2689 case MAC0+6 ... MAC0+7:
2690 /* reserved */
2691 break;
2692 case MAR0 ... MAR0+7:
2693 s->mult[addr - MAR0] = val;
2694 break;
2695 case ChipCmd:
2696 rtl8139_ChipCmd_write(s, val);
2697 break;
2698 case Cfg9346:
2699 rtl8139_Cfg9346_write(s, val);
2700 break;
2701 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2702 rtl8139_TxConfig_writeb(s, val);
2703 break;
2704 case Config0:
2705 rtl8139_Config0_write(s, val);
2706 break;
2707 case Config1:
2708 rtl8139_Config1_write(s, val);
2709 break;
2710 case Config3:
2711 rtl8139_Config3_write(s, val);
2712 break;
2713 case Config4:
2714 rtl8139_Config4_write(s, val);
2715 break;
2716 case Config5:
2717 rtl8139_Config5_write(s, val);
2718 break;
2719 case MediaStatus:
2720 /* ignore */
2721 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
2722 break;
2723
2724 case HltClk:
2725 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
2726 if (val == 'R')
2727 {
2728 s->clock_enabled = 1;
2729 }
2730 else if (val == 'H')
2731 {
2732 s->clock_enabled = 0;
2733 }
2734 break;
2735
2736 case TxThresh:
2737 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
2738 s->TxThresh = val;
2739 break;
2740
2741 case TxPoll:
2742 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
2743 if (val & (1 << 7))
2744 {
2745 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
2746 //rtl8139_cplus_transmit(s);
2747 }
2748 if (val & (1 << 6))
2749 {
2750 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
2751 rtl8139_cplus_transmit(s);
2752 }
2753
2754 break;
2755
2756 default:
2757 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
2758 break;
2759 }
2760 }
2761
2762 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2763 {
2764 RTL8139State *s = opaque;
2765
2766 addr &= 0xfe;
2767
2768 switch (addr)
2769 {
2770 case IntrMask:
2771 rtl8139_IntrMask_write(s, val);
2772 break;
2773
2774 case IntrStatus:
2775 rtl8139_IntrStatus_write(s, val);
2776 break;
2777
2778 case MultiIntr:
2779 rtl8139_MultiIntr_write(s, val);
2780 break;
2781
2782 case RxBufPtr:
2783 rtl8139_RxBufPtr_write(s, val);
2784 break;
2785
2786 case BasicModeCtrl:
2787 rtl8139_BasicModeCtrl_write(s, val);
2788 break;
2789 case BasicModeStatus:
2790 rtl8139_BasicModeStatus_write(s, val);
2791 break;
2792 case NWayAdvert:
2793 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
2794 s->NWayAdvert = val;
2795 break;
2796 case NWayLPAR:
2797 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
2798 break;
2799 case NWayExpansion:
2800 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
2801 s->NWayExpansion = val;
2802 break;
2803
2804 case CpCmd:
2805 rtl8139_CpCmd_write(s, val);
2806 break;
2807
2808 case IntrMitigate:
2809 rtl8139_IntrMitigate_write(s, val);
2810 break;
2811
2812 default:
2813 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
2814
2815 rtl8139_io_writeb(opaque, addr, val & 0xff);
2816 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2817 break;
2818 }
2819 }
2820
2821 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2822 {
2823 int64_t pci_time, next_time;
2824 uint32_t low_pci;
2825
2826 DEBUG_PRINT(("RTL8139: entered rtl8139_set_next_tctr_time\n"));
2827
2828 if (s->TimerExpire && current_time >= s->TimerExpire) {
2829 s->IntrStatus |= PCSTimeout;
2830 rtl8139_update_irq(s);
2831 }
2832
2833 /* Set QEMU timer only if needed that is
2834 * - TimerInt <> 0 (we have a timer)
2835 * - mask = 1 (we want an interrupt timer)
2836 * - irq = 0 (irq is not already active)
2837 * If any of above change we need to compute timer again
2838 * Also we must check if timer is passed without QEMU timer
2839 */
2840 s->TimerExpire = 0;
2841 if (!s->TimerInt) {
2842 return;
2843 }
2844
2845 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2846 get_ticks_per_sec());
2847 low_pci = pci_time & 0xffffffff;
2848 pci_time = pci_time - low_pci + s->TimerInt;
2849 if (low_pci >= s->TimerInt) {
2850 pci_time += 0x100000000LL;
2851 }
2852 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2853 PCI_FREQUENCY);
2854 s->TimerExpire = next_time;
2855
2856 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2857 qemu_mod_timer(s->timer, next_time);
2858 }
2859 }
2860
2861 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2862 {
2863 RTL8139State *s = opaque;
2864
2865 addr &= 0xfc;
2866
2867 switch (addr)
2868 {
2869 case RxMissed:
2870 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
2871 s->RxMissed = 0;
2872 break;
2873
2874 case TxConfig:
2875 rtl8139_TxConfig_write(s, val);
2876 break;
2877
2878 case RxConfig:
2879 rtl8139_RxConfig_write(s, val);
2880 break;
2881
2882 case TxStatus0 ... TxStatus0+4*4-1:
2883 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2884 break;
2885
2886 case TxAddr0 ... TxAddr0+4*4-1:
2887 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2888 break;
2889
2890 case RxBuf:
2891 rtl8139_RxBuf_write(s, val);
2892 break;
2893
2894 case RxRingAddrLO:
2895 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
2896 s->RxRingAddrLO = val;
2897 break;
2898
2899 case RxRingAddrHI:
2900 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
2901 s->RxRingAddrHI = val;
2902 break;
2903
2904 case Timer:
2905 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2906 s->TCTR_base = qemu_get_clock_ns(vm_clock);
2907 rtl8139_set_next_tctr_time(s, s->TCTR_base);
2908 break;
2909
2910 case FlashReg:
2911 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
2912 if (s->TimerInt != val) {
2913 s->TimerInt = val;
2914 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2915 }
2916 break;
2917
2918 default:
2919 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
2920 rtl8139_io_writeb(opaque, addr, val & 0xff);
2921 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2922 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2923 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2924 break;
2925 }
2926 }
2927
2928 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2929 {
2930 RTL8139State *s = opaque;
2931 int ret;
2932
2933 addr &= 0xff;
2934
2935 switch (addr)
2936 {
2937 case MAC0 ... MAC0+5:
2938 ret = s->phys[addr - MAC0];
2939 break;
2940 case MAC0+6 ... MAC0+7:
2941 ret = 0;
2942 break;
2943 case MAR0 ... MAR0+7:
2944 ret = s->mult[addr - MAR0];
2945 break;
2946 case ChipCmd:
2947 ret = rtl8139_ChipCmd_read(s);
2948 break;
2949 case Cfg9346:
2950 ret = rtl8139_Cfg9346_read(s);
2951 break;
2952 case Config0:
2953 ret = rtl8139_Config0_read(s);
2954 break;
2955 case Config1:
2956 ret = rtl8139_Config1_read(s);
2957 break;
2958 case Config3:
2959 ret = rtl8139_Config3_read(s);
2960 break;
2961 case Config4:
2962 ret = rtl8139_Config4_read(s);
2963 break;
2964 case Config5:
2965 ret = rtl8139_Config5_read(s);
2966 break;
2967
2968 case MediaStatus:
2969 ret = 0xd0;
2970 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
2971 break;
2972
2973 case HltClk:
2974 ret = s->clock_enabled;
2975 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
2976 break;
2977
2978 case PCIRevisionID:
2979 ret = RTL8139_PCI_REVID;
2980 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
2981 break;
2982
2983 case TxThresh:
2984 ret = s->TxThresh;
2985 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
2986 break;
2987
2988 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2989 ret = s->TxConfig >> 24;
2990 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
2991 break;
2992
2993 default:
2994 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
2995 ret = 0;
2996 break;
2997 }
2998
2999 return ret;
3000 }
3001
3002 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3003 {
3004 RTL8139State *s = opaque;
3005 uint32_t ret;
3006
3007 addr &= 0xfe; /* mask lower bit */
3008
3009 switch (addr)
3010 {
3011 case IntrMask:
3012 ret = rtl8139_IntrMask_read(s);
3013 break;
3014
3015 case IntrStatus:
3016 ret = rtl8139_IntrStatus_read(s);
3017 break;
3018
3019 case MultiIntr:
3020 ret = rtl8139_MultiIntr_read(s);
3021 break;
3022
3023 case RxBufPtr:
3024 ret = rtl8139_RxBufPtr_read(s);
3025 break;
3026
3027 case RxBufAddr:
3028 ret = rtl8139_RxBufAddr_read(s);
3029 break;
3030
3031 case BasicModeCtrl:
3032 ret = rtl8139_BasicModeCtrl_read(s);
3033 break;
3034 case BasicModeStatus:
3035 ret = rtl8139_BasicModeStatus_read(s);
3036 break;
3037 case NWayAdvert:
3038 ret = s->NWayAdvert;
3039 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
3040 break;
3041 case NWayLPAR:
3042 ret = s->NWayLPAR;
3043 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
3044 break;
3045 case NWayExpansion:
3046 ret = s->NWayExpansion;
3047 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
3048 break;
3049
3050 case CpCmd:
3051 ret = rtl8139_CpCmd_read(s);
3052 break;
3053
3054 case IntrMitigate:
3055 ret = rtl8139_IntrMitigate_read(s);
3056 break;
3057
3058 case TxSummary:
3059 ret = rtl8139_TSAD_read(s);
3060 break;
3061
3062 case CSCR:
3063 ret = rtl8139_CSCR_read(s);
3064 break;
3065
3066 default:
3067 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
3068
3069 ret = rtl8139_io_readb(opaque, addr);
3070 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3071
3072 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
3073 break;
3074 }
3075
3076 return ret;
3077 }
3078
3079 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3080 {
3081 RTL8139State *s = opaque;
3082 uint32_t ret;
3083
3084 addr &= 0xfc; /* also mask low 2 bits */
3085
3086 switch (addr)
3087 {
3088 case RxMissed:
3089 ret = s->RxMissed;
3090
3091 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
3092 break;
3093
3094 case TxConfig:
3095 ret = rtl8139_TxConfig_read(s);
3096 break;
3097
3098 case RxConfig:
3099 ret = rtl8139_RxConfig_read(s);
3100 break;
3101
3102 case TxStatus0 ... TxStatus0+4*4-1:
3103 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
3104 break;
3105
3106 case TxAddr0 ... TxAddr0+4*4-1:
3107 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3108 break;
3109
3110 case RxBuf:
3111 ret = rtl8139_RxBuf_read(s);
3112 break;
3113
3114 case RxRingAddrLO:
3115 ret = s->RxRingAddrLO;
3116 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
3117 break;
3118
3119 case RxRingAddrHI:
3120 ret = s->RxRingAddrHI;
3121 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3122 break;
3123
3124 case Timer:
3125 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
3126 PCI_FREQUENCY, get_ticks_per_sec());
3127 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3128 break;
3129
3130 case FlashReg:
3131 ret = s->TimerInt;
3132 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
3133 break;
3134
3135 default:
3136 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
3137
3138 ret = rtl8139_io_readb(opaque, addr);
3139 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3140 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3141 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3142
3143 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
3144 break;
3145 }
3146
3147 return ret;
3148 }
3149
3150 /* */
3151
3152 static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3153 {
3154 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3155 }
3156
3157 static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3158 {
3159 rtl8139_io_writew(opaque, addr & 0xFF, val);
3160 }
3161
3162 static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3163 {
3164 rtl8139_io_writel(opaque, addr & 0xFF, val);
3165 }
3166
3167 static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3168 {
3169 return rtl8139_io_readb(opaque, addr & 0xFF);
3170 }
3171
3172 static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3173 {
3174 return rtl8139_io_readw(opaque, addr & 0xFF);
3175 }
3176
3177 static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3178 {
3179 return rtl8139_io_readl(opaque, addr & 0xFF);
3180 }
3181
3182 /* */
3183
3184 static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3185 {
3186 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3187 }
3188
3189 static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3190 {
3191 rtl8139_io_writew(opaque, addr & 0xFF, val);
3192 }
3193
3194 static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3195 {
3196 rtl8139_io_writel(opaque, addr & 0xFF, val);
3197 }
3198
3199 static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3200 {
3201 return rtl8139_io_readb(opaque, addr & 0xFF);
3202 }
3203
3204 static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3205 {
3206 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
3207 return val;
3208 }
3209
3210 static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3211 {
3212 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
3213 return val;
3214 }
3215
3216 static int rtl8139_post_load(void *opaque, int version_id)
3217 {
3218 RTL8139State* s = opaque;
3219 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3220 if (version_id < 4) {
3221 s->cplus_enabled = s->CpCmd != 0;
3222 }
3223
3224 return 0;
3225 }
3226
3227 static bool rtl8139_hotplug_ready_needed(void *opaque)
3228 {
3229 return qdev_machine_modified();
3230 }
3231
3232 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3233 .name = "rtl8139/hotplug_ready",
3234 .version_id = 1,
3235 .minimum_version_id = 1,
3236 .minimum_version_id_old = 1,
3237 .fields = (VMStateField []) {
3238 VMSTATE_END_OF_LIST()
3239 }
3240 };
3241
3242 static void rtl8139_pre_save(void *opaque)
3243 {
3244 RTL8139State* s = opaque;
3245 int64_t current_time = qemu_get_clock_ns(vm_clock);
3246
3247 /* set IntrStatus correctly */
3248 rtl8139_set_next_tctr_time(s, current_time);
3249 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3250 get_ticks_per_sec());
3251 s->rtl8139_mmio_io_addr_dummy = s->rtl8139_mmio_io_addr;
3252 }
3253
3254 static const VMStateDescription vmstate_rtl8139 = {
3255 .name = "rtl8139",
3256 .version_id = 4,
3257 .minimum_version_id = 3,
3258 .minimum_version_id_old = 3,
3259 .post_load = rtl8139_post_load,
3260 .pre_save = rtl8139_pre_save,
3261 .fields = (VMStateField []) {
3262 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3263 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3264 VMSTATE_BUFFER(mult, RTL8139State),
3265 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3266 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3267
3268 VMSTATE_UINT32(RxBuf, RTL8139State),
3269 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3270 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3271 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3272
3273 VMSTATE_UINT16(IntrStatus, RTL8139State),
3274 VMSTATE_UINT16(IntrMask, RTL8139State),
3275
3276 VMSTATE_UINT32(TxConfig, RTL8139State),
3277 VMSTATE_UINT32(RxConfig, RTL8139State),
3278 VMSTATE_UINT32(RxMissed, RTL8139State),
3279 VMSTATE_UINT16(CSCR, RTL8139State),
3280
3281 VMSTATE_UINT8(Cfg9346, RTL8139State),
3282 VMSTATE_UINT8(Config0, RTL8139State),
3283 VMSTATE_UINT8(Config1, RTL8139State),
3284 VMSTATE_UINT8(Config3, RTL8139State),
3285 VMSTATE_UINT8(Config4, RTL8139State),
3286 VMSTATE_UINT8(Config5, RTL8139State),
3287
3288 VMSTATE_UINT8(clock_enabled, RTL8139State),
3289 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3290
3291 VMSTATE_UINT16(MultiIntr, RTL8139State),
3292
3293 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3294 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3295 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3296 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3297 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3298
3299 VMSTATE_UINT16(CpCmd, RTL8139State),
3300 VMSTATE_UINT8(TxThresh, RTL8139State),
3301
3302 VMSTATE_UNUSED(4),
3303 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
3304 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
3305
3306 VMSTATE_UINT32(currTxDesc, RTL8139State),
3307 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3308 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3309 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3310 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3311
3312 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3313 VMSTATE_INT32(eeprom.mode, RTL8139State),
3314 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3315 VMSTATE_UINT8(eeprom.address, RTL8139State),
3316 VMSTATE_UINT16(eeprom.input, RTL8139State),
3317 VMSTATE_UINT16(eeprom.output, RTL8139State),
3318
3319 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3320 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3321 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3322 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3323
3324 VMSTATE_UINT32(TCTR, RTL8139State),
3325 VMSTATE_UINT32(TimerInt, RTL8139State),
3326 VMSTATE_INT64(TCTR_base, RTL8139State),
3327
3328 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3329 vmstate_tally_counters, RTL8139TallyCounters),
3330
3331 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3332 VMSTATE_END_OF_LIST()
3333 },
3334 .subsections = (VMStateSubsection []) {
3335 {
3336 .vmsd = &vmstate_rtl8139_hotplug_ready,
3337 .needed = rtl8139_hotplug_ready_needed,
3338 }, {
3339 /* empty */
3340 }
3341 }
3342 };
3343
3344 /***********************************************************/
3345 /* PCI RTL8139 definitions */
3346
3347 static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
3348 pcibus_t addr, pcibus_t size, int type)
3349 {
3350 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
3351
3352 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3353 }
3354
3355 static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
3356 pcibus_t addr, pcibus_t size, int type)
3357 {
3358 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
3359
3360 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3361 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3362
3363 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3364 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3365
3366 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3367 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3368 }
3369
3370 static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
3371 rtl8139_mmio_readb,
3372 rtl8139_mmio_readw,
3373 rtl8139_mmio_readl,
3374 };
3375
3376 static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
3377 rtl8139_mmio_writeb,
3378 rtl8139_mmio_writew,
3379 rtl8139_mmio_writel,
3380 };
3381
3382 static void rtl8139_timer(void *opaque)
3383 {
3384 RTL8139State *s = opaque;
3385
3386 if (!s->clock_enabled)
3387 {
3388 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3389 return;
3390 }
3391
3392 s->IntrStatus |= PCSTimeout;
3393 rtl8139_update_irq(s);
3394 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3395 }
3396
3397 static void rtl8139_cleanup(VLANClientState *nc)
3398 {
3399 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
3400
3401 s->nic = NULL;
3402 }
3403
3404 static int pci_rtl8139_uninit(PCIDevice *dev)
3405 {
3406 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3407
3408 cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
3409 if (s->cplus_txbuffer) {
3410 qemu_free(s->cplus_txbuffer);
3411 s->cplus_txbuffer = NULL;
3412 }
3413 qemu_del_timer(s->timer);
3414 qemu_free_timer(s->timer);
3415 qemu_del_vlan_client(&s->nic->nc);
3416 return 0;
3417 }
3418
3419 static NetClientInfo net_rtl8139_info = {
3420 .type = NET_CLIENT_TYPE_NIC,
3421 .size = sizeof(NICState),
3422 .can_receive = rtl8139_can_receive,
3423 .receive = rtl8139_receive,
3424 .cleanup = rtl8139_cleanup,
3425 };
3426
3427 static int pci_rtl8139_init(PCIDevice *dev)
3428 {
3429 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
3430 uint8_t *pci_conf;
3431
3432 pci_conf = s->dev.config;
3433 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
3434 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
3435 pci_conf[PCI_REVISION_ID] = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3436 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
3437 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
3438 /* TODO: start of capability list, but no capability
3439 * list bit in status register, and offset 0xdc seems unused. */
3440 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
3441
3442 /* I/O handler for memory-mapped I/O */
3443 s->rtl8139_mmio_io_addr =
3444 cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s,
3445 DEVICE_LITTLE_ENDIAN);
3446
3447 pci_register_bar(&s->dev, 0, 0x100,
3448 PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map);
3449
3450 pci_register_bar(&s->dev, 1, 0x100,
3451 PCI_BASE_ADDRESS_SPACE_MEMORY, rtl8139_mmio_map);
3452
3453 qemu_macaddr_default_if_unset(&s->conf.macaddr);
3454
3455 /* prepare eeprom */
3456 s->eeprom.contents[0] = 0x8129;
3457 #if 1
3458 /* PCI vendor and device ID should be mirrored here */
3459 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3460 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3461 #endif
3462 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3463 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3464 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3465
3466 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3467 dev->qdev.info->name, dev->qdev.id, s);
3468 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
3469
3470 s->cplus_txbuffer = NULL;
3471 s->cplus_txbuffer_len = 0;
3472 s->cplus_txbuffer_offset = 0;
3473
3474 s->TimerExpire = 0;
3475 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
3476 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3477
3478 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3479
3480 return 0;
3481 }
3482
3483 static PCIDeviceInfo rtl8139_info = {
3484 .qdev.name = "rtl8139",
3485 .qdev.size = sizeof(RTL8139State),
3486 .qdev.reset = rtl8139_reset,
3487 .qdev.vmsd = &vmstate_rtl8139,
3488 .init = pci_rtl8139_init,
3489 .exit = pci_rtl8139_uninit,
3490 .romfile = "pxe-rtl8139.rom",
3491 .qdev.props = (Property[]) {
3492 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3493 DEFINE_PROP_END_OF_LIST(),
3494 }
3495 };
3496
3497 static void rtl8139_register_devices(void)
3498 {
3499 pci_qdev_register(&rtl8139_info);
3500 }
3501
3502 device_init(rtl8139_register_devices)
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