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1 /**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
49 */
50
51 /* For crc32 */
52 #include <zlib.h>
53
54 #include "hw.h"
55 #include "pci.h"
56 #include "dma.h"
57 #include "qemu-timer.h"
58 #include "net.h"
59 #include "loader.h"
60 #include "sysemu.h"
61 #include "iov.h"
62
63 /* debug RTL8139 card */
64 //#define DEBUG_RTL8139 1
65
66 #define PCI_FREQUENCY 33000000L
67
68 #define SET_MASKED(input, mask, curr) \
69 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
70
71 /* arg % size for size which is a power of 2 */
72 #define MOD2(input, size) \
73 ( ( input ) & ( size - 1 ) )
74
75 #define ETHER_ADDR_LEN 6
76 #define ETHER_TYPE_LEN 2
77 #define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
78 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
79 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
80 #define ETH_MTU 1500
81
82 #define VLAN_TCI_LEN 2
83 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
84
85 #if defined (DEBUG_RTL8139)
86 # define DPRINTF(fmt, ...) \
87 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
88 #else
89 static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
90 {
91 return 0;
92 }
93 #endif
94
95 /* Symbolic offsets to registers. */
96 enum RTL8139_registers {
97 MAC0 = 0, /* Ethernet hardware address. */
98 MAR0 = 8, /* Multicast filter. */
99 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
100 /* Dump Tally Conter control register(64bit). C+ mode only */
101 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
102 RxBuf = 0x30,
103 ChipCmd = 0x37,
104 RxBufPtr = 0x38,
105 RxBufAddr = 0x3A,
106 IntrMask = 0x3C,
107 IntrStatus = 0x3E,
108 TxConfig = 0x40,
109 RxConfig = 0x44,
110 Timer = 0x48, /* A general-purpose counter. */
111 RxMissed = 0x4C, /* 24 bits valid, write clears. */
112 Cfg9346 = 0x50,
113 Config0 = 0x51,
114 Config1 = 0x52,
115 FlashReg = 0x54,
116 MediaStatus = 0x58,
117 Config3 = 0x59,
118 Config4 = 0x5A, /* absent on RTL-8139A */
119 HltClk = 0x5B,
120 MultiIntr = 0x5C,
121 PCIRevisionID = 0x5E,
122 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
123 BasicModeCtrl = 0x62,
124 BasicModeStatus = 0x64,
125 NWayAdvert = 0x66,
126 NWayLPAR = 0x68,
127 NWayExpansion = 0x6A,
128 /* Undocumented registers, but required for proper operation. */
129 FIFOTMS = 0x70, /* FIFO Control and test. */
130 CSCR = 0x74, /* Chip Status and Configuration Register. */
131 PARA78 = 0x78,
132 PARA7c = 0x7c, /* Magic transceiver parameter register. */
133 Config5 = 0xD8, /* absent on RTL-8139A */
134 /* C+ mode */
135 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
136 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
137 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
138 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
139 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
140 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
141 TxThresh = 0xEC, /* Early Tx threshold */
142 };
143
144 enum ClearBitMasks {
145 MultiIntrClear = 0xF000,
146 ChipCmdClear = 0xE2,
147 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
148 };
149
150 enum ChipCmdBits {
151 CmdReset = 0x10,
152 CmdRxEnb = 0x08,
153 CmdTxEnb = 0x04,
154 RxBufEmpty = 0x01,
155 };
156
157 /* C+ mode */
158 enum CplusCmdBits {
159 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
160 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
161 CPlusRxEnb = 0x0002,
162 CPlusTxEnb = 0x0001,
163 };
164
165 /* Interrupt register bits, using my own meaningful names. */
166 enum IntrStatusBits {
167 PCIErr = 0x8000,
168 PCSTimeout = 0x4000,
169 RxFIFOOver = 0x40,
170 RxUnderrun = 0x20,
171 RxOverflow = 0x10,
172 TxErr = 0x08,
173 TxOK = 0x04,
174 RxErr = 0x02,
175 RxOK = 0x01,
176
177 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
178 };
179
180 enum TxStatusBits {
181 TxHostOwns = 0x2000,
182 TxUnderrun = 0x4000,
183 TxStatOK = 0x8000,
184 TxOutOfWindow = 0x20000000,
185 TxAborted = 0x40000000,
186 TxCarrierLost = 0x80000000,
187 };
188 enum RxStatusBits {
189 RxMulticast = 0x8000,
190 RxPhysical = 0x4000,
191 RxBroadcast = 0x2000,
192 RxBadSymbol = 0x0020,
193 RxRunt = 0x0010,
194 RxTooLong = 0x0008,
195 RxCRCErr = 0x0004,
196 RxBadAlign = 0x0002,
197 RxStatusOK = 0x0001,
198 };
199
200 /* Bits in RxConfig. */
201 enum rx_mode_bits {
202 AcceptErr = 0x20,
203 AcceptRunt = 0x10,
204 AcceptBroadcast = 0x08,
205 AcceptMulticast = 0x04,
206 AcceptMyPhys = 0x02,
207 AcceptAllPhys = 0x01,
208 };
209
210 /* Bits in TxConfig. */
211 enum tx_config_bits {
212
213 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
214 TxIFGShift = 24,
215 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
216 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
217 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
218 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
219
220 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
221 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
222 TxClearAbt = (1 << 0), /* Clear abort (WO) */
223 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
224 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
225
226 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
227 };
228
229
230 /* Transmit Status of All Descriptors (TSAD) Register */
231 enum TSAD_bits {
232 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
233 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
234 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
235 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
236 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
237 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
238 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
239 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
240 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
241 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
242 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
243 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
244 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
245 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
246 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
247 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
248 };
249
250
251 /* Bits in Config1 */
252 enum Config1Bits {
253 Cfg1_PM_Enable = 0x01,
254 Cfg1_VPD_Enable = 0x02,
255 Cfg1_PIO = 0x04,
256 Cfg1_MMIO = 0x08,
257 LWAKE = 0x10, /* not on 8139, 8139A */
258 Cfg1_Driver_Load = 0x20,
259 Cfg1_LED0 = 0x40,
260 Cfg1_LED1 = 0x80,
261 SLEEP = (1 << 1), /* only on 8139, 8139A */
262 PWRDN = (1 << 0), /* only on 8139, 8139A */
263 };
264
265 /* Bits in Config3 */
266 enum Config3Bits {
267 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
268 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
269 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
270 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
271 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
272 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
273 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
274 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
275 };
276
277 /* Bits in Config4 */
278 enum Config4Bits {
279 LWPTN = (1 << 2), /* not on 8139, 8139A */
280 };
281
282 /* Bits in Config5 */
283 enum Config5Bits {
284 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
285 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
286 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
287 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
288 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
289 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
290 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
291 };
292
293 enum RxConfigBits {
294 /* rx fifo threshold */
295 RxCfgFIFOShift = 13,
296 RxCfgFIFONone = (7 << RxCfgFIFOShift),
297
298 /* Max DMA burst */
299 RxCfgDMAShift = 8,
300 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
301
302 /* rx ring buffer length */
303 RxCfgRcv8K = 0,
304 RxCfgRcv16K = (1 << 11),
305 RxCfgRcv32K = (1 << 12),
306 RxCfgRcv64K = (1 << 11) | (1 << 12),
307
308 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
309 RxNoWrap = (1 << 7),
310 };
311
312 /* Twister tuning parameters from RealTek.
313 Completely undocumented, but required to tune bad links on some boards. */
314 /*
315 enum CSCRBits {
316 CSCR_LinkOKBit = 0x0400,
317 CSCR_LinkChangeBit = 0x0800,
318 CSCR_LinkStatusBits = 0x0f000,
319 CSCR_LinkDownOffCmd = 0x003c0,
320 CSCR_LinkDownCmd = 0x0f3c0,
321 */
322 enum CSCRBits {
323 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
324 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
325 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
326 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
327 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
328 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
329 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
330 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
331 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
332 };
333
334 enum Cfg9346Bits {
335 Cfg9346_Normal = 0x00,
336 Cfg9346_Autoload = 0x40,
337 Cfg9346_Programming = 0x80,
338 Cfg9346_ConfigWrite = 0xC0,
339 };
340
341 typedef enum {
342 CH_8139 = 0,
343 CH_8139_K,
344 CH_8139A,
345 CH_8139A_G,
346 CH_8139B,
347 CH_8130,
348 CH_8139C,
349 CH_8100,
350 CH_8100B_8139D,
351 CH_8101,
352 } chip_t;
353
354 enum chip_flags {
355 HasHltClk = (1 << 0),
356 HasLWake = (1 << 1),
357 };
358
359 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
360 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
361 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
362
363 #define RTL8139_PCI_REVID_8139 0x10
364 #define RTL8139_PCI_REVID_8139CPLUS 0x20
365
366 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
367
368 /* Size is 64 * 16bit words */
369 #define EEPROM_9346_ADDR_BITS 6
370 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
371 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
372
373 enum Chip9346Operation
374 {
375 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
376 Chip9346_op_read = 0x80, /* 10 AAAAAA */
377 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
378 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
379 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
380 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
381 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
382 };
383
384 enum Chip9346Mode
385 {
386 Chip9346_none = 0,
387 Chip9346_enter_command_mode,
388 Chip9346_read_command,
389 Chip9346_data_read, /* from output register */
390 Chip9346_data_write, /* to input register, then to contents at specified address */
391 Chip9346_data_write_all, /* to input register, then filling contents */
392 };
393
394 typedef struct EEprom9346
395 {
396 uint16_t contents[EEPROM_9346_SIZE];
397 int mode;
398 uint32_t tick;
399 uint8_t address;
400 uint16_t input;
401 uint16_t output;
402
403 uint8_t eecs;
404 uint8_t eesk;
405 uint8_t eedi;
406 uint8_t eedo;
407 } EEprom9346;
408
409 typedef struct RTL8139TallyCounters
410 {
411 /* Tally counters */
412 uint64_t TxOk;
413 uint64_t RxOk;
414 uint64_t TxERR;
415 uint32_t RxERR;
416 uint16_t MissPkt;
417 uint16_t FAE;
418 uint32_t Tx1Col;
419 uint32_t TxMCol;
420 uint64_t RxOkPhy;
421 uint64_t RxOkBrd;
422 uint32_t RxOkMul;
423 uint16_t TxAbt;
424 uint16_t TxUndrn;
425 } RTL8139TallyCounters;
426
427 /* Clears all tally counters */
428 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
429
430 typedef struct RTL8139State {
431 PCIDevice dev;
432 uint8_t phys[8]; /* mac address */
433 uint8_t mult[8]; /* multicast mask array */
434
435 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
436 uint32_t TxAddr[4]; /* TxAddr0 */
437 uint32_t RxBuf; /* Receive buffer */
438 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
439 uint32_t RxBufPtr;
440 uint32_t RxBufAddr;
441
442 uint16_t IntrStatus;
443 uint16_t IntrMask;
444
445 uint32_t TxConfig;
446 uint32_t RxConfig;
447 uint32_t RxMissed;
448
449 uint16_t CSCR;
450
451 uint8_t Cfg9346;
452 uint8_t Config0;
453 uint8_t Config1;
454 uint8_t Config3;
455 uint8_t Config4;
456 uint8_t Config5;
457
458 uint8_t clock_enabled;
459 uint8_t bChipCmdState;
460
461 uint16_t MultiIntr;
462
463 uint16_t BasicModeCtrl;
464 uint16_t BasicModeStatus;
465 uint16_t NWayAdvert;
466 uint16_t NWayLPAR;
467 uint16_t NWayExpansion;
468
469 uint16_t CpCmd;
470 uint8_t TxThresh;
471
472 NICState *nic;
473 NICConf conf;
474
475 /* C ring mode */
476 uint32_t currTxDesc;
477
478 /* C+ mode */
479 uint32_t cplus_enabled;
480
481 uint32_t currCPlusRxDesc;
482 uint32_t currCPlusTxDesc;
483
484 uint32_t RxRingAddrLO;
485 uint32_t RxRingAddrHI;
486
487 EEprom9346 eeprom;
488
489 uint32_t TCTR;
490 uint32_t TimerInt;
491 int64_t TCTR_base;
492
493 /* Tally counters */
494 RTL8139TallyCounters tally_counters;
495
496 /* Non-persistent data */
497 uint8_t *cplus_txbuffer;
498 int cplus_txbuffer_len;
499 int cplus_txbuffer_offset;
500
501 /* PCI interrupt timer */
502 QEMUTimer *timer;
503 int64_t TimerExpire;
504
505 MemoryRegion bar_io;
506 MemoryRegion bar_mem;
507
508 /* Support migration to/from old versions */
509 int rtl8139_mmio_io_addr_dummy;
510 } RTL8139State;
511
512 /* Writes tally counters to memory via DMA */
513 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
514
515 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
516
517 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
518 {
519 DPRINTF("eeprom command 0x%02x\n", command);
520
521 switch (command & Chip9346_op_mask)
522 {
523 case Chip9346_op_read:
524 {
525 eeprom->address = command & EEPROM_9346_ADDR_MASK;
526 eeprom->output = eeprom->contents[eeprom->address];
527 eeprom->eedo = 0;
528 eeprom->tick = 0;
529 eeprom->mode = Chip9346_data_read;
530 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
531 eeprom->address, eeprom->output);
532 }
533 break;
534
535 case Chip9346_op_write:
536 {
537 eeprom->address = command & EEPROM_9346_ADDR_MASK;
538 eeprom->input = 0;
539 eeprom->tick = 0;
540 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
541 DPRINTF("eeprom begin write to address 0x%02x\n",
542 eeprom->address);
543 }
544 break;
545 default:
546 eeprom->mode = Chip9346_none;
547 switch (command & Chip9346_op_ext_mask)
548 {
549 case Chip9346_op_write_enable:
550 DPRINTF("eeprom write enabled\n");
551 break;
552 case Chip9346_op_write_all:
553 DPRINTF("eeprom begin write all\n");
554 break;
555 case Chip9346_op_write_disable:
556 DPRINTF("eeprom write disabled\n");
557 break;
558 }
559 break;
560 }
561 }
562
563 static void prom9346_shift_clock(EEprom9346 *eeprom)
564 {
565 int bit = eeprom->eedi?1:0;
566
567 ++ eeprom->tick;
568
569 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
570 eeprom->eedo);
571
572 switch (eeprom->mode)
573 {
574 case Chip9346_enter_command_mode:
575 if (bit)
576 {
577 eeprom->mode = Chip9346_read_command;
578 eeprom->tick = 0;
579 eeprom->input = 0;
580 DPRINTF("eeprom: +++ synchronized, begin command read\n");
581 }
582 break;
583
584 case Chip9346_read_command:
585 eeprom->input = (eeprom->input << 1) | (bit & 1);
586 if (eeprom->tick == 8)
587 {
588 prom9346_decode_command(eeprom, eeprom->input & 0xff);
589 }
590 break;
591
592 case Chip9346_data_read:
593 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
594 eeprom->output <<= 1;
595 if (eeprom->tick == 16)
596 {
597 #if 1
598 // the FreeBSD drivers (rl and re) don't explicitly toggle
599 // CS between reads (or does setting Cfg9346 to 0 count too?),
600 // so we need to enter wait-for-command state here
601 eeprom->mode = Chip9346_enter_command_mode;
602 eeprom->input = 0;
603 eeprom->tick = 0;
604
605 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
606 #else
607 // original behaviour
608 ++eeprom->address;
609 eeprom->address &= EEPROM_9346_ADDR_MASK;
610 eeprom->output = eeprom->contents[eeprom->address];
611 eeprom->tick = 0;
612
613 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
614 eeprom->address, eeprom->output);
615 #endif
616 }
617 break;
618
619 case Chip9346_data_write:
620 eeprom->input = (eeprom->input << 1) | (bit & 1);
621 if (eeprom->tick == 16)
622 {
623 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
624 eeprom->address, eeprom->input);
625
626 eeprom->contents[eeprom->address] = eeprom->input;
627 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
628 eeprom->tick = 0;
629 eeprom->input = 0;
630 }
631 break;
632
633 case Chip9346_data_write_all:
634 eeprom->input = (eeprom->input << 1) | (bit & 1);
635 if (eeprom->tick == 16)
636 {
637 int i;
638 for (i = 0; i < EEPROM_9346_SIZE; i++)
639 {
640 eeprom->contents[i] = eeprom->input;
641 }
642 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
643
644 eeprom->mode = Chip9346_enter_command_mode;
645 eeprom->tick = 0;
646 eeprom->input = 0;
647 }
648 break;
649
650 default:
651 break;
652 }
653 }
654
655 static int prom9346_get_wire(RTL8139State *s)
656 {
657 EEprom9346 *eeprom = &s->eeprom;
658 if (!eeprom->eecs)
659 return 0;
660
661 return eeprom->eedo;
662 }
663
664 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
665 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
666 {
667 EEprom9346 *eeprom = &s->eeprom;
668 uint8_t old_eecs = eeprom->eecs;
669 uint8_t old_eesk = eeprom->eesk;
670
671 eeprom->eecs = eecs;
672 eeprom->eesk = eesk;
673 eeprom->eedi = eedi;
674
675 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
676 eeprom->eesk, eeprom->eedi, eeprom->eedo);
677
678 if (!old_eecs && eecs)
679 {
680 /* Synchronize start */
681 eeprom->tick = 0;
682 eeprom->input = 0;
683 eeprom->output = 0;
684 eeprom->mode = Chip9346_enter_command_mode;
685
686 DPRINTF("=== eeprom: begin access, enter command mode\n");
687 }
688
689 if (!eecs)
690 {
691 DPRINTF("=== eeprom: end access\n");
692 return;
693 }
694
695 if (!old_eesk && eesk)
696 {
697 /* SK front rules */
698 prom9346_shift_clock(eeprom);
699 }
700 }
701
702 static void rtl8139_update_irq(RTL8139State *s)
703 {
704 int isr;
705 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
706
707 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
708 s->IntrMask);
709
710 qemu_set_irq(s->dev.irq[0], (isr != 0));
711 }
712
713 static int rtl8139_RxWrap(RTL8139State *s)
714 {
715 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
716 return (s->RxConfig & (1 << 7));
717 }
718
719 static int rtl8139_receiver_enabled(RTL8139State *s)
720 {
721 return s->bChipCmdState & CmdRxEnb;
722 }
723
724 static int rtl8139_transmitter_enabled(RTL8139State *s)
725 {
726 return s->bChipCmdState & CmdTxEnb;
727 }
728
729 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
730 {
731 return s->CpCmd & CPlusRxEnb;
732 }
733
734 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
735 {
736 return s->CpCmd & CPlusTxEnb;
737 }
738
739 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
740 {
741 if (s->RxBufAddr + size > s->RxBufferSize)
742 {
743 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
744
745 /* write packet data */
746 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
747 {
748 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
749
750 if (size > wrapped)
751 {
752 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
753 buf, size-wrapped);
754 }
755
756 /* reset buffer pointer */
757 s->RxBufAddr = 0;
758
759 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
760 buf + (size-wrapped), wrapped);
761
762 s->RxBufAddr = wrapped;
763
764 return;
765 }
766 }
767
768 /* non-wrapping path or overwrapping enabled */
769 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, buf, size);
770
771 s->RxBufAddr += size;
772 }
773
774 #define MIN_BUF_SIZE 60
775 static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
776 {
777 #if TARGET_PHYS_ADDR_BITS > 32
778 return low | ((target_phys_addr_t)high << 32);
779 #else
780 return low;
781 #endif
782 }
783
784 /* Workaround for buggy guest driver such as linux who allocates rx
785 * rings after the receiver were enabled. */
786 static bool rtl8139_cp_rx_valid(RTL8139State *s)
787 {
788 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0);
789 }
790
791 static int rtl8139_can_receive(VLANClientState *nc)
792 {
793 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
794 int avail;
795
796 /* Receive (drop) packets if card is disabled. */
797 if (!s->clock_enabled)
798 return 1;
799 if (!rtl8139_receiver_enabled(s))
800 return 1;
801
802 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) {
803 /* ??? Flow control not implemented in c+ mode.
804 This is a hack to work around slirp deficiencies anyway. */
805 return 1;
806 } else {
807 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
808 s->RxBufferSize);
809 return (avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow));
810 }
811 }
812
813 static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
814 {
815 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
816 /* size is the length of the buffer passed to the driver */
817 int size = size_;
818 const uint8_t *dot1q_buf = NULL;
819
820 uint32_t packet_header = 0;
821
822 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
823 static const uint8_t broadcast_macaddr[6] =
824 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
825
826 DPRINTF(">>> received len=%d\n", size);
827
828 /* test if board clock is stopped */
829 if (!s->clock_enabled)
830 {
831 DPRINTF("stopped ==========================\n");
832 return -1;
833 }
834
835 /* first check if receiver is enabled */
836
837 if (!rtl8139_receiver_enabled(s))
838 {
839 DPRINTF("receiver disabled ================\n");
840 return -1;
841 }
842
843 /* XXX: check this */
844 if (s->RxConfig & AcceptAllPhys) {
845 /* promiscuous: receive all */
846 DPRINTF(">>> packet received in promiscuous mode\n");
847
848 } else {
849 if (!memcmp(buf, broadcast_macaddr, 6)) {
850 /* broadcast address */
851 if (!(s->RxConfig & AcceptBroadcast))
852 {
853 DPRINTF(">>> broadcast packet rejected\n");
854
855 /* update tally counter */
856 ++s->tally_counters.RxERR;
857
858 return size;
859 }
860
861 packet_header |= RxBroadcast;
862
863 DPRINTF(">>> broadcast packet received\n");
864
865 /* update tally counter */
866 ++s->tally_counters.RxOkBrd;
867
868 } else if (buf[0] & 0x01) {
869 /* multicast */
870 if (!(s->RxConfig & AcceptMulticast))
871 {
872 DPRINTF(">>> multicast packet rejected\n");
873
874 /* update tally counter */
875 ++s->tally_counters.RxERR;
876
877 return size;
878 }
879
880 int mcast_idx = compute_mcast_idx(buf);
881
882 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
883 {
884 DPRINTF(">>> multicast address mismatch\n");
885
886 /* update tally counter */
887 ++s->tally_counters.RxERR;
888
889 return size;
890 }
891
892 packet_header |= RxMulticast;
893
894 DPRINTF(">>> multicast packet received\n");
895
896 /* update tally counter */
897 ++s->tally_counters.RxOkMul;
898
899 } else if (s->phys[0] == buf[0] &&
900 s->phys[1] == buf[1] &&
901 s->phys[2] == buf[2] &&
902 s->phys[3] == buf[3] &&
903 s->phys[4] == buf[4] &&
904 s->phys[5] == buf[5]) {
905 /* match */
906 if (!(s->RxConfig & AcceptMyPhys))
907 {
908 DPRINTF(">>> rejecting physical address matching packet\n");
909
910 /* update tally counter */
911 ++s->tally_counters.RxERR;
912
913 return size;
914 }
915
916 packet_header |= RxPhysical;
917
918 DPRINTF(">>> physical address matching packet received\n");
919
920 /* update tally counter */
921 ++s->tally_counters.RxOkPhy;
922
923 } else {
924
925 DPRINTF(">>> unknown packet\n");
926
927 /* update tally counter */
928 ++s->tally_counters.RxERR;
929
930 return size;
931 }
932 }
933
934 /* if too small buffer, then expand it
935 * Include some tailroom in case a vlan tag is later removed. */
936 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
937 memcpy(buf1, buf, size);
938 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
939 buf = buf1;
940 if (size < MIN_BUF_SIZE) {
941 size = MIN_BUF_SIZE;
942 }
943 }
944
945 if (rtl8139_cp_receiver_enabled(s))
946 {
947 if (!rtl8139_cp_rx_valid(s)) {
948 return size;
949 }
950
951 DPRINTF("in C+ Rx mode ================\n");
952
953 /* begin C+ receiver mode */
954
955 /* w0 ownership flag */
956 #define CP_RX_OWN (1<<31)
957 /* w0 end of ring flag */
958 #define CP_RX_EOR (1<<30)
959 /* w0 bits 0...12 : buffer size */
960 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
961 /* w1 tag available flag */
962 #define CP_RX_TAVA (1<<16)
963 /* w1 bits 0...15 : VLAN tag */
964 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
965 /* w2 low 32bit of Rx buffer ptr */
966 /* w3 high 32bit of Rx buffer ptr */
967
968 int descriptor = s->currCPlusRxDesc;
969 dma_addr_t cplus_rx_ring_desc;
970
971 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
972 cplus_rx_ring_desc += 16 * descriptor;
973
974 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
975 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
976 s->RxRingAddrLO, cplus_rx_ring_desc);
977
978 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
979
980 pci_dma_read(&s->dev, cplus_rx_ring_desc, &val, 4);
981 rxdw0 = le32_to_cpu(val);
982 pci_dma_read(&s->dev, cplus_rx_ring_desc+4, &val, 4);
983 rxdw1 = le32_to_cpu(val);
984 pci_dma_read(&s->dev, cplus_rx_ring_desc+8, &val, 4);
985 rxbufLO = le32_to_cpu(val);
986 pci_dma_read(&s->dev, cplus_rx_ring_desc+12, &val, 4);
987 rxbufHI = le32_to_cpu(val);
988
989 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
990 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
991
992 if (!(rxdw0 & CP_RX_OWN))
993 {
994 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
995 descriptor);
996
997 s->IntrStatus |= RxOverflow;
998 ++s->RxMissed;
999
1000 /* update tally counter */
1001 ++s->tally_counters.RxERR;
1002 ++s->tally_counters.MissPkt;
1003
1004 rtl8139_update_irq(s);
1005 return size_;
1006 }
1007
1008 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1009
1010 /* write VLAN info to descriptor variables. */
1011 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1012 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1013 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1014 size -= VLAN_HLEN;
1015 /* if too small buffer, use the tailroom added duing expansion */
1016 if (size < MIN_BUF_SIZE) {
1017 size = MIN_BUF_SIZE;
1018 }
1019
1020 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1021 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1022 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1023 &dot1q_buf[ETHER_TYPE_LEN]);
1024
1025 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1026 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
1027 } else {
1028 /* reset VLAN tag flag */
1029 rxdw1 &= ~CP_RX_TAVA;
1030 }
1031
1032 /* TODO: scatter the packet over available receive ring descriptors space */
1033
1034 if (size+4 > rx_space)
1035 {
1036 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1037 descriptor, rx_space, size);
1038
1039 s->IntrStatus |= RxOverflow;
1040 ++s->RxMissed;
1041
1042 /* update tally counter */
1043 ++s->tally_counters.RxERR;
1044 ++s->tally_counters.MissPkt;
1045
1046 rtl8139_update_irq(s);
1047 return size_;
1048 }
1049
1050 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1051
1052 /* receive/copy to target memory */
1053 if (dot1q_buf) {
1054 pci_dma_write(&s->dev, rx_addr, buf, 2 * ETHER_ADDR_LEN);
1055 pci_dma_write(&s->dev, rx_addr + 2 * ETHER_ADDR_LEN,
1056 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1057 size - 2 * ETHER_ADDR_LEN);
1058 } else {
1059 pci_dma_write(&s->dev, rx_addr, buf, size);
1060 }
1061
1062 if (s->CpCmd & CPlusRxChkSum)
1063 {
1064 /* do some packet checksumming */
1065 }
1066
1067 /* write checksum */
1068 val = cpu_to_le32(crc32(0, buf, size_));
1069 pci_dma_write(&s->dev, rx_addr+size, (uint8_t *)&val, 4);
1070
1071 /* first segment of received packet flag */
1072 #define CP_RX_STATUS_FS (1<<29)
1073 /* last segment of received packet flag */
1074 #define CP_RX_STATUS_LS (1<<28)
1075 /* multicast packet flag */
1076 #define CP_RX_STATUS_MAR (1<<26)
1077 /* physical-matching packet flag */
1078 #define CP_RX_STATUS_PAM (1<<25)
1079 /* broadcast packet flag */
1080 #define CP_RX_STATUS_BAR (1<<24)
1081 /* runt packet flag */
1082 #define CP_RX_STATUS_RUNT (1<<19)
1083 /* crc error flag */
1084 #define CP_RX_STATUS_CRC (1<<18)
1085 /* IP checksum error flag */
1086 #define CP_RX_STATUS_IPF (1<<15)
1087 /* UDP checksum error flag */
1088 #define CP_RX_STATUS_UDPF (1<<14)
1089 /* TCP checksum error flag */
1090 #define CP_RX_STATUS_TCPF (1<<13)
1091
1092 /* transfer ownership to target */
1093 rxdw0 &= ~CP_RX_OWN;
1094
1095 /* set first segment bit */
1096 rxdw0 |= CP_RX_STATUS_FS;
1097
1098 /* set last segment bit */
1099 rxdw0 |= CP_RX_STATUS_LS;
1100
1101 /* set received packet type flags */
1102 if (packet_header & RxBroadcast)
1103 rxdw0 |= CP_RX_STATUS_BAR;
1104 if (packet_header & RxMulticast)
1105 rxdw0 |= CP_RX_STATUS_MAR;
1106 if (packet_header & RxPhysical)
1107 rxdw0 |= CP_RX_STATUS_PAM;
1108
1109 /* set received size */
1110 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1111 rxdw0 |= (size+4);
1112
1113 /* update ring data */
1114 val = cpu_to_le32(rxdw0);
1115 pci_dma_write(&s->dev, cplus_rx_ring_desc, (uint8_t *)&val, 4);
1116 val = cpu_to_le32(rxdw1);
1117 pci_dma_write(&s->dev, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1118
1119 /* update tally counter */
1120 ++s->tally_counters.RxOk;
1121
1122 /* seek to next Rx descriptor */
1123 if (rxdw0 & CP_RX_EOR)
1124 {
1125 s->currCPlusRxDesc = 0;
1126 }
1127 else
1128 {
1129 ++s->currCPlusRxDesc;
1130 }
1131
1132 DPRINTF("done C+ Rx mode ----------------\n");
1133
1134 }
1135 else
1136 {
1137 DPRINTF("in ring Rx mode ================\n");
1138
1139 /* begin ring receiver mode */
1140 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1141
1142 /* if receiver buffer is empty then avail == 0 */
1143
1144 if (avail != 0 && size + 8 >= avail)
1145 {
1146 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1147 "read 0x%04x === available 0x%04x need 0x%04x\n",
1148 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
1149
1150 s->IntrStatus |= RxOverflow;
1151 ++s->RxMissed;
1152 rtl8139_update_irq(s);
1153 return size_;
1154 }
1155
1156 packet_header |= RxStatusOK;
1157
1158 packet_header |= (((size+4) << 16) & 0xffff0000);
1159
1160 /* write header */
1161 uint32_t val = cpu_to_le32(packet_header);
1162
1163 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1164
1165 rtl8139_write_buffer(s, buf, size);
1166
1167 /* write checksum */
1168 val = cpu_to_le32(crc32(0, buf, size));
1169 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1170
1171 /* correct buffer write pointer */
1172 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1173
1174 /* now we can signal we have received something */
1175
1176 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1177 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
1178 }
1179
1180 s->IntrStatus |= RxOK;
1181
1182 if (do_interrupt)
1183 {
1184 rtl8139_update_irq(s);
1185 }
1186
1187 return size_;
1188 }
1189
1190 static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
1191 {
1192 return rtl8139_do_receive(nc, buf, size, 1);
1193 }
1194
1195 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1196 {
1197 s->RxBufferSize = bufferSize;
1198 s->RxBufPtr = 0;
1199 s->RxBufAddr = 0;
1200 }
1201
1202 static void rtl8139_reset(DeviceState *d)
1203 {
1204 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
1205 int i;
1206
1207 /* restore MAC address */
1208 memcpy(s->phys, s->conf.macaddr.a, 6);
1209
1210 /* reset interrupt mask */
1211 s->IntrStatus = 0;
1212 s->IntrMask = 0;
1213
1214 rtl8139_update_irq(s);
1215
1216 /* mark all status registers as owned by host */
1217 for (i = 0; i < 4; ++i)
1218 {
1219 s->TxStatus[i] = TxHostOwns;
1220 }
1221
1222 s->currTxDesc = 0;
1223 s->currCPlusRxDesc = 0;
1224 s->currCPlusTxDesc = 0;
1225
1226 s->RxRingAddrLO = 0;
1227 s->RxRingAddrHI = 0;
1228
1229 s->RxBuf = 0;
1230
1231 rtl8139_reset_rxring(s, 8192);
1232
1233 /* ACK the reset */
1234 s->TxConfig = 0;
1235
1236 #if 0
1237 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1238 s->clock_enabled = 0;
1239 #else
1240 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1241 s->clock_enabled = 1;
1242 #endif
1243
1244 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1245
1246 /* set initial state data */
1247 s->Config0 = 0x0; /* No boot ROM */
1248 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1249 s->Config3 = 0x1; /* fast back-to-back compatible */
1250 s->Config5 = 0x0;
1251
1252 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1253
1254 s->CpCmd = 0x0; /* reset C+ mode */
1255 s->cplus_enabled = 0;
1256
1257
1258 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1259 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1260 s->BasicModeCtrl = 0x1000; // autonegotiation
1261
1262 s->BasicModeStatus = 0x7809;
1263 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1264 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1265 s->BasicModeStatus |= 0x0004; /* link is up */
1266
1267 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1268 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1269 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1270
1271 /* also reset timer and disable timer interrupt */
1272 s->TCTR = 0;
1273 s->TimerInt = 0;
1274 s->TCTR_base = 0;
1275
1276 /* reset tally counters */
1277 RTL8139TallyCounters_clear(&s->tally_counters);
1278 }
1279
1280 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1281 {
1282 counters->TxOk = 0;
1283 counters->RxOk = 0;
1284 counters->TxERR = 0;
1285 counters->RxERR = 0;
1286 counters->MissPkt = 0;
1287 counters->FAE = 0;
1288 counters->Tx1Col = 0;
1289 counters->TxMCol = 0;
1290 counters->RxOkPhy = 0;
1291 counters->RxOkBrd = 0;
1292 counters->RxOkMul = 0;
1293 counters->TxAbt = 0;
1294 counters->TxUndrn = 0;
1295 }
1296
1297 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
1298 {
1299 RTL8139TallyCounters *tally_counters = &s->tally_counters;
1300 uint16_t val16;
1301 uint32_t val32;
1302 uint64_t val64;
1303
1304 val64 = cpu_to_le64(tally_counters->TxOk);
1305 pci_dma_write(&s->dev, tc_addr + 0, (uint8_t *)&val64, 8);
1306
1307 val64 = cpu_to_le64(tally_counters->RxOk);
1308 pci_dma_write(&s->dev, tc_addr + 8, (uint8_t *)&val64, 8);
1309
1310 val64 = cpu_to_le64(tally_counters->TxERR);
1311 pci_dma_write(&s->dev, tc_addr + 16, (uint8_t *)&val64, 8);
1312
1313 val32 = cpu_to_le32(tally_counters->RxERR);
1314 pci_dma_write(&s->dev, tc_addr + 24, (uint8_t *)&val32, 4);
1315
1316 val16 = cpu_to_le16(tally_counters->MissPkt);
1317 pci_dma_write(&s->dev, tc_addr + 28, (uint8_t *)&val16, 2);
1318
1319 val16 = cpu_to_le16(tally_counters->FAE);
1320 pci_dma_write(&s->dev, tc_addr + 30, (uint8_t *)&val16, 2);
1321
1322 val32 = cpu_to_le32(tally_counters->Tx1Col);
1323 pci_dma_write(&s->dev, tc_addr + 32, (uint8_t *)&val32, 4);
1324
1325 val32 = cpu_to_le32(tally_counters->TxMCol);
1326 pci_dma_write(&s->dev, tc_addr + 36, (uint8_t *)&val32, 4);
1327
1328 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1329 pci_dma_write(&s->dev, tc_addr + 40, (uint8_t *)&val64, 8);
1330
1331 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1332 pci_dma_write(&s->dev, tc_addr + 48, (uint8_t *)&val64, 8);
1333
1334 val32 = cpu_to_le32(tally_counters->RxOkMul);
1335 pci_dma_write(&s->dev, tc_addr + 56, (uint8_t *)&val32, 4);
1336
1337 val16 = cpu_to_le16(tally_counters->TxAbt);
1338 pci_dma_write(&s->dev, tc_addr + 60, (uint8_t *)&val16, 2);
1339
1340 val16 = cpu_to_le16(tally_counters->TxUndrn);
1341 pci_dma_write(&s->dev, tc_addr + 62, (uint8_t *)&val16, 2);
1342 }
1343
1344 /* Loads values of tally counters from VM state file */
1345
1346 static const VMStateDescription vmstate_tally_counters = {
1347 .name = "tally_counters",
1348 .version_id = 1,
1349 .minimum_version_id = 1,
1350 .minimum_version_id_old = 1,
1351 .fields = (VMStateField []) {
1352 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1353 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1354 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1355 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1356 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1357 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1358 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1359 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1360 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1361 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1362 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1363 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1364 VMSTATE_END_OF_LIST()
1365 }
1366 };
1367
1368 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1369 {
1370 val &= 0xff;
1371
1372 DPRINTF("ChipCmd write val=0x%08x\n", val);
1373
1374 if (val & CmdReset)
1375 {
1376 DPRINTF("ChipCmd reset\n");
1377 rtl8139_reset(&s->dev.qdev);
1378 }
1379 if (val & CmdRxEnb)
1380 {
1381 DPRINTF("ChipCmd enable receiver\n");
1382
1383 s->currCPlusRxDesc = 0;
1384 }
1385 if (val & CmdTxEnb)
1386 {
1387 DPRINTF("ChipCmd enable transmitter\n");
1388
1389 s->currCPlusTxDesc = 0;
1390 }
1391
1392 /* mask unwritable bits */
1393 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1394
1395 /* Deassert reset pin before next read */
1396 val &= ~CmdReset;
1397
1398 s->bChipCmdState = val;
1399 }
1400
1401 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1402 {
1403 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1404
1405 if (unread != 0)
1406 {
1407 DPRINTF("receiver buffer data available 0x%04x\n", unread);
1408 return 0;
1409 }
1410
1411 DPRINTF("receiver buffer is empty\n");
1412
1413 return 1;
1414 }
1415
1416 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1417 {
1418 uint32_t ret = s->bChipCmdState;
1419
1420 if (rtl8139_RxBufferEmpty(s))
1421 ret |= RxBufEmpty;
1422
1423 DPRINTF("ChipCmd read val=0x%04x\n", ret);
1424
1425 return ret;
1426 }
1427
1428 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1429 {
1430 val &= 0xffff;
1431
1432 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
1433
1434 s->cplus_enabled = 1;
1435
1436 /* mask unwritable bits */
1437 val = SET_MASKED(val, 0xff84, s->CpCmd);
1438
1439 s->CpCmd = val;
1440 }
1441
1442 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1443 {
1444 uint32_t ret = s->CpCmd;
1445
1446 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
1447
1448 return ret;
1449 }
1450
1451 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1452 {
1453 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
1454 }
1455
1456 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1457 {
1458 uint32_t ret = 0;
1459
1460 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
1461
1462 return ret;
1463 }
1464
1465 static int rtl8139_config_writable(RTL8139State *s)
1466 {
1467 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
1468 {
1469 return 1;
1470 }
1471
1472 DPRINTF("Configuration registers are write-protected\n");
1473
1474 return 0;
1475 }
1476
1477 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1478 {
1479 val &= 0xffff;
1480
1481 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
1482
1483 /* mask unwritable bits */
1484 uint32_t mask = 0x4cff;
1485
1486 if (1 || !rtl8139_config_writable(s))
1487 {
1488 /* Speed setting and autonegotiation enable bits are read-only */
1489 mask |= 0x3000;
1490 /* Duplex mode setting is read-only */
1491 mask |= 0x0100;
1492 }
1493
1494 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1495
1496 s->BasicModeCtrl = val;
1497 }
1498
1499 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1500 {
1501 uint32_t ret = s->BasicModeCtrl;
1502
1503 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
1504
1505 return ret;
1506 }
1507
1508 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1509 {
1510 val &= 0xffff;
1511
1512 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
1513
1514 /* mask unwritable bits */
1515 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1516
1517 s->BasicModeStatus = val;
1518 }
1519
1520 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1521 {
1522 uint32_t ret = s->BasicModeStatus;
1523
1524 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
1525
1526 return ret;
1527 }
1528
1529 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1530 {
1531 val &= 0xff;
1532
1533 DPRINTF("Cfg9346 write val=0x%02x\n", val);
1534
1535 /* mask unwritable bits */
1536 val = SET_MASKED(val, 0x31, s->Cfg9346);
1537
1538 uint32_t opmode = val & 0xc0;
1539 uint32_t eeprom_val = val & 0xf;
1540
1541 if (opmode == 0x80) {
1542 /* eeprom access */
1543 int eecs = (eeprom_val & 0x08)?1:0;
1544 int eesk = (eeprom_val & 0x04)?1:0;
1545 int eedi = (eeprom_val & 0x02)?1:0;
1546 prom9346_set_wire(s, eecs, eesk, eedi);
1547 } else if (opmode == 0x40) {
1548 /* Reset. */
1549 val = 0;
1550 rtl8139_reset(&s->dev.qdev);
1551 }
1552
1553 s->Cfg9346 = val;
1554 }
1555
1556 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1557 {
1558 uint32_t ret = s->Cfg9346;
1559
1560 uint32_t opmode = ret & 0xc0;
1561
1562 if (opmode == 0x80)
1563 {
1564 /* eeprom access */
1565 int eedo = prom9346_get_wire(s);
1566 if (eedo)
1567 {
1568 ret |= 0x01;
1569 }
1570 else
1571 {
1572 ret &= ~0x01;
1573 }
1574 }
1575
1576 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
1577
1578 return ret;
1579 }
1580
1581 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1582 {
1583 val &= 0xff;
1584
1585 DPRINTF("Config0 write val=0x%02x\n", val);
1586
1587 if (!rtl8139_config_writable(s)) {
1588 return;
1589 }
1590
1591 /* mask unwritable bits */
1592 val = SET_MASKED(val, 0xf8, s->Config0);
1593
1594 s->Config0 = val;
1595 }
1596
1597 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1598 {
1599 uint32_t ret = s->Config0;
1600
1601 DPRINTF("Config0 read val=0x%02x\n", ret);
1602
1603 return ret;
1604 }
1605
1606 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1607 {
1608 val &= 0xff;
1609
1610 DPRINTF("Config1 write val=0x%02x\n", val);
1611
1612 if (!rtl8139_config_writable(s)) {
1613 return;
1614 }
1615
1616 /* mask unwritable bits */
1617 val = SET_MASKED(val, 0xC, s->Config1);
1618
1619 s->Config1 = val;
1620 }
1621
1622 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1623 {
1624 uint32_t ret = s->Config1;
1625
1626 DPRINTF("Config1 read val=0x%02x\n", ret);
1627
1628 return ret;
1629 }
1630
1631 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1632 {
1633 val &= 0xff;
1634
1635 DPRINTF("Config3 write val=0x%02x\n", val);
1636
1637 if (!rtl8139_config_writable(s)) {
1638 return;
1639 }
1640
1641 /* mask unwritable bits */
1642 val = SET_MASKED(val, 0x8F, s->Config3);
1643
1644 s->Config3 = val;
1645 }
1646
1647 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1648 {
1649 uint32_t ret = s->Config3;
1650
1651 DPRINTF("Config3 read val=0x%02x\n", ret);
1652
1653 return ret;
1654 }
1655
1656 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1657 {
1658 val &= 0xff;
1659
1660 DPRINTF("Config4 write val=0x%02x\n", val);
1661
1662 if (!rtl8139_config_writable(s)) {
1663 return;
1664 }
1665
1666 /* mask unwritable bits */
1667 val = SET_MASKED(val, 0x0a, s->Config4);
1668
1669 s->Config4 = val;
1670 }
1671
1672 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1673 {
1674 uint32_t ret = s->Config4;
1675
1676 DPRINTF("Config4 read val=0x%02x\n", ret);
1677
1678 return ret;
1679 }
1680
1681 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1682 {
1683 val &= 0xff;
1684
1685 DPRINTF("Config5 write val=0x%02x\n", val);
1686
1687 /* mask unwritable bits */
1688 val = SET_MASKED(val, 0x80, s->Config5);
1689
1690 s->Config5 = val;
1691 }
1692
1693 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1694 {
1695 uint32_t ret = s->Config5;
1696
1697 DPRINTF("Config5 read val=0x%02x\n", ret);
1698
1699 return ret;
1700 }
1701
1702 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1703 {
1704 if (!rtl8139_transmitter_enabled(s))
1705 {
1706 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
1707 return;
1708 }
1709
1710 DPRINTF("TxConfig write val=0x%08x\n", val);
1711
1712 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1713
1714 s->TxConfig = val;
1715 }
1716
1717 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1718 {
1719 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
1720
1721 uint32_t tc = s->TxConfig;
1722 tc &= 0xFFFFFF00;
1723 tc |= (val & 0x000000FF);
1724 rtl8139_TxConfig_write(s, tc);
1725 }
1726
1727 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1728 {
1729 uint32_t ret = s->TxConfig;
1730
1731 DPRINTF("TxConfig read val=0x%04x\n", ret);
1732
1733 return ret;
1734 }
1735
1736 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1737 {
1738 DPRINTF("RxConfig write val=0x%08x\n", val);
1739
1740 /* mask unwritable bits */
1741 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1742
1743 s->RxConfig = val;
1744
1745 /* reset buffer size and read/write pointers */
1746 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1747
1748 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
1749 }
1750
1751 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1752 {
1753 uint32_t ret = s->RxConfig;
1754
1755 DPRINTF("RxConfig read val=0x%08x\n", ret);
1756
1757 return ret;
1758 }
1759
1760 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1761 int do_interrupt, const uint8_t *dot1q_buf)
1762 {
1763 struct iovec *iov = NULL;
1764
1765 if (!size)
1766 {
1767 DPRINTF("+++ empty ethernet frame\n");
1768 return;
1769 }
1770
1771 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1772 iov = (struct iovec[3]) {
1773 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1774 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1775 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1776 .iov_len = size - ETHER_ADDR_LEN * 2 },
1777 };
1778 }
1779
1780 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1781 {
1782 size_t buf2_size;
1783 uint8_t *buf2;
1784
1785 if (iov) {
1786 buf2_size = iov_size(iov, 3);
1787 buf2 = g_malloc(buf2_size);
1788 iov_to_buf(iov, 3, 0, buf2, buf2_size);
1789 buf = buf2;
1790 }
1791
1792 DPRINTF("+++ transmit loopback mode\n");
1793 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
1794
1795 if (iov) {
1796 g_free(buf2);
1797 }
1798 }
1799 else
1800 {
1801 if (iov) {
1802 qemu_sendv_packet(&s->nic->nc, iov, 3);
1803 } else {
1804 qemu_send_packet(&s->nic->nc, buf, size);
1805 }
1806 }
1807 }
1808
1809 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1810 {
1811 if (!rtl8139_transmitter_enabled(s))
1812 {
1813 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1814 "disabled\n", descriptor);
1815 return 0;
1816 }
1817
1818 if (s->TxStatus[descriptor] & TxHostOwns)
1819 {
1820 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1821 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
1822 return 0;
1823 }
1824
1825 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
1826
1827 int txsize = s->TxStatus[descriptor] & 0x1fff;
1828 uint8_t txbuffer[0x2000];
1829
1830 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1831 txsize, s->TxAddr[descriptor]);
1832
1833 pci_dma_read(&s->dev, s->TxAddr[descriptor], txbuffer, txsize);
1834
1835 /* Mark descriptor as transferred */
1836 s->TxStatus[descriptor] |= TxHostOwns;
1837 s->TxStatus[descriptor] |= TxStatOK;
1838
1839 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
1840
1841 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1842 descriptor);
1843
1844 /* update interrupt */
1845 s->IntrStatus |= TxOK;
1846 rtl8139_update_irq(s);
1847
1848 return 1;
1849 }
1850
1851 /* structures and macros for task offloading */
1852 typedef struct ip_header
1853 {
1854 uint8_t ip_ver_len; /* version and header length */
1855 uint8_t ip_tos; /* type of service */
1856 uint16_t ip_len; /* total length */
1857 uint16_t ip_id; /* identification */
1858 uint16_t ip_off; /* fragment offset field */
1859 uint8_t ip_ttl; /* time to live */
1860 uint8_t ip_p; /* protocol */
1861 uint16_t ip_sum; /* checksum */
1862 uint32_t ip_src,ip_dst; /* source and dest address */
1863 } ip_header;
1864
1865 #define IP_HEADER_VERSION_4 4
1866 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1867 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1868
1869 typedef struct tcp_header
1870 {
1871 uint16_t th_sport; /* source port */
1872 uint16_t th_dport; /* destination port */
1873 uint32_t th_seq; /* sequence number */
1874 uint32_t th_ack; /* acknowledgement number */
1875 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1876 uint16_t th_win; /* window */
1877 uint16_t th_sum; /* checksum */
1878 uint16_t th_urp; /* urgent pointer */
1879 } tcp_header;
1880
1881 typedef struct udp_header
1882 {
1883 uint16_t uh_sport; /* source port */
1884 uint16_t uh_dport; /* destination port */
1885 uint16_t uh_ulen; /* udp length */
1886 uint16_t uh_sum; /* udp checksum */
1887 } udp_header;
1888
1889 typedef struct ip_pseudo_header
1890 {
1891 uint32_t ip_src;
1892 uint32_t ip_dst;
1893 uint8_t zeros;
1894 uint8_t ip_proto;
1895 uint16_t ip_payload;
1896 } ip_pseudo_header;
1897
1898 #define IP_PROTO_TCP 6
1899 #define IP_PROTO_UDP 17
1900
1901 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1902 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1903 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1904
1905 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1906
1907 #define TCP_FLAG_FIN 0x01
1908 #define TCP_FLAG_PUSH 0x08
1909
1910 /* produces ones' complement sum of data */
1911 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1912 {
1913 uint32_t result = 0;
1914
1915 for (; len > 1; data+=2, len-=2)
1916 {
1917 result += *(uint16_t*)data;
1918 }
1919
1920 /* add the remainder byte */
1921 if (len)
1922 {
1923 uint8_t odd[2] = {*data, 0};
1924 result += *(uint16_t*)odd;
1925 }
1926
1927 while (result>>16)
1928 result = (result & 0xffff) + (result >> 16);
1929
1930 return result;
1931 }
1932
1933 static uint16_t ip_checksum(void *data, size_t len)
1934 {
1935 return ~ones_complement_sum((uint8_t*)data, len);
1936 }
1937
1938 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1939 {
1940 if (!rtl8139_transmitter_enabled(s))
1941 {
1942 DPRINTF("+++ C+ mode: transmitter disabled\n");
1943 return 0;
1944 }
1945
1946 if (!rtl8139_cp_transmitter_enabled(s))
1947 {
1948 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
1949 return 0 ;
1950 }
1951
1952 int descriptor = s->currCPlusTxDesc;
1953
1954 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1955
1956 /* Normal priority ring */
1957 cplus_tx_ring_desc += 16 * descriptor;
1958
1959 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
1960 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
1961 s->TxAddr[0], cplus_tx_ring_desc);
1962
1963 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1964
1965 pci_dma_read(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
1966 txdw0 = le32_to_cpu(val);
1967 pci_dma_read(&s->dev, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1968 txdw1 = le32_to_cpu(val);
1969 pci_dma_read(&s->dev, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1970 txbufLO = le32_to_cpu(val);
1971 pci_dma_read(&s->dev, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1972 txbufHI = le32_to_cpu(val);
1973
1974 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1975 txdw0, txdw1, txbufLO, txbufHI);
1976
1977 /* w0 ownership flag */
1978 #define CP_TX_OWN (1<<31)
1979 /* w0 end of ring flag */
1980 #define CP_TX_EOR (1<<30)
1981 /* first segment of received packet flag */
1982 #define CP_TX_FS (1<<29)
1983 /* last segment of received packet flag */
1984 #define CP_TX_LS (1<<28)
1985 /* large send packet flag */
1986 #define CP_TX_LGSEN (1<<27)
1987 /* large send MSS mask, bits 16...25 */
1988 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1989
1990 /* IP checksum offload flag */
1991 #define CP_TX_IPCS (1<<18)
1992 /* UDP checksum offload flag */
1993 #define CP_TX_UDPCS (1<<17)
1994 /* TCP checksum offload flag */
1995 #define CP_TX_TCPCS (1<<16)
1996
1997 /* w0 bits 0...15 : buffer size */
1998 #define CP_TX_BUFFER_SIZE (1<<16)
1999 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
2000 /* w1 add tag flag */
2001 #define CP_TX_TAGC (1<<17)
2002 /* w1 bits 0...15 : VLAN tag (big endian) */
2003 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
2004 /* w2 low 32bit of Rx buffer ptr */
2005 /* w3 high 32bit of Rx buffer ptr */
2006
2007 /* set after transmission */
2008 /* FIFO underrun flag */
2009 #define CP_TX_STATUS_UNF (1<<25)
2010 /* transmit error summary flag, valid if set any of three below */
2011 #define CP_TX_STATUS_TES (1<<23)
2012 /* out-of-window collision flag */
2013 #define CP_TX_STATUS_OWC (1<<22)
2014 /* link failure flag */
2015 #define CP_TX_STATUS_LNKF (1<<21)
2016 /* excessive collisions flag */
2017 #define CP_TX_STATUS_EXC (1<<20)
2018
2019 if (!(txdw0 & CP_TX_OWN))
2020 {
2021 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
2022 return 0 ;
2023 }
2024
2025 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
2026
2027 if (txdw0 & CP_TX_FS)
2028 {
2029 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
2030 "descriptor\n", descriptor);
2031
2032 /* reset internal buffer offset */
2033 s->cplus_txbuffer_offset = 0;
2034 }
2035
2036 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
2037 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
2038
2039 /* make sure we have enough space to assemble the packet */
2040 if (!s->cplus_txbuffer)
2041 {
2042 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2043 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
2044 s->cplus_txbuffer_offset = 0;
2045
2046 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2047 s->cplus_txbuffer_len);
2048 }
2049
2050 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2051 {
2052 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
2053 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
2054 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
2055 "length to %d\n", txsize);
2056 }
2057
2058 if (!s->cplus_txbuffer)
2059 {
2060 /* out of memory */
2061
2062 DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
2063 s->cplus_txbuffer_len);
2064
2065 /* update tally counter */
2066 ++s->tally_counters.TxERR;
2067 ++s->tally_counters.TxAbt;
2068
2069 return 0;
2070 }
2071
2072 /* append more data to the packet */
2073
2074 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
2075 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
2076 s->cplus_txbuffer_offset);
2077
2078 pci_dma_read(&s->dev, tx_addr,
2079 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2080 s->cplus_txbuffer_offset += txsize;
2081
2082 /* seek to next Rx descriptor */
2083 if (txdw0 & CP_TX_EOR)
2084 {
2085 s->currCPlusTxDesc = 0;
2086 }
2087 else
2088 {
2089 ++s->currCPlusTxDesc;
2090 if (s->currCPlusTxDesc >= 64)
2091 s->currCPlusTxDesc = 0;
2092 }
2093
2094 /* transfer ownership to target */
2095 txdw0 &= ~CP_RX_OWN;
2096
2097 /* reset error indicator bits */
2098 txdw0 &= ~CP_TX_STATUS_UNF;
2099 txdw0 &= ~CP_TX_STATUS_TES;
2100 txdw0 &= ~CP_TX_STATUS_OWC;
2101 txdw0 &= ~CP_TX_STATUS_LNKF;
2102 txdw0 &= ~CP_TX_STATUS_EXC;
2103
2104 /* update ring data */
2105 val = cpu_to_le32(txdw0);
2106 pci_dma_write(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
2107
2108 /* Now decide if descriptor being processed is holding the last segment of packet */
2109 if (txdw0 & CP_TX_LS)
2110 {
2111 uint8_t dot1q_buffer_space[VLAN_HLEN];
2112 uint16_t *dot1q_buffer;
2113
2114 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2115 descriptor);
2116
2117 /* can transfer fully assembled packet */
2118
2119 uint8_t *saved_buffer = s->cplus_txbuffer;
2120 int saved_size = s->cplus_txbuffer_offset;
2121 int saved_buffer_len = s->cplus_txbuffer_len;
2122
2123 /* create vlan tag */
2124 if (txdw1 & CP_TX_TAGC) {
2125 /* the vlan tag is in BE byte order in the descriptor
2126 * BE + le_to_cpu() + ~swap()~ = cpu */
2127 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2128 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
2129
2130 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2131 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2132 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2133 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2134 } else {
2135 dot1q_buffer = NULL;
2136 }
2137
2138 /* reset the card space to protect from recursive call */
2139 s->cplus_txbuffer = NULL;
2140 s->cplus_txbuffer_offset = 0;
2141 s->cplus_txbuffer_len = 0;
2142
2143 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2144 {
2145 DPRINTF("+++ C+ mode offloaded task checksum\n");
2146
2147 /* ip packet header */
2148 ip_header *ip = NULL;
2149 int hlen = 0;
2150 uint8_t ip_protocol = 0;
2151 uint16_t ip_data_len = 0;
2152
2153 uint8_t *eth_payload_data = NULL;
2154 size_t eth_payload_len = 0;
2155
2156 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2157 if (proto == ETH_P_IP)
2158 {
2159 DPRINTF("+++ C+ mode has IP packet\n");
2160
2161 /* not aligned */
2162 eth_payload_data = saved_buffer + ETH_HLEN;
2163 eth_payload_len = saved_size - ETH_HLEN;
2164
2165 ip = (ip_header*)eth_payload_data;
2166
2167 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2168 DPRINTF("+++ C+ mode packet has bad IP version %d "
2169 "expected %d\n", IP_HEADER_VERSION(ip),
2170 IP_HEADER_VERSION_4);
2171 ip = NULL;
2172 } else {
2173 hlen = IP_HEADER_LENGTH(ip);
2174 ip_protocol = ip->ip_p;
2175 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
2176 }
2177 }
2178
2179 if (ip)
2180 {
2181 if (txdw0 & CP_TX_IPCS)
2182 {
2183 DPRINTF("+++ C+ mode need IP checksum\n");
2184
2185 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
2186 /* bad packet header len */
2187 /* or packet too short */
2188 }
2189 else
2190 {
2191 ip->ip_sum = 0;
2192 ip->ip_sum = ip_checksum(ip, hlen);
2193 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2194 hlen, ip->ip_sum);
2195 }
2196 }
2197
2198 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2199 {
2200 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2201
2202 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2203 "frame data %d specified MSS=%d\n", ETH_MTU,
2204 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
2205
2206 int tcp_send_offset = 0;
2207 int send_count = 0;
2208
2209 /* maximum IP header length is 60 bytes */
2210 uint8_t saved_ip_header[60];
2211
2212 /* save IP header template; data area is used in tcp checksum calculation */
2213 memcpy(saved_ip_header, eth_payload_data, hlen);
2214
2215 /* a placeholder for checksum calculation routine in tcp case */
2216 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2217 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2218
2219 /* pointer to TCP header */
2220 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2221
2222 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2223
2224 /* ETH_MTU = ip header len + tcp header len + payload */
2225 int tcp_data_len = ip_data_len - tcp_hlen;
2226 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2227
2228 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2229 "data len %d TCP chunk size %d\n", ip_data_len,
2230 tcp_hlen, tcp_data_len, tcp_chunk_size);
2231
2232 /* note the cycle below overwrites IP header data,
2233 but restores it from saved_ip_header before sending packet */
2234
2235 int is_last_frame = 0;
2236
2237 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2238 {
2239 uint16_t chunk_size = tcp_chunk_size;
2240
2241 /* check if this is the last frame */
2242 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2243 {
2244 is_last_frame = 1;
2245 chunk_size = tcp_data_len - tcp_send_offset;
2246 }
2247
2248 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2249 be32_to_cpu(p_tcp_hdr->th_seq));
2250
2251 /* add 4 TCP pseudoheader fields */
2252 /* copy IP source and destination fields */
2253 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2254
2255 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2256 "packet with %d bytes data\n", tcp_hlen +
2257 chunk_size);
2258
2259 if (tcp_send_offset)
2260 {
2261 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2262 }
2263
2264 /* keep PUSH and FIN flags only for the last frame */
2265 if (!is_last_frame)
2266 {
2267 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2268 }
2269
2270 /* recalculate TCP checksum */
2271 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2272 p_tcpip_hdr->zeros = 0;
2273 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2274 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2275
2276 p_tcp_hdr->th_sum = 0;
2277
2278 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2279 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2280 tcp_checksum);
2281
2282 p_tcp_hdr->th_sum = tcp_checksum;
2283
2284 /* restore IP header */
2285 memcpy(eth_payload_data, saved_ip_header, hlen);
2286
2287 /* set IP data length and recalculate IP checksum */
2288 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2289
2290 /* increment IP id for subsequent frames */
2291 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2292
2293 ip->ip_sum = 0;
2294 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2295 DPRINTF("+++ C+ mode TSO IP header len=%d "
2296 "checksum=%04x\n", hlen, ip->ip_sum);
2297
2298 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2299 DPRINTF("+++ C+ mode TSO transferring packet size "
2300 "%d\n", tso_send_size);
2301 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2302 0, (uint8_t *) dot1q_buffer);
2303
2304 /* add transferred count to TCP sequence number */
2305 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2306 ++send_count;
2307 }
2308
2309 /* Stop sending this frame */
2310 saved_size = 0;
2311 }
2312 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2313 {
2314 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
2315
2316 /* maximum IP header length is 60 bytes */
2317 uint8_t saved_ip_header[60];
2318 memcpy(saved_ip_header, eth_payload_data, hlen);
2319
2320 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2321 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2322
2323 /* add 4 TCP pseudoheader fields */
2324 /* copy IP source and destination fields */
2325 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2326
2327 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2328 {
2329 DPRINTF("+++ C+ mode calculating TCP checksum for "
2330 "packet with %d bytes data\n", ip_data_len);
2331
2332 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2333 p_tcpip_hdr->zeros = 0;
2334 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2335 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2336
2337 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2338
2339 p_tcp_hdr->th_sum = 0;
2340
2341 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2342 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2343 tcp_checksum);
2344
2345 p_tcp_hdr->th_sum = tcp_checksum;
2346 }
2347 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2348 {
2349 DPRINTF("+++ C+ mode calculating UDP checksum for "
2350 "packet with %d bytes data\n", ip_data_len);
2351
2352 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2353 p_udpip_hdr->zeros = 0;
2354 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2355 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2356
2357 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2358
2359 p_udp_hdr->uh_sum = 0;
2360
2361 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2362 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2363 udp_checksum);
2364
2365 p_udp_hdr->uh_sum = udp_checksum;
2366 }
2367
2368 /* restore IP header */
2369 memcpy(eth_payload_data, saved_ip_header, hlen);
2370 }
2371 }
2372 }
2373
2374 /* update tally counter */
2375 ++s->tally_counters.TxOk;
2376
2377 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
2378
2379 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2380 (uint8_t *) dot1q_buffer);
2381
2382 /* restore card space if there was no recursion and reset offset */
2383 if (!s->cplus_txbuffer)
2384 {
2385 s->cplus_txbuffer = saved_buffer;
2386 s->cplus_txbuffer_len = saved_buffer_len;
2387 s->cplus_txbuffer_offset = 0;
2388 }
2389 else
2390 {
2391 g_free(saved_buffer);
2392 }
2393 }
2394 else
2395 {
2396 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
2397 }
2398
2399 return 1;
2400 }
2401
2402 static void rtl8139_cplus_transmit(RTL8139State *s)
2403 {
2404 int txcount = 0;
2405
2406 while (rtl8139_cplus_transmit_one(s))
2407 {
2408 ++txcount;
2409 }
2410
2411 /* Mark transfer completed */
2412 if (!txcount)
2413 {
2414 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2415 s->currCPlusTxDesc);
2416 }
2417 else
2418 {
2419 /* update interrupt status */
2420 s->IntrStatus |= TxOK;
2421 rtl8139_update_irq(s);
2422 }
2423 }
2424
2425 static void rtl8139_transmit(RTL8139State *s)
2426 {
2427 int descriptor = s->currTxDesc, txcount = 0;
2428
2429 /*while*/
2430 if (rtl8139_transmit_one(s, descriptor))
2431 {
2432 ++s->currTxDesc;
2433 s->currTxDesc %= 4;
2434 ++txcount;
2435 }
2436
2437 /* Mark transfer completed */
2438 if (!txcount)
2439 {
2440 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2441 s->currTxDesc);
2442 }
2443 }
2444
2445 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2446 {
2447
2448 int descriptor = txRegOffset/4;
2449
2450 /* handle C+ transmit mode register configuration */
2451
2452 if (s->cplus_enabled)
2453 {
2454 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2455 "descriptor=%d\n", txRegOffset, val, descriptor);
2456
2457 /* handle Dump Tally Counters command */
2458 s->TxStatus[descriptor] = val;
2459
2460 if (descriptor == 0 && (val & 0x8))
2461 {
2462 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2463
2464 /* dump tally counters to specified memory location */
2465 RTL8139TallyCounters_dma_write(s, tc_addr);
2466
2467 /* mark dump completed */
2468 s->TxStatus[0] &= ~0x8;
2469 }
2470
2471 return;
2472 }
2473
2474 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2475 txRegOffset, val, descriptor);
2476
2477 /* mask only reserved bits */
2478 val &= ~0xff00c000; /* these bits are reset on write */
2479 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2480
2481 s->TxStatus[descriptor] = val;
2482
2483 /* attempt to start transmission */
2484 rtl8139_transmit(s);
2485 }
2486
2487 static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
2488 uint32_t base, uint8_t addr,
2489 int size)
2490 {
2491 uint32_t reg = (addr - base) / 4;
2492 uint32_t offset = addr & 0x3;
2493 uint32_t ret = 0;
2494
2495 if (addr & (size - 1)) {
2496 DPRINTF("not implemented read for TxStatus/TxAddr "
2497 "addr=0x%x size=0x%x\n", addr, size);
2498 return ret;
2499 }
2500
2501 switch (size) {
2502 case 1: /* fall through */
2503 case 2: /* fall through */
2504 case 4:
2505 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1);
2506 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
2507 reg, addr, size, ret);
2508 break;
2509 default:
2510 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
2511 break;
2512 }
2513
2514 return ret;
2515 }
2516
2517 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2518 {
2519 uint16_t ret = 0;
2520
2521 /* Simulate TSAD, it is read only anyway */
2522
2523 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2524 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2525 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2526 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2527
2528 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2529 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2530 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2531 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2532
2533 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2534 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2535 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2536 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2537
2538 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2539 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2540 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2541 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2542
2543
2544 DPRINTF("TSAD read val=0x%04x\n", ret);
2545
2546 return ret;
2547 }
2548
2549 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2550 {
2551 uint16_t ret = s->CSCR;
2552
2553 DPRINTF("CSCR read val=0x%04x\n", ret);
2554
2555 return ret;
2556 }
2557
2558 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2559 {
2560 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
2561
2562 s->TxAddr[txAddrOffset/4] = val;
2563 }
2564
2565 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2566 {
2567 uint32_t ret = s->TxAddr[txAddrOffset/4];
2568
2569 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
2570
2571 return ret;
2572 }
2573
2574 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2575 {
2576 DPRINTF("RxBufPtr write val=0x%04x\n", val);
2577
2578 /* this value is off by 16 */
2579 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2580
2581 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2582 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
2583 }
2584
2585 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2586 {
2587 /* this value is off by 16 */
2588 uint32_t ret = s->RxBufPtr - 0x10;
2589
2590 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
2591
2592 return ret;
2593 }
2594
2595 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2596 {
2597 /* this value is NOT off by 16 */
2598 uint32_t ret = s->RxBufAddr;
2599
2600 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
2601
2602 return ret;
2603 }
2604
2605 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2606 {
2607 DPRINTF("RxBuf write val=0x%08x\n", val);
2608
2609 s->RxBuf = val;
2610
2611 /* may need to reset rxring here */
2612 }
2613
2614 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2615 {
2616 uint32_t ret = s->RxBuf;
2617
2618 DPRINTF("RxBuf read val=0x%08x\n", ret);
2619
2620 return ret;
2621 }
2622
2623 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2624 {
2625 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
2626
2627 /* mask unwritable bits */
2628 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2629
2630 s->IntrMask = val;
2631
2632 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2633 rtl8139_update_irq(s);
2634
2635 }
2636
2637 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2638 {
2639 uint32_t ret = s->IntrMask;
2640
2641 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
2642
2643 return ret;
2644 }
2645
2646 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2647 {
2648 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
2649
2650 #if 0
2651
2652 /* writing to ISR has no effect */
2653
2654 return;
2655
2656 #else
2657 uint16_t newStatus = s->IntrStatus & ~val;
2658
2659 /* mask unwritable bits */
2660 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2661
2662 /* writing 1 to interrupt status register bit clears it */
2663 s->IntrStatus = 0;
2664 rtl8139_update_irq(s);
2665
2666 s->IntrStatus = newStatus;
2667 /*
2668 * Computing if we miss an interrupt here is not that correct but
2669 * considered that we should have had already an interrupt
2670 * and probably emulated is slower is better to assume this resetting was
2671 * done before testing on previous rtl8139_update_irq lead to IRQ losing
2672 */
2673 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2674 rtl8139_update_irq(s);
2675
2676 #endif
2677 }
2678
2679 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2680 {
2681 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2682
2683 uint32_t ret = s->IntrStatus;
2684
2685 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
2686
2687 #if 0
2688
2689 /* reading ISR clears all interrupts */
2690 s->IntrStatus = 0;
2691
2692 rtl8139_update_irq(s);
2693
2694 #endif
2695
2696 return ret;
2697 }
2698
2699 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2700 {
2701 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
2702
2703 /* mask unwritable bits */
2704 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2705
2706 s->MultiIntr = val;
2707 }
2708
2709 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2710 {
2711 uint32_t ret = s->MultiIntr;
2712
2713 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
2714
2715 return ret;
2716 }
2717
2718 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2719 {
2720 RTL8139State *s = opaque;
2721
2722 switch (addr)
2723 {
2724 case MAC0 ... MAC0+5:
2725 s->phys[addr - MAC0] = val;
2726 break;
2727 case MAC0+6 ... MAC0+7:
2728 /* reserved */
2729 break;
2730 case MAR0 ... MAR0+7:
2731 s->mult[addr - MAR0] = val;
2732 break;
2733 case ChipCmd:
2734 rtl8139_ChipCmd_write(s, val);
2735 break;
2736 case Cfg9346:
2737 rtl8139_Cfg9346_write(s, val);
2738 break;
2739 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2740 rtl8139_TxConfig_writeb(s, val);
2741 break;
2742 case Config0:
2743 rtl8139_Config0_write(s, val);
2744 break;
2745 case Config1:
2746 rtl8139_Config1_write(s, val);
2747 break;
2748 case Config3:
2749 rtl8139_Config3_write(s, val);
2750 break;
2751 case Config4:
2752 rtl8139_Config4_write(s, val);
2753 break;
2754 case Config5:
2755 rtl8139_Config5_write(s, val);
2756 break;
2757 case MediaStatus:
2758 /* ignore */
2759 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2760 val);
2761 break;
2762
2763 case HltClk:
2764 DPRINTF("HltClk write val=0x%08x\n", val);
2765 if (val == 'R')
2766 {
2767 s->clock_enabled = 1;
2768 }
2769 else if (val == 'H')
2770 {
2771 s->clock_enabled = 0;
2772 }
2773 break;
2774
2775 case TxThresh:
2776 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
2777 s->TxThresh = val;
2778 break;
2779
2780 case TxPoll:
2781 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
2782 if (val & (1 << 7))
2783 {
2784 DPRINTF("C+ TxPoll high priority transmission (not "
2785 "implemented)\n");
2786 //rtl8139_cplus_transmit(s);
2787 }
2788 if (val & (1 << 6))
2789 {
2790 DPRINTF("C+ TxPoll normal priority transmission\n");
2791 rtl8139_cplus_transmit(s);
2792 }
2793
2794 break;
2795
2796 default:
2797 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2798 val);
2799 break;
2800 }
2801 }
2802
2803 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2804 {
2805 RTL8139State *s = opaque;
2806
2807 switch (addr)
2808 {
2809 case IntrMask:
2810 rtl8139_IntrMask_write(s, val);
2811 break;
2812
2813 case IntrStatus:
2814 rtl8139_IntrStatus_write(s, val);
2815 break;
2816
2817 case MultiIntr:
2818 rtl8139_MultiIntr_write(s, val);
2819 break;
2820
2821 case RxBufPtr:
2822 rtl8139_RxBufPtr_write(s, val);
2823 break;
2824
2825 case BasicModeCtrl:
2826 rtl8139_BasicModeCtrl_write(s, val);
2827 break;
2828 case BasicModeStatus:
2829 rtl8139_BasicModeStatus_write(s, val);
2830 break;
2831 case NWayAdvert:
2832 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
2833 s->NWayAdvert = val;
2834 break;
2835 case NWayLPAR:
2836 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
2837 break;
2838 case NWayExpansion:
2839 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
2840 s->NWayExpansion = val;
2841 break;
2842
2843 case CpCmd:
2844 rtl8139_CpCmd_write(s, val);
2845 break;
2846
2847 case IntrMitigate:
2848 rtl8139_IntrMitigate_write(s, val);
2849 break;
2850
2851 default:
2852 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2853 addr, val);
2854
2855 rtl8139_io_writeb(opaque, addr, val & 0xff);
2856 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2857 break;
2858 }
2859 }
2860
2861 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2862 {
2863 int64_t pci_time, next_time;
2864 uint32_t low_pci;
2865
2866 DPRINTF("entered rtl8139_set_next_tctr_time\n");
2867
2868 if (s->TimerExpire && current_time >= s->TimerExpire) {
2869 s->IntrStatus |= PCSTimeout;
2870 rtl8139_update_irq(s);
2871 }
2872
2873 /* Set QEMU timer only if needed that is
2874 * - TimerInt <> 0 (we have a timer)
2875 * - mask = 1 (we want an interrupt timer)
2876 * - irq = 0 (irq is not already active)
2877 * If any of above change we need to compute timer again
2878 * Also we must check if timer is passed without QEMU timer
2879 */
2880 s->TimerExpire = 0;
2881 if (!s->TimerInt) {
2882 return;
2883 }
2884
2885 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2886 get_ticks_per_sec());
2887 low_pci = pci_time & 0xffffffff;
2888 pci_time = pci_time - low_pci + s->TimerInt;
2889 if (low_pci >= s->TimerInt) {
2890 pci_time += 0x100000000LL;
2891 }
2892 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2893 PCI_FREQUENCY);
2894 s->TimerExpire = next_time;
2895
2896 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2897 qemu_mod_timer(s->timer, next_time);
2898 }
2899 }
2900
2901 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2902 {
2903 RTL8139State *s = opaque;
2904
2905 switch (addr)
2906 {
2907 case RxMissed:
2908 DPRINTF("RxMissed clearing on write\n");
2909 s->RxMissed = 0;
2910 break;
2911
2912 case TxConfig:
2913 rtl8139_TxConfig_write(s, val);
2914 break;
2915
2916 case RxConfig:
2917 rtl8139_RxConfig_write(s, val);
2918 break;
2919
2920 case TxStatus0 ... TxStatus0+4*4-1:
2921 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2922 break;
2923
2924 case TxAddr0 ... TxAddr0+4*4-1:
2925 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2926 break;
2927
2928 case RxBuf:
2929 rtl8139_RxBuf_write(s, val);
2930 break;
2931
2932 case RxRingAddrLO:
2933 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
2934 s->RxRingAddrLO = val;
2935 break;
2936
2937 case RxRingAddrHI:
2938 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
2939 s->RxRingAddrHI = val;
2940 break;
2941
2942 case Timer:
2943 DPRINTF("TCTR Timer reset on write\n");
2944 s->TCTR_base = qemu_get_clock_ns(vm_clock);
2945 rtl8139_set_next_tctr_time(s, s->TCTR_base);
2946 break;
2947
2948 case FlashReg:
2949 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
2950 if (s->TimerInt != val) {
2951 s->TimerInt = val;
2952 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2953 }
2954 break;
2955
2956 default:
2957 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2958 addr, val);
2959 rtl8139_io_writeb(opaque, addr, val & 0xff);
2960 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2961 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2962 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2963 break;
2964 }
2965 }
2966
2967 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2968 {
2969 RTL8139State *s = opaque;
2970 int ret;
2971
2972 switch (addr)
2973 {
2974 case MAC0 ... MAC0+5:
2975 ret = s->phys[addr - MAC0];
2976 break;
2977 case MAC0+6 ... MAC0+7:
2978 ret = 0;
2979 break;
2980 case MAR0 ... MAR0+7:
2981 ret = s->mult[addr - MAR0];
2982 break;
2983 case TxStatus0 ... TxStatus0+4*4-1:
2984 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
2985 addr, 1);
2986 break;
2987 case ChipCmd:
2988 ret = rtl8139_ChipCmd_read(s);
2989 break;
2990 case Cfg9346:
2991 ret = rtl8139_Cfg9346_read(s);
2992 break;
2993 case Config0:
2994 ret = rtl8139_Config0_read(s);
2995 break;
2996 case Config1:
2997 ret = rtl8139_Config1_read(s);
2998 break;
2999 case Config3:
3000 ret = rtl8139_Config3_read(s);
3001 break;
3002 case Config4:
3003 ret = rtl8139_Config4_read(s);
3004 break;
3005 case Config5:
3006 ret = rtl8139_Config5_read(s);
3007 break;
3008
3009 case MediaStatus:
3010 ret = 0xd0;
3011 DPRINTF("MediaStatus read 0x%x\n", ret);
3012 break;
3013
3014 case HltClk:
3015 ret = s->clock_enabled;
3016 DPRINTF("HltClk read 0x%x\n", ret);
3017 break;
3018
3019 case PCIRevisionID:
3020 ret = RTL8139_PCI_REVID;
3021 DPRINTF("PCI Revision ID read 0x%x\n", ret);
3022 break;
3023
3024 case TxThresh:
3025 ret = s->TxThresh;
3026 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
3027 break;
3028
3029 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
3030 ret = s->TxConfig >> 24;
3031 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
3032 break;
3033
3034 default:
3035 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
3036 ret = 0;
3037 break;
3038 }
3039
3040 return ret;
3041 }
3042
3043 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3044 {
3045 RTL8139State *s = opaque;
3046 uint32_t ret;
3047
3048 switch (addr)
3049 {
3050 case TxAddr0 ... TxAddr0+4*4-1:
3051 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
3052 break;
3053 case IntrMask:
3054 ret = rtl8139_IntrMask_read(s);
3055 break;
3056
3057 case IntrStatus:
3058 ret = rtl8139_IntrStatus_read(s);
3059 break;
3060
3061 case MultiIntr:
3062 ret = rtl8139_MultiIntr_read(s);
3063 break;
3064
3065 case RxBufPtr:
3066 ret = rtl8139_RxBufPtr_read(s);
3067 break;
3068
3069 case RxBufAddr:
3070 ret = rtl8139_RxBufAddr_read(s);
3071 break;
3072
3073 case BasicModeCtrl:
3074 ret = rtl8139_BasicModeCtrl_read(s);
3075 break;
3076 case BasicModeStatus:
3077 ret = rtl8139_BasicModeStatus_read(s);
3078 break;
3079 case NWayAdvert:
3080 ret = s->NWayAdvert;
3081 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
3082 break;
3083 case NWayLPAR:
3084 ret = s->NWayLPAR;
3085 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
3086 break;
3087 case NWayExpansion:
3088 ret = s->NWayExpansion;
3089 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
3090 break;
3091
3092 case CpCmd:
3093 ret = rtl8139_CpCmd_read(s);
3094 break;
3095
3096 case IntrMitigate:
3097 ret = rtl8139_IntrMitigate_read(s);
3098 break;
3099
3100 case TxSummary:
3101 ret = rtl8139_TSAD_read(s);
3102 break;
3103
3104 case CSCR:
3105 ret = rtl8139_CSCR_read(s);
3106 break;
3107
3108 default:
3109 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
3110
3111 ret = rtl8139_io_readb(opaque, addr);
3112 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3113
3114 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
3115 break;
3116 }
3117
3118 return ret;
3119 }
3120
3121 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3122 {
3123 RTL8139State *s = opaque;
3124 uint32_t ret;
3125
3126 switch (addr)
3127 {
3128 case RxMissed:
3129 ret = s->RxMissed;
3130
3131 DPRINTF("RxMissed read val=0x%08x\n", ret);
3132 break;
3133
3134 case TxConfig:
3135 ret = rtl8139_TxConfig_read(s);
3136 break;
3137
3138 case RxConfig:
3139 ret = rtl8139_RxConfig_read(s);
3140 break;
3141
3142 case TxStatus0 ... TxStatus0+4*4-1:
3143 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
3144 addr, 4);
3145 break;
3146
3147 case TxAddr0 ... TxAddr0+4*4-1:
3148 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3149 break;
3150
3151 case RxBuf:
3152 ret = rtl8139_RxBuf_read(s);
3153 break;
3154
3155 case RxRingAddrLO:
3156 ret = s->RxRingAddrLO;
3157 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
3158 break;
3159
3160 case RxRingAddrHI:
3161 ret = s->RxRingAddrHI;
3162 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
3163 break;
3164
3165 case Timer:
3166 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
3167 PCI_FREQUENCY, get_ticks_per_sec());
3168 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
3169 break;
3170
3171 case FlashReg:
3172 ret = s->TimerInt;
3173 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
3174 break;
3175
3176 default:
3177 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
3178
3179 ret = rtl8139_io_readb(opaque, addr);
3180 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3181 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3182 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3183
3184 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
3185 break;
3186 }
3187
3188 return ret;
3189 }
3190
3191 /* */
3192
3193 static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3194 {
3195 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3196 }
3197
3198 static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3199 {
3200 rtl8139_io_writew(opaque, addr & 0xFF, val);
3201 }
3202
3203 static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3204 {
3205 rtl8139_io_writel(opaque, addr & 0xFF, val);
3206 }
3207
3208 static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3209 {
3210 return rtl8139_io_readb(opaque, addr & 0xFF);
3211 }
3212
3213 static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3214 {
3215 return rtl8139_io_readw(opaque, addr & 0xFF);
3216 }
3217
3218 static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3219 {
3220 return rtl8139_io_readl(opaque, addr & 0xFF);
3221 }
3222
3223 /* */
3224
3225 static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3226 {
3227 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3228 }
3229
3230 static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3231 {
3232 rtl8139_io_writew(opaque, addr & 0xFF, val);
3233 }
3234
3235 static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3236 {
3237 rtl8139_io_writel(opaque, addr & 0xFF, val);
3238 }
3239
3240 static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3241 {
3242 return rtl8139_io_readb(opaque, addr & 0xFF);
3243 }
3244
3245 static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3246 {
3247 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
3248 return val;
3249 }
3250
3251 static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3252 {
3253 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
3254 return val;
3255 }
3256
3257 static int rtl8139_post_load(void *opaque, int version_id)
3258 {
3259 RTL8139State* s = opaque;
3260 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3261 if (version_id < 4) {
3262 s->cplus_enabled = s->CpCmd != 0;
3263 }
3264
3265 return 0;
3266 }
3267
3268 static bool rtl8139_hotplug_ready_needed(void *opaque)
3269 {
3270 return qdev_machine_modified();
3271 }
3272
3273 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3274 .name = "rtl8139/hotplug_ready",
3275 .version_id = 1,
3276 .minimum_version_id = 1,
3277 .minimum_version_id_old = 1,
3278 .fields = (VMStateField []) {
3279 VMSTATE_END_OF_LIST()
3280 }
3281 };
3282
3283 static void rtl8139_pre_save(void *opaque)
3284 {
3285 RTL8139State* s = opaque;
3286 int64_t current_time = qemu_get_clock_ns(vm_clock);
3287
3288 /* set IntrStatus correctly */
3289 rtl8139_set_next_tctr_time(s, current_time);
3290 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3291 get_ticks_per_sec());
3292 s->rtl8139_mmio_io_addr_dummy = 0;
3293 }
3294
3295 static const VMStateDescription vmstate_rtl8139 = {
3296 .name = "rtl8139",
3297 .version_id = 4,
3298 .minimum_version_id = 3,
3299 .minimum_version_id_old = 3,
3300 .post_load = rtl8139_post_load,
3301 .pre_save = rtl8139_pre_save,
3302 .fields = (VMStateField []) {
3303 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3304 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3305 VMSTATE_BUFFER(mult, RTL8139State),
3306 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3307 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3308
3309 VMSTATE_UINT32(RxBuf, RTL8139State),
3310 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3311 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3312 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3313
3314 VMSTATE_UINT16(IntrStatus, RTL8139State),
3315 VMSTATE_UINT16(IntrMask, RTL8139State),
3316
3317 VMSTATE_UINT32(TxConfig, RTL8139State),
3318 VMSTATE_UINT32(RxConfig, RTL8139State),
3319 VMSTATE_UINT32(RxMissed, RTL8139State),
3320 VMSTATE_UINT16(CSCR, RTL8139State),
3321
3322 VMSTATE_UINT8(Cfg9346, RTL8139State),
3323 VMSTATE_UINT8(Config0, RTL8139State),
3324 VMSTATE_UINT8(Config1, RTL8139State),
3325 VMSTATE_UINT8(Config3, RTL8139State),
3326 VMSTATE_UINT8(Config4, RTL8139State),
3327 VMSTATE_UINT8(Config5, RTL8139State),
3328
3329 VMSTATE_UINT8(clock_enabled, RTL8139State),
3330 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3331
3332 VMSTATE_UINT16(MultiIntr, RTL8139State),
3333
3334 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3335 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3336 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3337 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3338 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3339
3340 VMSTATE_UINT16(CpCmd, RTL8139State),
3341 VMSTATE_UINT8(TxThresh, RTL8139State),
3342
3343 VMSTATE_UNUSED(4),
3344 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
3345 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
3346
3347 VMSTATE_UINT32(currTxDesc, RTL8139State),
3348 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3349 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3350 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3351 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3352
3353 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3354 VMSTATE_INT32(eeprom.mode, RTL8139State),
3355 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3356 VMSTATE_UINT8(eeprom.address, RTL8139State),
3357 VMSTATE_UINT16(eeprom.input, RTL8139State),
3358 VMSTATE_UINT16(eeprom.output, RTL8139State),
3359
3360 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3361 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3362 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3363 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3364
3365 VMSTATE_UINT32(TCTR, RTL8139State),
3366 VMSTATE_UINT32(TimerInt, RTL8139State),
3367 VMSTATE_INT64(TCTR_base, RTL8139State),
3368
3369 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3370 vmstate_tally_counters, RTL8139TallyCounters),
3371
3372 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3373 VMSTATE_END_OF_LIST()
3374 },
3375 .subsections = (VMStateSubsection []) {
3376 {
3377 .vmsd = &vmstate_rtl8139_hotplug_ready,
3378 .needed = rtl8139_hotplug_ready_needed,
3379 }, {
3380 /* empty */
3381 }
3382 }
3383 };
3384
3385 /***********************************************************/
3386 /* PCI RTL8139 definitions */
3387
3388 static const MemoryRegionPortio rtl8139_portio[] = {
3389 { 0, 0x100, 1, .read = rtl8139_ioport_readb, },
3390 { 0, 0x100, 1, .write = rtl8139_ioport_writeb, },
3391 { 0, 0x100, 2, .read = rtl8139_ioport_readw, },
3392 { 0, 0x100, 2, .write = rtl8139_ioport_writew, },
3393 { 0, 0x100, 4, .read = rtl8139_ioport_readl, },
3394 { 0, 0x100, 4, .write = rtl8139_ioport_writel, },
3395 PORTIO_END_OF_LIST()
3396 };
3397
3398 static const MemoryRegionOps rtl8139_io_ops = {
3399 .old_portio = rtl8139_portio,
3400 .endianness = DEVICE_LITTLE_ENDIAN,
3401 };
3402
3403 static const MemoryRegionOps rtl8139_mmio_ops = {
3404 .old_mmio = {
3405 .read = {
3406 rtl8139_mmio_readb,
3407 rtl8139_mmio_readw,
3408 rtl8139_mmio_readl,
3409 },
3410 .write = {
3411 rtl8139_mmio_writeb,
3412 rtl8139_mmio_writew,
3413 rtl8139_mmio_writel,
3414 },
3415 },
3416 .endianness = DEVICE_LITTLE_ENDIAN,
3417 };
3418
3419 static void rtl8139_timer(void *opaque)
3420 {
3421 RTL8139State *s = opaque;
3422
3423 if (!s->clock_enabled)
3424 {
3425 DPRINTF(">>> timer: clock is not running\n");
3426 return;
3427 }
3428
3429 s->IntrStatus |= PCSTimeout;
3430 rtl8139_update_irq(s);
3431 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3432 }
3433
3434 static void rtl8139_cleanup(VLANClientState *nc)
3435 {
3436 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
3437
3438 s->nic = NULL;
3439 }
3440
3441 static int pci_rtl8139_uninit(PCIDevice *dev)
3442 {
3443 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3444
3445 memory_region_destroy(&s->bar_io);
3446 memory_region_destroy(&s->bar_mem);
3447 if (s->cplus_txbuffer) {
3448 g_free(s->cplus_txbuffer);
3449 s->cplus_txbuffer = NULL;
3450 }
3451 qemu_del_timer(s->timer);
3452 qemu_free_timer(s->timer);
3453 qemu_del_vlan_client(&s->nic->nc);
3454 return 0;
3455 }
3456
3457 static NetClientInfo net_rtl8139_info = {
3458 .type = NET_CLIENT_OPTIONS_KIND_NIC,
3459 .size = sizeof(NICState),
3460 .can_receive = rtl8139_can_receive,
3461 .receive = rtl8139_receive,
3462 .cleanup = rtl8139_cleanup,
3463 };
3464
3465 static int pci_rtl8139_init(PCIDevice *dev)
3466 {
3467 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
3468 uint8_t *pci_conf;
3469
3470 pci_conf = s->dev.config;
3471 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
3472 /* TODO: start of capability list, but no capability
3473 * list bit in status register, and offset 0xdc seems unused. */
3474 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
3475
3476 memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100);
3477 memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100);
3478 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3479 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
3480
3481 qemu_macaddr_default_if_unset(&s->conf.macaddr);
3482
3483 /* prepare eeprom */
3484 s->eeprom.contents[0] = 0x8129;
3485 #if 1
3486 /* PCI vendor and device ID should be mirrored here */
3487 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3488 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3489 #endif
3490 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3491 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3492 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3493
3494 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3495 object_get_typename(OBJECT(dev)), dev->qdev.id, s);
3496 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
3497
3498 s->cplus_txbuffer = NULL;
3499 s->cplus_txbuffer_len = 0;
3500 s->cplus_txbuffer_offset = 0;
3501
3502 s->TimerExpire = 0;
3503 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
3504 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3505
3506 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3507
3508 return 0;
3509 }
3510
3511 static Property rtl8139_properties[] = {
3512 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3513 DEFINE_PROP_END_OF_LIST(),
3514 };
3515
3516 static void rtl8139_class_init(ObjectClass *klass, void *data)
3517 {
3518 DeviceClass *dc = DEVICE_CLASS(klass);
3519 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3520
3521 k->init = pci_rtl8139_init;
3522 k->exit = pci_rtl8139_uninit;
3523 k->romfile = "pxe-rtl8139.rom";
3524 k->vendor_id = PCI_VENDOR_ID_REALTEK;
3525 k->device_id = PCI_DEVICE_ID_REALTEK_8139;
3526 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3527 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
3528 dc->reset = rtl8139_reset;
3529 dc->vmsd = &vmstate_rtl8139;
3530 dc->props = rtl8139_properties;
3531 }
3532
3533 static TypeInfo rtl8139_info = {
3534 .name = "rtl8139",
3535 .parent = TYPE_PCI_DEVICE,
3536 .instance_size = sizeof(RTL8139State),
3537 .class_init = rtl8139_class_init,
3538 };
3539
3540 static void rtl8139_register_types(void)
3541 {
3542 type_register_static(&rtl8139_info);
3543 }
3544
3545 type_init(rtl8139_register_types)
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