2 * QEMU RTL8139 emulation
4 * Copyright (c) 2006 Igor Kovalenko
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
48 #include "qemu-timer.h"
52 /* debug RTL8139 card */
53 //#define DEBUG_RTL8139 1
55 #define PCI_FREQUENCY 33000000L
57 /* debug RTL8139 card C+ mode only */
58 //#define DEBUG_RTL8139CP 1
60 /* Calculate CRCs properly on Rx packets */
61 #define RTL8139_CALCULATE_RXCRC 1
63 /* Uncomment to enable on-board timer interrupts */
64 //#define RTL8139_ONBOARD_TIMER 1
66 #if defined(RTL8139_CALCULATE_RXCRC)
71 #define SET_MASKED(input, mask, curr) \
72 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
74 /* arg % size for size which is a power of 2 */
75 #define MOD2(input, size) \
76 ( ( input ) & ( size - 1 ) )
78 #if defined (DEBUG_RTL8139)
79 # define DEBUG_PRINT(x) do { printf x ; } while (0)
81 # define DEBUG_PRINT(x)
84 /* Symbolic offsets to registers. */
85 enum RTL8139_registers
{
86 MAC0
= 0, /* Ethernet hardware address. */
87 MAR0
= 8, /* Multicast filter. */
88 TxStatus0
= 0x10,/* Transmit status (Four 32bit registers). C mode only */
89 /* Dump Tally Conter control register(64bit). C+ mode only */
90 TxAddr0
= 0x20, /* Tx descriptors (also four 32bit). */
99 Timer
= 0x48, /* A general-purpose counter. */
100 RxMissed
= 0x4C, /* 24 bits valid, write clears. */
107 Config4
= 0x5A, /* absent on RTL-8139A */
110 PCIRevisionID
= 0x5E,
111 TxSummary
= 0x60, /* TSAD register. Transmit Status of All Descriptors*/
112 BasicModeCtrl
= 0x62,
113 BasicModeStatus
= 0x64,
116 NWayExpansion
= 0x6A,
117 /* Undocumented registers, but required for proper operation. */
118 FIFOTMS
= 0x70, /* FIFO Control and test. */
119 CSCR
= 0x74, /* Chip Status and Configuration Register. */
121 PARA7c
= 0x7c, /* Magic transceiver parameter register. */
122 Config5
= 0xD8, /* absent on RTL-8139A */
124 TxPoll
= 0xD9, /* Tell chip to check Tx descriptors for work */
125 RxMaxSize
= 0xDA, /* Max size of an Rx packet (8169 only) */
126 CpCmd
= 0xE0, /* C+ Command register (C+ mode only) */
127 IntrMitigate
= 0xE2, /* rx/tx interrupt mitigation control */
128 RxRingAddrLO
= 0xE4, /* 64-bit start addr of Rx ring */
129 RxRingAddrHI
= 0xE8, /* 64-bit start addr of Rx ring */
130 TxThresh
= 0xEC, /* Early Tx threshold */
134 MultiIntrClear
= 0xF000,
136 Config1Clear
= (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
148 CPlusRxVLAN
= 0x0040, /* enable receive VLAN detagging */
149 CPlusRxChkSum
= 0x0020, /* enable receive checksum offloading */
154 /* Interrupt register bits, using my own meaningful names. */
155 enum IntrStatusBits
{
166 RxAckBits
= RxFIFOOver
| RxOverflow
| RxOK
,
173 TxOutOfWindow
= 0x20000000,
174 TxAborted
= 0x40000000,
175 TxCarrierLost
= 0x80000000,
178 RxMulticast
= 0x8000,
180 RxBroadcast
= 0x2000,
181 RxBadSymbol
= 0x0020,
189 /* Bits in RxConfig. */
193 AcceptBroadcast
= 0x08,
194 AcceptMulticast
= 0x04,
196 AcceptAllPhys
= 0x01,
199 /* Bits in TxConfig. */
200 enum tx_config_bits
{
202 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
204 TxIFG84
= (0 << TxIFGShift
), /* 8.4us / 840ns (10 / 100Mbps) */
205 TxIFG88
= (1 << TxIFGShift
), /* 8.8us / 880ns (10 / 100Mbps) */
206 TxIFG92
= (2 << TxIFGShift
), /* 9.2us / 920ns (10 / 100Mbps) */
207 TxIFG96
= (3 << TxIFGShift
), /* 9.6us / 960ns (10 / 100Mbps) */
209 TxLoopBack
= (1 << 18) | (1 << 17), /* enable loopback test mode */
210 TxCRC
= (1 << 16), /* DISABLE appending CRC to end of Tx packets */
211 TxClearAbt
= (1 << 0), /* Clear abort (WO) */
212 TxDMAShift
= 8, /* DMA burst value (0-7) is shifted this many bits */
213 TxRetryShift
= 4, /* TXRR value (0-15) is shifted this many bits */
215 TxVersionMask
= 0x7C800000, /* mask out version bits 30-26, 23 */
219 /* Transmit Status of All Descriptors (TSAD) Register */
221 TSAD_TOK3
= 1<<15, // TOK bit of Descriptor 3
222 TSAD_TOK2
= 1<<14, // TOK bit of Descriptor 2
223 TSAD_TOK1
= 1<<13, // TOK bit of Descriptor 1
224 TSAD_TOK0
= 1<<12, // TOK bit of Descriptor 0
225 TSAD_TUN3
= 1<<11, // TUN bit of Descriptor 3
226 TSAD_TUN2
= 1<<10, // TUN bit of Descriptor 2
227 TSAD_TUN1
= 1<<9, // TUN bit of Descriptor 1
228 TSAD_TUN0
= 1<<8, // TUN bit of Descriptor 0
229 TSAD_TABT3
= 1<<07, // TABT bit of Descriptor 3
230 TSAD_TABT2
= 1<<06, // TABT bit of Descriptor 2
231 TSAD_TABT1
= 1<<05, // TABT bit of Descriptor 1
232 TSAD_TABT0
= 1<<04, // TABT bit of Descriptor 0
233 TSAD_OWN3
= 1<<03, // OWN bit of Descriptor 3
234 TSAD_OWN2
= 1<<02, // OWN bit of Descriptor 2
235 TSAD_OWN1
= 1<<01, // OWN bit of Descriptor 1
236 TSAD_OWN0
= 1<<00, // OWN bit of Descriptor 0
240 /* Bits in Config1 */
242 Cfg1_PM_Enable
= 0x01,
243 Cfg1_VPD_Enable
= 0x02,
246 LWAKE
= 0x10, /* not on 8139, 8139A */
247 Cfg1_Driver_Load
= 0x20,
250 SLEEP
= (1 << 1), /* only on 8139, 8139A */
251 PWRDN
= (1 << 0), /* only on 8139, 8139A */
254 /* Bits in Config3 */
256 Cfg3_FBtBEn
= (1 << 0), /* 1 = Fast Back to Back */
257 Cfg3_FuncRegEn
= (1 << 1), /* 1 = enable CardBus Function registers */
258 Cfg3_CLKRUN_En
= (1 << 2), /* 1 = enable CLKRUN */
259 Cfg3_CardB_En
= (1 << 3), /* 1 = enable CardBus registers */
260 Cfg3_LinkUp
= (1 << 4), /* 1 = wake up on link up */
261 Cfg3_Magic
= (1 << 5), /* 1 = wake up on Magic Packet (tm) */
262 Cfg3_PARM_En
= (1 << 6), /* 0 = software can set twister parameters */
263 Cfg3_GNTSel
= (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
266 /* Bits in Config4 */
268 LWPTN
= (1 << 2), /* not on 8139, 8139A */
271 /* Bits in Config5 */
273 Cfg5_PME_STS
= (1 << 0), /* 1 = PCI reset resets PME_Status */
274 Cfg5_LANWake
= (1 << 1), /* 1 = enable LANWake signal */
275 Cfg5_LDPS
= (1 << 2), /* 0 = save power when link is down */
276 Cfg5_FIFOAddrPtr
= (1 << 3), /* Realtek internal SRAM testing */
277 Cfg5_UWF
= (1 << 4), /* 1 = accept unicast wakeup frame */
278 Cfg5_MWF
= (1 << 5), /* 1 = accept multicast wakeup frame */
279 Cfg5_BWF
= (1 << 6), /* 1 = accept broadcast wakeup frame */
283 /* rx fifo threshold */
285 RxCfgFIFONone
= (7 << RxCfgFIFOShift
),
289 RxCfgDMAUnlimited
= (7 << RxCfgDMAShift
),
291 /* rx ring buffer length */
293 RxCfgRcv16K
= (1 << 11),
294 RxCfgRcv32K
= (1 << 12),
295 RxCfgRcv64K
= (1 << 11) | (1 << 12),
297 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
301 /* Twister tuning parameters from RealTek.
302 Completely undocumented, but required to tune bad links on some boards. */
305 CSCR_LinkOKBit = 0x0400,
306 CSCR_LinkChangeBit = 0x0800,
307 CSCR_LinkStatusBits = 0x0f000,
308 CSCR_LinkDownOffCmd = 0x003c0,
309 CSCR_LinkDownCmd = 0x0f3c0,
312 CSCR_Testfun
= 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
313 CSCR_LD
= 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
314 CSCR_HEART_BIT
= 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
315 CSCR_JBEN
= 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
316 CSCR_F_LINK_100
= 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
317 CSCR_F_Connect
= 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
318 CSCR_Con_status
= 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
319 CSCR_Con_status_En
= 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
320 CSCR_PASS_SCR
= 1<<0, /* Bypass Scramble, def 0*/
325 Cfg9346_Unlock
= 0xC0,
342 HasHltClk
= (1 << 0),
346 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
347 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
348 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
350 #define RTL8139_PCI_REVID_8139 0x10
351 #define RTL8139_PCI_REVID_8139CPLUS 0x20
353 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
355 /* Size is 64 * 16bit words */
356 #define EEPROM_9346_ADDR_BITS 6
357 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
358 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
360 enum Chip9346Operation
362 Chip9346_op_mask
= 0xc0, /* 10 zzzzzz */
363 Chip9346_op_read
= 0x80, /* 10 AAAAAA */
364 Chip9346_op_write
= 0x40, /* 01 AAAAAA D(15)..D(0) */
365 Chip9346_op_ext_mask
= 0xf0, /* 11 zzzzzz */
366 Chip9346_op_write_enable
= 0x30, /* 00 11zzzz */
367 Chip9346_op_write_all
= 0x10, /* 00 01zzzz */
368 Chip9346_op_write_disable
= 0x00, /* 00 00zzzz */
374 Chip9346_enter_command_mode
,
375 Chip9346_read_command
,
376 Chip9346_data_read
, /* from output register */
377 Chip9346_data_write
, /* to input register, then to contents at specified address */
378 Chip9346_data_write_all
, /* to input register, then filling contents */
381 typedef struct EEprom9346
383 uint16_t contents
[EEPROM_9346_SIZE
];
396 typedef struct RTL8139TallyCounters
412 } RTL8139TallyCounters
;
414 /* Clears all tally counters */
415 static void RTL8139TallyCounters_clear(RTL8139TallyCounters
* counters
);
417 /* Writes tally counters to specified physical memory address */
418 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr
, RTL8139TallyCounters
* counters
);
420 /* Loads values of tally counters from VM state file */
421 static void RTL8139TallyCounters_load(QEMUFile
* f
, RTL8139TallyCounters
*tally_counters
);
423 /* Saves values of tally counters to VM state file */
424 static void RTL8139TallyCounters_save(QEMUFile
* f
, RTL8139TallyCounters
*tally_counters
);
426 typedef struct RTL8139State
{
428 uint8_t phys
[8]; /* mac address */
429 uint8_t mult
[8]; /* multicast mask array */
431 uint32_t TxStatus
[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
432 uint32_t TxAddr
[4]; /* TxAddr0 */
433 uint32_t RxBuf
; /* Receive buffer */
434 uint32_t RxBufferSize
;/* internal variable, receive ring buffer size in C mode */
454 uint8_t clock_enabled
;
455 uint8_t bChipCmdState
;
459 uint16_t BasicModeCtrl
;
460 uint16_t BasicModeStatus
;
463 uint16_t NWayExpansion
;
470 int rtl8139_mmio_io_addr
;
476 uint32_t cplus_enabled
;
478 uint32_t currCPlusRxDesc
;
479 uint32_t currCPlusTxDesc
;
481 uint32_t RxRingAddrLO
;
482 uint32_t RxRingAddrHI
;
491 RTL8139TallyCounters tally_counters
;
493 /* Non-persistent data */
494 uint8_t *cplus_txbuffer
;
495 int cplus_txbuffer_len
;
496 int cplus_txbuffer_offset
;
498 /* PCI interrupt timer */
503 static void prom9346_decode_command(EEprom9346
*eeprom
, uint8_t command
)
505 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command
));
507 switch (command
& Chip9346_op_mask
)
509 case Chip9346_op_read
:
511 eeprom
->address
= command
& EEPROM_9346_ADDR_MASK
;
512 eeprom
->output
= eeprom
->contents
[eeprom
->address
];
515 eeprom
->mode
= Chip9346_data_read
;
516 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
517 eeprom
->address
, eeprom
->output
));
521 case Chip9346_op_write
:
523 eeprom
->address
= command
& EEPROM_9346_ADDR_MASK
;
526 eeprom
->mode
= Chip9346_none
; /* Chip9346_data_write */
527 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
532 eeprom
->mode
= Chip9346_none
;
533 switch (command
& Chip9346_op_ext_mask
)
535 case Chip9346_op_write_enable
:
536 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
538 case Chip9346_op_write_all
:
539 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
541 case Chip9346_op_write_disable
:
542 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
549 static void prom9346_shift_clock(EEprom9346
*eeprom
)
551 int bit
= eeprom
->eedi
?1:0;
555 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom
->tick
, eeprom
->eedi
, eeprom
->eedo
));
557 switch (eeprom
->mode
)
559 case Chip9346_enter_command_mode
:
562 eeprom
->mode
= Chip9346_read_command
;
565 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
569 case Chip9346_read_command
:
570 eeprom
->input
= (eeprom
->input
<< 1) | (bit
& 1);
571 if (eeprom
->tick
== 8)
573 prom9346_decode_command(eeprom
, eeprom
->input
& 0xff);
577 case Chip9346_data_read
:
578 eeprom
->eedo
= (eeprom
->output
& 0x8000)?1:0;
579 eeprom
->output
<<= 1;
580 if (eeprom
->tick
== 16)
583 // the FreeBSD drivers (rl and re) don't explicitly toggle
584 // CS between reads (or does setting Cfg9346 to 0 count too?),
585 // so we need to enter wait-for-command state here
586 eeprom
->mode
= Chip9346_enter_command_mode
;
590 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
592 // original behaviour
594 eeprom
->address
&= EEPROM_9346_ADDR_MASK
;
595 eeprom
->output
= eeprom
->contents
[eeprom
->address
];
598 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
599 eeprom
->address
, eeprom
->output
));
604 case Chip9346_data_write
:
605 eeprom
->input
= (eeprom
->input
<< 1) | (bit
& 1);
606 if (eeprom
->tick
== 16)
608 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
609 eeprom
->address
, eeprom
->input
));
611 eeprom
->contents
[eeprom
->address
] = eeprom
->input
;
612 eeprom
->mode
= Chip9346_none
; /* waiting for next command after CS cycle */
618 case Chip9346_data_write_all
:
619 eeprom
->input
= (eeprom
->input
<< 1) | (bit
& 1);
620 if (eeprom
->tick
== 16)
623 for (i
= 0; i
< EEPROM_9346_SIZE
; i
++)
625 eeprom
->contents
[i
] = eeprom
->input
;
627 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
630 eeprom
->mode
= Chip9346_enter_command_mode
;
641 static int prom9346_get_wire(RTL8139State
*s
)
643 EEprom9346
*eeprom
= &s
->eeprom
;
650 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
651 static void prom9346_set_wire(RTL8139State
*s
, int eecs
, int eesk
, int eedi
)
653 EEprom9346
*eeprom
= &s
->eeprom
;
654 uint8_t old_eecs
= eeprom
->eecs
;
655 uint8_t old_eesk
= eeprom
->eesk
;
661 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
662 eeprom
->eecs
, eeprom
->eesk
, eeprom
->eedi
, eeprom
->eedo
));
664 if (!old_eecs
&& eecs
)
666 /* Synchronize start */
670 eeprom
->mode
= Chip9346_enter_command_mode
;
672 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
677 DEBUG_PRINT(("=== eeprom: end access\n"));
681 if (!old_eesk
&& eesk
)
684 prom9346_shift_clock(eeprom
);
688 static void rtl8139_update_irq(RTL8139State
*s
)
691 isr
= (s
->IntrStatus
& s
->IntrMask
) & 0xffff;
693 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
694 isr
? 1 : 0, s
->IntrStatus
, s
->IntrMask
));
696 qemu_set_irq(s
->dev
.irq
[0], (isr
!= 0));
699 #define POLYNOMIAL 0x04c11db6
703 static int compute_mcast_idx(const uint8_t *ep
)
710 for (i
= 0; i
< 6; i
++) {
712 for (j
= 0; j
< 8; j
++) {
713 carry
= ((crc
& 0x80000000L
) ? 1 : 0) ^ (b
& 0x01);
717 crc
= ((crc
^ POLYNOMIAL
) | carry
);
723 static int rtl8139_RxWrap(RTL8139State
*s
)
725 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
726 return (s
->RxConfig
& (1 << 7));
729 static int rtl8139_receiver_enabled(RTL8139State
*s
)
731 return s
->bChipCmdState
& CmdRxEnb
;
734 static int rtl8139_transmitter_enabled(RTL8139State
*s
)
736 return s
->bChipCmdState
& CmdTxEnb
;
739 static int rtl8139_cp_receiver_enabled(RTL8139State
*s
)
741 return s
->CpCmd
& CPlusRxEnb
;
744 static int rtl8139_cp_transmitter_enabled(RTL8139State
*s
)
746 return s
->CpCmd
& CPlusTxEnb
;
749 static void rtl8139_write_buffer(RTL8139State
*s
, const void *buf
, int size
)
751 if (s
->RxBufAddr
+ size
> s
->RxBufferSize
)
753 int wrapped
= MOD2(s
->RxBufAddr
+ size
, s
->RxBufferSize
);
755 /* write packet data */
756 if (wrapped
&& !(s
->RxBufferSize
< 65536 && rtl8139_RxWrap(s
)))
758 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size
-wrapped
));
762 cpu_physical_memory_write( s
->RxBuf
+ s
->RxBufAddr
,
766 /* reset buffer pointer */
769 cpu_physical_memory_write( s
->RxBuf
+ s
->RxBufAddr
,
770 buf
+ (size
-wrapped
), wrapped
);
772 s
->RxBufAddr
= wrapped
;
778 /* non-wrapping path or overwrapping enabled */
779 cpu_physical_memory_write( s
->RxBuf
+ s
->RxBufAddr
, buf
, size
);
781 s
->RxBufAddr
+= size
;
784 #define MIN_BUF_SIZE 60
785 static inline target_phys_addr_t
rtl8139_addr64(uint32_t low
, uint32_t high
)
787 #if TARGET_PHYS_ADDR_BITS > 32
788 return low
| ((target_phys_addr_t
)high
<< 32);
794 static int rtl8139_can_receive(VLANClientState
*vc
)
796 RTL8139State
*s
= vc
->opaque
;
799 /* Receive (drop) packets if card is disabled. */
800 if (!s
->clock_enabled
)
802 if (!rtl8139_receiver_enabled(s
))
805 if (rtl8139_cp_receiver_enabled(s
)) {
806 /* ??? Flow control not implemented in c+ mode.
807 This is a hack to work around slirp deficiencies anyway. */
810 avail
= MOD2(s
->RxBufferSize
+ s
->RxBufPtr
- s
->RxBufAddr
,
812 return (avail
== 0 || avail
>= 1514);
816 static ssize_t
rtl8139_do_receive(VLANClientState
*vc
, const uint8_t *buf
, size_t size_
, int do_interrupt
)
818 RTL8139State
*s
= vc
->opaque
;
821 uint32_t packet_header
= 0;
824 static const uint8_t broadcast_macaddr
[6] =
825 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
827 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size
));
829 /* test if board clock is stopped */
830 if (!s
->clock_enabled
)
832 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
836 /* first check if receiver is enabled */
838 if (!rtl8139_receiver_enabled(s
))
840 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
844 /* XXX: check this */
845 if (s
->RxConfig
& AcceptAllPhys
) {
846 /* promiscuous: receive all */
847 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
850 if (!memcmp(buf
, broadcast_macaddr
, 6)) {
851 /* broadcast address */
852 if (!(s
->RxConfig
& AcceptBroadcast
))
854 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
856 /* update tally counter */
857 ++s
->tally_counters
.RxERR
;
862 packet_header
|= RxBroadcast
;
864 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
866 /* update tally counter */
867 ++s
->tally_counters
.RxOkBrd
;
869 } else if (buf
[0] & 0x01) {
871 if (!(s
->RxConfig
& AcceptMulticast
))
873 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
875 /* update tally counter */
876 ++s
->tally_counters
.RxERR
;
881 int mcast_idx
= compute_mcast_idx(buf
);
883 if (!(s
->mult
[mcast_idx
>> 3] & (1 << (mcast_idx
& 7))))
885 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
887 /* update tally counter */
888 ++s
->tally_counters
.RxERR
;
893 packet_header
|= RxMulticast
;
895 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
897 /* update tally counter */
898 ++s
->tally_counters
.RxOkMul
;
900 } else if (s
->phys
[0] == buf
[0] &&
901 s
->phys
[1] == buf
[1] &&
902 s
->phys
[2] == buf
[2] &&
903 s
->phys
[3] == buf
[3] &&
904 s
->phys
[4] == buf
[4] &&
905 s
->phys
[5] == buf
[5]) {
907 if (!(s
->RxConfig
& AcceptMyPhys
))
909 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
911 /* update tally counter */
912 ++s
->tally_counters
.RxERR
;
917 packet_header
|= RxPhysical
;
919 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
921 /* update tally counter */
922 ++s
->tally_counters
.RxOkPhy
;
926 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
928 /* update tally counter */
929 ++s
->tally_counters
.RxERR
;
935 /* if too small buffer, then expand it */
936 if (size
< MIN_BUF_SIZE
) {
937 memcpy(buf1
, buf
, size
);
938 memset(buf1
+ size
, 0, MIN_BUF_SIZE
- size
);
943 if (rtl8139_cp_receiver_enabled(s
))
945 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
947 /* begin C+ receiver mode */
949 /* w0 ownership flag */
950 #define CP_RX_OWN (1<<31)
951 /* w0 end of ring flag */
952 #define CP_RX_EOR (1<<30)
953 /* w0 bits 0...12 : buffer size */
954 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
955 /* w1 tag available flag */
956 #define CP_RX_TAVA (1<<16)
957 /* w1 bits 0...15 : VLAN tag */
958 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
959 /* w2 low 32bit of Rx buffer ptr */
960 /* w3 high 32bit of Rx buffer ptr */
962 int descriptor
= s
->currCPlusRxDesc
;
963 target_phys_addr_t cplus_rx_ring_desc
;
965 cplus_rx_ring_desc
= rtl8139_addr64(s
->RxRingAddrLO
, s
->RxRingAddrHI
);
966 cplus_rx_ring_desc
+= 16 * descriptor
;
968 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64
"\n",
969 descriptor
, s
->RxRingAddrHI
, s
->RxRingAddrLO
, (uint64_t)cplus_rx_ring_desc
));
971 uint32_t val
, rxdw0
,rxdw1
,rxbufLO
,rxbufHI
;
973 cpu_physical_memory_read(cplus_rx_ring_desc
, (uint8_t *)&val
, 4);
974 rxdw0
= le32_to_cpu(val
);
975 cpu_physical_memory_read(cplus_rx_ring_desc
+4, (uint8_t *)&val
, 4);
976 rxdw1
= le32_to_cpu(val
);
977 cpu_physical_memory_read(cplus_rx_ring_desc
+8, (uint8_t *)&val
, 4);
978 rxbufLO
= le32_to_cpu(val
);
979 cpu_physical_memory_read(cplus_rx_ring_desc
+12, (uint8_t *)&val
, 4);
980 rxbufHI
= le32_to_cpu(val
);
982 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
984 rxdw0
, rxdw1
, rxbufLO
, rxbufHI
));
986 if (!(rxdw0
& CP_RX_OWN
))
988 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor
));
990 s
->IntrStatus
|= RxOverflow
;
993 /* update tally counter */
994 ++s
->tally_counters
.RxERR
;
995 ++s
->tally_counters
.MissPkt
;
997 rtl8139_update_irq(s
);
1001 uint32_t rx_space
= rxdw0
& CP_RX_BUFFER_SIZE_MASK
;
1003 /* TODO: scatter the packet over available receive ring descriptors space */
1005 if (size
+4 > rx_space
)
1007 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1008 descriptor
, rx_space
, size
));
1010 s
->IntrStatus
|= RxOverflow
;
1013 /* update tally counter */
1014 ++s
->tally_counters
.RxERR
;
1015 ++s
->tally_counters
.MissPkt
;
1017 rtl8139_update_irq(s
);
1021 target_phys_addr_t rx_addr
= rtl8139_addr64(rxbufLO
, rxbufHI
);
1023 /* receive/copy to target memory */
1024 cpu_physical_memory_write( rx_addr
, buf
, size
);
1026 if (s
->CpCmd
& CPlusRxChkSum
)
1028 /* do some packet checksumming */
1031 /* write checksum */
1032 #if defined (RTL8139_CALCULATE_RXCRC)
1033 val
= cpu_to_le32(crc32(0, buf
, size
));
1037 cpu_physical_memory_write( rx_addr
+size
, (uint8_t *)&val
, 4);
1039 /* first segment of received packet flag */
1040 #define CP_RX_STATUS_FS (1<<29)
1041 /* last segment of received packet flag */
1042 #define CP_RX_STATUS_LS (1<<28)
1043 /* multicast packet flag */
1044 #define CP_RX_STATUS_MAR (1<<26)
1045 /* physical-matching packet flag */
1046 #define CP_RX_STATUS_PAM (1<<25)
1047 /* broadcast packet flag */
1048 #define CP_RX_STATUS_BAR (1<<24)
1049 /* runt packet flag */
1050 #define CP_RX_STATUS_RUNT (1<<19)
1051 /* crc error flag */
1052 #define CP_RX_STATUS_CRC (1<<18)
1053 /* IP checksum error flag */
1054 #define CP_RX_STATUS_IPF (1<<15)
1055 /* UDP checksum error flag */
1056 #define CP_RX_STATUS_UDPF (1<<14)
1057 /* TCP checksum error flag */
1058 #define CP_RX_STATUS_TCPF (1<<13)
1060 /* transfer ownership to target */
1061 rxdw0
&= ~CP_RX_OWN
;
1063 /* set first segment bit */
1064 rxdw0
|= CP_RX_STATUS_FS
;
1066 /* set last segment bit */
1067 rxdw0
|= CP_RX_STATUS_LS
;
1069 /* set received packet type flags */
1070 if (packet_header
& RxBroadcast
)
1071 rxdw0
|= CP_RX_STATUS_BAR
;
1072 if (packet_header
& RxMulticast
)
1073 rxdw0
|= CP_RX_STATUS_MAR
;
1074 if (packet_header
& RxPhysical
)
1075 rxdw0
|= CP_RX_STATUS_PAM
;
1077 /* set received size */
1078 rxdw0
&= ~CP_RX_BUFFER_SIZE_MASK
;
1081 /* reset VLAN tag flag */
1082 rxdw1
&= ~CP_RX_TAVA
;
1084 /* update ring data */
1085 val
= cpu_to_le32(rxdw0
);
1086 cpu_physical_memory_write(cplus_rx_ring_desc
, (uint8_t *)&val
, 4);
1087 val
= cpu_to_le32(rxdw1
);
1088 cpu_physical_memory_write(cplus_rx_ring_desc
+4, (uint8_t *)&val
, 4);
1090 /* update tally counter */
1091 ++s
->tally_counters
.RxOk
;
1093 /* seek to next Rx descriptor */
1094 if (rxdw0
& CP_RX_EOR
)
1096 s
->currCPlusRxDesc
= 0;
1100 ++s
->currCPlusRxDesc
;
1103 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
1108 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1110 /* begin ring receiver mode */
1111 int avail
= MOD2(s
->RxBufferSize
+ s
->RxBufPtr
- s
->RxBufAddr
, s
->RxBufferSize
);
1113 /* if receiver buffer is empty then avail == 0 */
1115 if (avail
!= 0 && size
+ 8 >= avail
)
1117 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1118 s
->RxBufferSize
, s
->RxBufAddr
, s
->RxBufPtr
, avail
, size
+ 8));
1120 s
->IntrStatus
|= RxOverflow
;
1122 rtl8139_update_irq(s
);
1126 packet_header
|= RxStatusOK
;
1128 packet_header
|= (((size
+4) << 16) & 0xffff0000);
1131 uint32_t val
= cpu_to_le32(packet_header
);
1133 rtl8139_write_buffer(s
, (uint8_t *)&val
, 4);
1135 rtl8139_write_buffer(s
, buf
, size
);
1137 /* write checksum */
1138 #if defined (RTL8139_CALCULATE_RXCRC)
1139 val
= cpu_to_le32(crc32(0, buf
, size
));
1144 rtl8139_write_buffer(s
, (uint8_t *)&val
, 4);
1146 /* correct buffer write pointer */
1147 s
->RxBufAddr
= MOD2((s
->RxBufAddr
+ 3) & ~0x3, s
->RxBufferSize
);
1149 /* now we can signal we have received something */
1151 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1152 s
->RxBufferSize
, s
->RxBufAddr
, s
->RxBufPtr
));
1155 s
->IntrStatus
|= RxOK
;
1159 rtl8139_update_irq(s
);
1165 static ssize_t
rtl8139_receive(VLANClientState
*vc
, const uint8_t *buf
, size_t size
)
1167 return rtl8139_do_receive(vc
, buf
, size
, 1);
1170 static void rtl8139_reset_rxring(RTL8139State
*s
, uint32_t bufferSize
)
1172 s
->RxBufferSize
= bufferSize
;
1177 static void rtl8139_reset(DeviceState
*d
)
1179 RTL8139State
*s
= container_of(d
, RTL8139State
, dev
.qdev
);
1182 /* restore MAC address */
1183 memcpy(s
->phys
, s
->conf
.macaddr
.a
, 6);
1185 /* reset interrupt mask */
1189 rtl8139_update_irq(s
);
1191 /* prepare eeprom */
1192 s
->eeprom
.contents
[0] = 0x8129;
1194 // PCI vendor and device ID should be mirrored here
1195 s
->eeprom
.contents
[1] = PCI_VENDOR_ID_REALTEK
;
1196 s
->eeprom
.contents
[2] = PCI_DEVICE_ID_REALTEK_8139
;
1199 s
->eeprom
.contents
[7] = s
->conf
.macaddr
.a
[0] | s
->conf
.macaddr
.a
[1] << 8;
1200 s
->eeprom
.contents
[8] = s
->conf
.macaddr
.a
[2] | s
->conf
.macaddr
.a
[3] << 8;
1201 s
->eeprom
.contents
[9] = s
->conf
.macaddr
.a
[4] | s
->conf
.macaddr
.a
[5] << 8;
1203 /* mark all status registers as owned by host */
1204 for (i
= 0; i
< 4; ++i
)
1206 s
->TxStatus
[i
] = TxHostOwns
;
1210 s
->currCPlusRxDesc
= 0;
1211 s
->currCPlusTxDesc
= 0;
1213 s
->RxRingAddrLO
= 0;
1214 s
->RxRingAddrHI
= 0;
1218 rtl8139_reset_rxring(s
, 8192);
1224 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1225 s
->clock_enabled
= 0;
1227 s
->TxConfig
|= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1228 s
->clock_enabled
= 1;
1231 s
->bChipCmdState
= CmdReset
; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1233 /* set initial state data */
1234 s
->Config0
= 0x0; /* No boot ROM */
1235 s
->Config1
= 0xC; /* IO mapped and MEM mapped registers available */
1236 s
->Config3
= 0x1; /* fast back-to-back compatible */
1239 s
->CSCR
= CSCR_F_LINK_100
| CSCR_HEART_BIT
| CSCR_LD
;
1241 s
->CpCmd
= 0x0; /* reset C+ mode */
1242 s
->cplus_enabled
= 0;
1245 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1246 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1247 s
->BasicModeCtrl
= 0x1000; // autonegotiation
1249 s
->BasicModeStatus
= 0x7809;
1250 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1251 s
->BasicModeStatus
|= 0x0020; /* autonegotiation completed */
1252 s
->BasicModeStatus
|= 0x0004; /* link is up */
1254 s
->NWayAdvert
= 0x05e1; /* all modes, full duplex */
1255 s
->NWayLPAR
= 0x05e1; /* all modes, full duplex */
1256 s
->NWayExpansion
= 0x0001; /* autonegotiation supported */
1258 /* also reset timer and disable timer interrupt */
1263 /* reset tally counters */
1264 RTL8139TallyCounters_clear(&s
->tally_counters
);
1267 static void RTL8139TallyCounters_clear(RTL8139TallyCounters
* counters
)
1271 counters
->TxERR
= 0;
1272 counters
->RxERR
= 0;
1273 counters
->MissPkt
= 0;
1275 counters
->Tx1Col
= 0;
1276 counters
->TxMCol
= 0;
1277 counters
->RxOkPhy
= 0;
1278 counters
->RxOkBrd
= 0;
1279 counters
->RxOkMul
= 0;
1280 counters
->TxAbt
= 0;
1281 counters
->TxUndrn
= 0;
1284 static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr
, RTL8139TallyCounters
* tally_counters
)
1290 val64
= cpu_to_le64(tally_counters
->TxOk
);
1291 cpu_physical_memory_write(tc_addr
+ 0, (uint8_t *)&val64
, 8);
1293 val64
= cpu_to_le64(tally_counters
->RxOk
);
1294 cpu_physical_memory_write(tc_addr
+ 8, (uint8_t *)&val64
, 8);
1296 val64
= cpu_to_le64(tally_counters
->TxERR
);
1297 cpu_physical_memory_write(tc_addr
+ 16, (uint8_t *)&val64
, 8);
1299 val32
= cpu_to_le32(tally_counters
->RxERR
);
1300 cpu_physical_memory_write(tc_addr
+ 24, (uint8_t *)&val32
, 4);
1302 val16
= cpu_to_le16(tally_counters
->MissPkt
);
1303 cpu_physical_memory_write(tc_addr
+ 28, (uint8_t *)&val16
, 2);
1305 val16
= cpu_to_le16(tally_counters
->FAE
);
1306 cpu_physical_memory_write(tc_addr
+ 30, (uint8_t *)&val16
, 2);
1308 val32
= cpu_to_le32(tally_counters
->Tx1Col
);
1309 cpu_physical_memory_write(tc_addr
+ 32, (uint8_t *)&val32
, 4);
1311 val32
= cpu_to_le32(tally_counters
->TxMCol
);
1312 cpu_physical_memory_write(tc_addr
+ 36, (uint8_t *)&val32
, 4);
1314 val64
= cpu_to_le64(tally_counters
->RxOkPhy
);
1315 cpu_physical_memory_write(tc_addr
+ 40, (uint8_t *)&val64
, 8);
1317 val64
= cpu_to_le64(tally_counters
->RxOkBrd
);
1318 cpu_physical_memory_write(tc_addr
+ 48, (uint8_t *)&val64
, 8);
1320 val32
= cpu_to_le32(tally_counters
->RxOkMul
);
1321 cpu_physical_memory_write(tc_addr
+ 56, (uint8_t *)&val32
, 4);
1323 val16
= cpu_to_le16(tally_counters
->TxAbt
);
1324 cpu_physical_memory_write(tc_addr
+ 60, (uint8_t *)&val16
, 2);
1326 val16
= cpu_to_le16(tally_counters
->TxUndrn
);
1327 cpu_physical_memory_write(tc_addr
+ 62, (uint8_t *)&val16
, 2);
1330 /* Loads values of tally counters from VM state file */
1332 static const VMStateDescription vmstate_tally_counters
= {
1333 .name
= "tally_counters",
1335 .minimum_version_id
= 1,
1336 .minimum_version_id_old
= 1,
1337 .fields
= (VMStateField
[]) {
1338 VMSTATE_UINT64(TxOk
, RTL8139TallyCounters
),
1339 VMSTATE_UINT64(RxOk
, RTL8139TallyCounters
),
1340 VMSTATE_UINT64(TxERR
, RTL8139TallyCounters
),
1341 VMSTATE_UINT32(RxERR
, RTL8139TallyCounters
),
1342 VMSTATE_UINT16(MissPkt
, RTL8139TallyCounters
),
1343 VMSTATE_UINT16(FAE
, RTL8139TallyCounters
),
1344 VMSTATE_UINT32(Tx1Col
, RTL8139TallyCounters
),
1345 VMSTATE_UINT32(TxMCol
, RTL8139TallyCounters
),
1346 VMSTATE_UINT64(RxOkPhy
, RTL8139TallyCounters
),
1347 VMSTATE_UINT64(RxOkBrd
, RTL8139TallyCounters
),
1348 VMSTATE_UINT16(TxAbt
, RTL8139TallyCounters
),
1349 VMSTATE_UINT16(TxUndrn
, RTL8139TallyCounters
),
1350 VMSTATE_END_OF_LIST()
1353 static void RTL8139TallyCounters_load(QEMUFile
* f
, RTL8139TallyCounters
*tally_counters
)
1355 vmstate_load_state(f
, &vmstate_tally_counters
, tally_counters
, vmstate_tally_counters
.version_id
);
1358 /* Saves values of tally counters to VM state file */
1359 static void RTL8139TallyCounters_save(QEMUFile
* f
, RTL8139TallyCounters
*tally_counters
)
1361 vmstate_save_state(f
, &vmstate_tally_counters
, tally_counters
);
1364 static void rtl8139_ChipCmd_write(RTL8139State
*s
, uint32_t val
)
1368 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val
));
1372 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
1373 rtl8139_reset(&s
->dev
.qdev
);
1377 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
1379 s
->currCPlusRxDesc
= 0;
1383 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
1385 s
->currCPlusTxDesc
= 0;
1388 /* mask unwriteable bits */
1389 val
= SET_MASKED(val
, 0xe3, s
->bChipCmdState
);
1391 /* Deassert reset pin before next read */
1394 s
->bChipCmdState
= val
;
1397 static int rtl8139_RxBufferEmpty(RTL8139State
*s
)
1399 int unread
= MOD2(s
->RxBufferSize
+ s
->RxBufAddr
- s
->RxBufPtr
, s
->RxBufferSize
);
1403 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread
));
1407 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
1412 static uint32_t rtl8139_ChipCmd_read(RTL8139State
*s
)
1414 uint32_t ret
= s
->bChipCmdState
;
1416 if (rtl8139_RxBufferEmpty(s
))
1419 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret
));
1424 static void rtl8139_CpCmd_write(RTL8139State
*s
, uint32_t val
)
1428 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val
));
1430 s
->cplus_enabled
= 1;
1432 /* mask unwriteable bits */
1433 val
= SET_MASKED(val
, 0xff84, s
->CpCmd
);
1438 static uint32_t rtl8139_CpCmd_read(RTL8139State
*s
)
1440 uint32_t ret
= s
->CpCmd
;
1442 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret
));
1447 static void rtl8139_IntrMitigate_write(RTL8139State
*s
, uint32_t val
)
1449 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val
));
1452 static uint32_t rtl8139_IntrMitigate_read(RTL8139State
*s
)
1456 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret
));
1461 static int rtl8139_config_writeable(RTL8139State
*s
)
1463 if (s
->Cfg9346
& Cfg9346_Unlock
)
1468 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
1473 static void rtl8139_BasicModeCtrl_write(RTL8139State
*s
, uint32_t val
)
1477 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val
));
1479 /* mask unwriteable bits */
1480 uint32_t mask
= 0x4cff;
1482 if (1 || !rtl8139_config_writeable(s
))
1484 /* Speed setting and autonegotiation enable bits are read-only */
1486 /* Duplex mode setting is read-only */
1490 val
= SET_MASKED(val
, mask
, s
->BasicModeCtrl
);
1492 s
->BasicModeCtrl
= val
;
1495 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State
*s
)
1497 uint32_t ret
= s
->BasicModeCtrl
;
1499 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret
));
1504 static void rtl8139_BasicModeStatus_write(RTL8139State
*s
, uint32_t val
)
1508 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val
));
1510 /* mask unwriteable bits */
1511 val
= SET_MASKED(val
, 0xff3f, s
->BasicModeStatus
);
1513 s
->BasicModeStatus
= val
;
1516 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State
*s
)
1518 uint32_t ret
= s
->BasicModeStatus
;
1520 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret
));
1525 static void rtl8139_Cfg9346_write(RTL8139State
*s
, uint32_t val
)
1529 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val
));
1531 /* mask unwriteable bits */
1532 val
= SET_MASKED(val
, 0x31, s
->Cfg9346
);
1534 uint32_t opmode
= val
& 0xc0;
1535 uint32_t eeprom_val
= val
& 0xf;
1537 if (opmode
== 0x80) {
1539 int eecs
= (eeprom_val
& 0x08)?1:0;
1540 int eesk
= (eeprom_val
& 0x04)?1:0;
1541 int eedi
= (eeprom_val
& 0x02)?1:0;
1542 prom9346_set_wire(s
, eecs
, eesk
, eedi
);
1543 } else if (opmode
== 0x40) {
1546 rtl8139_reset(&s
->dev
.qdev
);
1552 static uint32_t rtl8139_Cfg9346_read(RTL8139State
*s
)
1554 uint32_t ret
= s
->Cfg9346
;
1556 uint32_t opmode
= ret
& 0xc0;
1561 int eedo
= prom9346_get_wire(s
);
1572 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret
));
1577 static void rtl8139_Config0_write(RTL8139State
*s
, uint32_t val
)
1581 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val
));
1583 if (!rtl8139_config_writeable(s
))
1586 /* mask unwriteable bits */
1587 val
= SET_MASKED(val
, 0xf8, s
->Config0
);
1592 static uint32_t rtl8139_Config0_read(RTL8139State
*s
)
1594 uint32_t ret
= s
->Config0
;
1596 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret
));
1601 static void rtl8139_Config1_write(RTL8139State
*s
, uint32_t val
)
1605 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val
));
1607 if (!rtl8139_config_writeable(s
))
1610 /* mask unwriteable bits */
1611 val
= SET_MASKED(val
, 0xC, s
->Config1
);
1616 static uint32_t rtl8139_Config1_read(RTL8139State
*s
)
1618 uint32_t ret
= s
->Config1
;
1620 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret
));
1625 static void rtl8139_Config3_write(RTL8139State
*s
, uint32_t val
)
1629 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val
));
1631 if (!rtl8139_config_writeable(s
))
1634 /* mask unwriteable bits */
1635 val
= SET_MASKED(val
, 0x8F, s
->Config3
);
1640 static uint32_t rtl8139_Config3_read(RTL8139State
*s
)
1642 uint32_t ret
= s
->Config3
;
1644 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret
));
1649 static void rtl8139_Config4_write(RTL8139State
*s
, uint32_t val
)
1653 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val
));
1655 if (!rtl8139_config_writeable(s
))
1658 /* mask unwriteable bits */
1659 val
= SET_MASKED(val
, 0x0a, s
->Config4
);
1664 static uint32_t rtl8139_Config4_read(RTL8139State
*s
)
1666 uint32_t ret
= s
->Config4
;
1668 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret
));
1673 static void rtl8139_Config5_write(RTL8139State
*s
, uint32_t val
)
1677 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val
));
1679 /* mask unwriteable bits */
1680 val
= SET_MASKED(val
, 0x80, s
->Config5
);
1685 static uint32_t rtl8139_Config5_read(RTL8139State
*s
)
1687 uint32_t ret
= s
->Config5
;
1689 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret
));
1694 static void rtl8139_TxConfig_write(RTL8139State
*s
, uint32_t val
)
1696 if (!rtl8139_transmitter_enabled(s
))
1698 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val
));
1702 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val
));
1704 val
= SET_MASKED(val
, TxVersionMask
| 0x8070f80f, s
->TxConfig
);
1709 static void rtl8139_TxConfig_writeb(RTL8139State
*s
, uint32_t val
)
1711 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val
));
1713 uint32_t tc
= s
->TxConfig
;
1715 tc
|= (val
& 0x000000FF);
1716 rtl8139_TxConfig_write(s
, tc
);
1719 static uint32_t rtl8139_TxConfig_read(RTL8139State
*s
)
1721 uint32_t ret
= s
->TxConfig
;
1723 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret
));
1728 static void rtl8139_RxConfig_write(RTL8139State
*s
, uint32_t val
)
1730 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val
));
1732 /* mask unwriteable bits */
1733 val
= SET_MASKED(val
, 0xf0fc0040, s
->RxConfig
);
1737 /* reset buffer size and read/write pointers */
1738 rtl8139_reset_rxring(s
, 8192 << ((s
->RxConfig
>> 11) & 0x3));
1740 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s
->RxBufferSize
));
1743 static uint32_t rtl8139_RxConfig_read(RTL8139State
*s
)
1745 uint32_t ret
= s
->RxConfig
;
1747 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret
));
1752 static void rtl8139_transfer_frame(RTL8139State
*s
, const uint8_t *buf
, int size
, int do_interrupt
)
1756 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1760 if (TxLoopBack
== (s
->TxConfig
& TxLoopBack
))
1762 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1763 rtl8139_do_receive(s
->vc
, buf
, size
, do_interrupt
);
1767 qemu_send_packet(s
->vc
, buf
, size
);
1771 static int rtl8139_transmit_one(RTL8139State
*s
, int descriptor
)
1773 if (!rtl8139_transmitter_enabled(s
))
1775 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1780 if (s
->TxStatus
[descriptor
] & TxHostOwns
)
1782 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1783 descriptor
, s
->TxStatus
[descriptor
]));
1787 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor
));
1789 int txsize
= s
->TxStatus
[descriptor
] & 0x1fff;
1790 uint8_t txbuffer
[0x2000];
1792 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1793 txsize
, s
->TxAddr
[descriptor
]));
1795 cpu_physical_memory_read(s
->TxAddr
[descriptor
], txbuffer
, txsize
);
1797 /* Mark descriptor as transferred */
1798 s
->TxStatus
[descriptor
] |= TxHostOwns
;
1799 s
->TxStatus
[descriptor
] |= TxStatOK
;
1801 rtl8139_transfer_frame(s
, txbuffer
, txsize
, 0);
1803 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize
, descriptor
));
1805 /* update interrupt */
1806 s
->IntrStatus
|= TxOK
;
1807 rtl8139_update_irq(s
);
1812 /* structures and macros for task offloading */
1813 typedef struct ip_header
1815 uint8_t ip_ver_len
; /* version and header length */
1816 uint8_t ip_tos
; /* type of service */
1817 uint16_t ip_len
; /* total length */
1818 uint16_t ip_id
; /* identification */
1819 uint16_t ip_off
; /* fragment offset field */
1820 uint8_t ip_ttl
; /* time to live */
1821 uint8_t ip_p
; /* protocol */
1822 uint16_t ip_sum
; /* checksum */
1823 uint32_t ip_src
,ip_dst
; /* source and dest address */
1826 #define IP_HEADER_VERSION_4 4
1827 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1828 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1830 typedef struct tcp_header
1832 uint16_t th_sport
; /* source port */
1833 uint16_t th_dport
; /* destination port */
1834 uint32_t th_seq
; /* sequence number */
1835 uint32_t th_ack
; /* acknowledgement number */
1836 uint16_t th_offset_flags
; /* data offset, reserved 6 bits, TCP protocol flags */
1837 uint16_t th_win
; /* window */
1838 uint16_t th_sum
; /* checksum */
1839 uint16_t th_urp
; /* urgent pointer */
1842 typedef struct udp_header
1844 uint16_t uh_sport
; /* source port */
1845 uint16_t uh_dport
; /* destination port */
1846 uint16_t uh_ulen
; /* udp length */
1847 uint16_t uh_sum
; /* udp checksum */
1850 typedef struct ip_pseudo_header
1856 uint16_t ip_payload
;
1859 #define IP_PROTO_TCP 6
1860 #define IP_PROTO_UDP 17
1862 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1863 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1864 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1866 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1868 #define TCP_FLAG_FIN 0x01
1869 #define TCP_FLAG_PUSH 0x08
1871 /* produces ones' complement sum of data */
1872 static uint16_t ones_complement_sum(uint8_t *data
, size_t len
)
1874 uint32_t result
= 0;
1876 for (; len
> 1; data
+=2, len
-=2)
1878 result
+= *(uint16_t*)data
;
1881 /* add the remainder byte */
1884 uint8_t odd
[2] = {*data
, 0};
1885 result
+= *(uint16_t*)odd
;
1889 result
= (result
& 0xffff) + (result
>> 16);
1894 static uint16_t ip_checksum(void *data
, size_t len
)
1896 return ~ones_complement_sum((uint8_t*)data
, len
);
1899 static int rtl8139_cplus_transmit_one(RTL8139State
*s
)
1901 if (!rtl8139_transmitter_enabled(s
))
1903 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
1907 if (!rtl8139_cp_transmitter_enabled(s
))
1909 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
1913 int descriptor
= s
->currCPlusTxDesc
;
1915 target_phys_addr_t cplus_tx_ring_desc
=
1916 rtl8139_addr64(s
->TxAddr
[0], s
->TxAddr
[1]);
1918 /* Normal priority ring */
1919 cplus_tx_ring_desc
+= 16 * descriptor
;
1921 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1922 descriptor
, s
->TxAddr
[1], s
->TxAddr
[0], cplus_tx_ring_desc
));
1924 uint32_t val
, txdw0
,txdw1
,txbufLO
,txbufHI
;
1926 cpu_physical_memory_read(cplus_tx_ring_desc
, (uint8_t *)&val
, 4);
1927 txdw0
= le32_to_cpu(val
);
1928 cpu_physical_memory_read(cplus_tx_ring_desc
+4, (uint8_t *)&val
, 4);
1929 txdw1
= le32_to_cpu(val
);
1930 cpu_physical_memory_read(cplus_tx_ring_desc
+8, (uint8_t *)&val
, 4);
1931 txbufLO
= le32_to_cpu(val
);
1932 cpu_physical_memory_read(cplus_tx_ring_desc
+12, (uint8_t *)&val
, 4);
1933 txbufHI
= le32_to_cpu(val
);
1935 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
1937 txdw0
, txdw1
, txbufLO
, txbufHI
));
1939 /* w0 ownership flag */
1940 #define CP_TX_OWN (1<<31)
1941 /* w0 end of ring flag */
1942 #define CP_TX_EOR (1<<30)
1943 /* first segment of received packet flag */
1944 #define CP_TX_FS (1<<29)
1945 /* last segment of received packet flag */
1946 #define CP_TX_LS (1<<28)
1947 /* large send packet flag */
1948 #define CP_TX_LGSEN (1<<27)
1949 /* large send MSS mask, bits 16...25 */
1950 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1952 /* IP checksum offload flag */
1953 #define CP_TX_IPCS (1<<18)
1954 /* UDP checksum offload flag */
1955 #define CP_TX_UDPCS (1<<17)
1956 /* TCP checksum offload flag */
1957 #define CP_TX_TCPCS (1<<16)
1959 /* w0 bits 0...15 : buffer size */
1960 #define CP_TX_BUFFER_SIZE (1<<16)
1961 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1962 /* w1 tag available flag */
1963 #define CP_RX_TAGC (1<<17)
1964 /* w1 bits 0...15 : VLAN tag */
1965 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1966 /* w2 low 32bit of Rx buffer ptr */
1967 /* w3 high 32bit of Rx buffer ptr */
1969 /* set after transmission */
1970 /* FIFO underrun flag */
1971 #define CP_TX_STATUS_UNF (1<<25)
1972 /* transmit error summary flag, valid if set any of three below */
1973 #define CP_TX_STATUS_TES (1<<23)
1974 /* out-of-window collision flag */
1975 #define CP_TX_STATUS_OWC (1<<22)
1976 /* link failure flag */
1977 #define CP_TX_STATUS_LNKF (1<<21)
1978 /* excessive collisions flag */
1979 #define CP_TX_STATUS_EXC (1<<20)
1981 if (!(txdw0
& CP_TX_OWN
))
1983 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor
));
1987 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor
));
1989 if (txdw0
& CP_TX_FS
)
1991 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor
));
1993 /* reset internal buffer offset */
1994 s
->cplus_txbuffer_offset
= 0;
1997 int txsize
= txdw0
& CP_TX_BUFFER_SIZE_MASK
;
1998 target_phys_addr_t tx_addr
= rtl8139_addr64(txbufLO
, txbufHI
);
2000 /* make sure we have enough space to assemble the packet */
2001 if (!s
->cplus_txbuffer
)
2003 s
->cplus_txbuffer_len
= CP_TX_BUFFER_SIZE
;
2004 s
->cplus_txbuffer
= malloc(s
->cplus_txbuffer_len
);
2005 s
->cplus_txbuffer_offset
= 0;
2007 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s
->cplus_txbuffer_len
));
2010 while (s
->cplus_txbuffer
&& s
->cplus_txbuffer_offset
+ txsize
>= s
->cplus_txbuffer_len
)
2012 s
->cplus_txbuffer_len
+= CP_TX_BUFFER_SIZE
;
2013 s
->cplus_txbuffer
= qemu_realloc(s
->cplus_txbuffer
, s
->cplus_txbuffer_len
);
2015 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s
->cplus_txbuffer_len
));
2018 if (!s
->cplus_txbuffer
)
2022 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s
->cplus_txbuffer_len
));
2024 /* update tally counter */
2025 ++s
->tally_counters
.TxERR
;
2026 ++s
->tally_counters
.TxAbt
;
2031 /* append more data to the packet */
2033 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64
" to offset %d\n",
2034 txsize
, (uint64_t)tx_addr
, s
->cplus_txbuffer_offset
));
2036 cpu_physical_memory_read(tx_addr
, s
->cplus_txbuffer
+ s
->cplus_txbuffer_offset
, txsize
);
2037 s
->cplus_txbuffer_offset
+= txsize
;
2039 /* seek to next Rx descriptor */
2040 if (txdw0
& CP_TX_EOR
)
2042 s
->currCPlusTxDesc
= 0;
2046 ++s
->currCPlusTxDesc
;
2047 if (s
->currCPlusTxDesc
>= 64)
2048 s
->currCPlusTxDesc
= 0;
2051 /* transfer ownership to target */
2052 txdw0
&= ~CP_RX_OWN
;
2054 /* reset error indicator bits */
2055 txdw0
&= ~CP_TX_STATUS_UNF
;
2056 txdw0
&= ~CP_TX_STATUS_TES
;
2057 txdw0
&= ~CP_TX_STATUS_OWC
;
2058 txdw0
&= ~CP_TX_STATUS_LNKF
;
2059 txdw0
&= ~CP_TX_STATUS_EXC
;
2061 /* update ring data */
2062 val
= cpu_to_le32(txdw0
);
2063 cpu_physical_memory_write(cplus_tx_ring_desc
, (uint8_t *)&val
, 4);
2064 // val = cpu_to_le32(txdw1);
2065 // cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2067 /* Now decide if descriptor being processed is holding the last segment of packet */
2068 if (txdw0
& CP_TX_LS
)
2070 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor
));
2072 /* can transfer fully assembled packet */
2074 uint8_t *saved_buffer
= s
->cplus_txbuffer
;
2075 int saved_size
= s
->cplus_txbuffer_offset
;
2076 int saved_buffer_len
= s
->cplus_txbuffer_len
;
2078 /* reset the card space to protect from recursive call */
2079 s
->cplus_txbuffer
= NULL
;
2080 s
->cplus_txbuffer_offset
= 0;
2081 s
->cplus_txbuffer_len
= 0;
2083 if (txdw0
& (CP_TX_IPCS
| CP_TX_UDPCS
| CP_TX_TCPCS
| CP_TX_LGSEN
))
2085 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2087 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2089 #define ETH_MTU 1500
2091 /* ip packet header */
2092 ip_header
*ip
= NULL
;
2094 uint8_t ip_protocol
= 0;
2095 uint16_t ip_data_len
= 0;
2097 uint8_t *eth_payload_data
= NULL
;
2098 size_t eth_payload_len
= 0;
2100 int proto
= be16_to_cpu(*(uint16_t *)(saved_buffer
+ 12));
2101 if (proto
== ETH_P_IP
)
2103 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2106 eth_payload_data
= saved_buffer
+ ETH_HLEN
;
2107 eth_payload_len
= saved_size
- ETH_HLEN
;
2109 ip
= (ip_header
*)eth_payload_data
;
2111 if (IP_HEADER_VERSION(ip
) != IP_HEADER_VERSION_4
) {
2112 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip
), IP_HEADER_VERSION_4
));
2115 hlen
= IP_HEADER_LENGTH(ip
);
2116 ip_protocol
= ip
->ip_p
;
2117 ip_data_len
= be16_to_cpu(ip
->ip_len
) - hlen
;
2123 if (txdw0
& CP_TX_IPCS
)
2125 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2127 if (hlen
<sizeof(ip_header
) || hlen
>eth_payload_len
) {/* min header length */
2128 /* bad packet header len */
2129 /* or packet too short */
2134 ip
->ip_sum
= ip_checksum(ip
, hlen
);
2135 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen
, ip
->ip_sum
));
2139 if ((txdw0
& CP_TX_LGSEN
) && ip_protocol
== IP_PROTO_TCP
)
2141 #if defined (DEBUG_RTL8139)
2142 int large_send_mss
= (txdw0
>> 16) & CP_TC_LGSEN_MSS_MASK
;
2144 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2145 ETH_MTU
, ip_data_len
, saved_size
- ETH_HLEN
, large_send_mss
));
2147 int tcp_send_offset
= 0;
2150 /* maximum IP header length is 60 bytes */
2151 uint8_t saved_ip_header
[60];
2153 /* save IP header template; data area is used in tcp checksum calculation */
2154 memcpy(saved_ip_header
, eth_payload_data
, hlen
);
2156 /* a placeholder for checksum calculation routine in tcp case */
2157 uint8_t *data_to_checksum
= eth_payload_data
+ hlen
- 12;
2158 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2160 /* pointer to TCP header */
2161 tcp_header
*p_tcp_hdr
= (tcp_header
*)(eth_payload_data
+ hlen
);
2163 int tcp_hlen
= TCP_HEADER_DATA_OFFSET(p_tcp_hdr
);
2165 /* ETH_MTU = ip header len + tcp header len + payload */
2166 int tcp_data_len
= ip_data_len
- tcp_hlen
;
2167 int tcp_chunk_size
= ETH_MTU
- hlen
- tcp_hlen
;
2169 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2170 ip_data_len
, tcp_hlen
, tcp_data_len
, tcp_chunk_size
));
2172 /* note the cycle below overwrites IP header data,
2173 but restores it from saved_ip_header before sending packet */
2175 int is_last_frame
= 0;
2177 for (tcp_send_offset
= 0; tcp_send_offset
< tcp_data_len
; tcp_send_offset
+= tcp_chunk_size
)
2179 uint16_t chunk_size
= tcp_chunk_size
;
2181 /* check if this is the last frame */
2182 if (tcp_send_offset
+ tcp_chunk_size
>= tcp_data_len
)
2185 chunk_size
= tcp_data_len
- tcp_send_offset
;
2188 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr
->th_seq
)));
2190 /* add 4 TCP pseudoheader fields */
2191 /* copy IP source and destination fields */
2192 memcpy(data_to_checksum
, saved_ip_header
+ 12, 8);
2194 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen
+ chunk_size
));
2196 if (tcp_send_offset
)
2198 memcpy((uint8_t*)p_tcp_hdr
+ tcp_hlen
, (uint8_t*)p_tcp_hdr
+ tcp_hlen
+ tcp_send_offset
, chunk_size
);
2201 /* keep PUSH and FIN flags only for the last frame */
2204 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr
, TCP_FLAG_PUSH
|TCP_FLAG_FIN
);
2207 /* recalculate TCP checksum */
2208 ip_pseudo_header
*p_tcpip_hdr
= (ip_pseudo_header
*)data_to_checksum
;
2209 p_tcpip_hdr
->zeros
= 0;
2210 p_tcpip_hdr
->ip_proto
= IP_PROTO_TCP
;
2211 p_tcpip_hdr
->ip_payload
= cpu_to_be16(tcp_hlen
+ chunk_size
);
2213 p_tcp_hdr
->th_sum
= 0;
2215 int tcp_checksum
= ip_checksum(data_to_checksum
, tcp_hlen
+ chunk_size
+ 12);
2216 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum
));
2218 p_tcp_hdr
->th_sum
= tcp_checksum
;
2220 /* restore IP header */
2221 memcpy(eth_payload_data
, saved_ip_header
, hlen
);
2223 /* set IP data length and recalculate IP checksum */
2224 ip
->ip_len
= cpu_to_be16(hlen
+ tcp_hlen
+ chunk_size
);
2226 /* increment IP id for subsequent frames */
2227 ip
->ip_id
= cpu_to_be16(tcp_send_offset
/tcp_chunk_size
+ be16_to_cpu(ip
->ip_id
));
2230 ip
->ip_sum
= ip_checksum(eth_payload_data
, hlen
);
2231 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen
, ip
->ip_sum
));
2233 int tso_send_size
= ETH_HLEN
+ hlen
+ tcp_hlen
+ chunk_size
;
2234 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size
));
2235 rtl8139_transfer_frame(s
, saved_buffer
, tso_send_size
, 0);
2237 /* add transferred count to TCP sequence number */
2238 p_tcp_hdr
->th_seq
= cpu_to_be32(chunk_size
+ be32_to_cpu(p_tcp_hdr
->th_seq
));
2242 /* Stop sending this frame */
2245 else if (txdw0
& (CP_TX_TCPCS
|CP_TX_UDPCS
))
2247 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2249 /* maximum IP header length is 60 bytes */
2250 uint8_t saved_ip_header
[60];
2251 memcpy(saved_ip_header
, eth_payload_data
, hlen
);
2253 uint8_t *data_to_checksum
= eth_payload_data
+ hlen
- 12;
2254 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2256 /* add 4 TCP pseudoheader fields */
2257 /* copy IP source and destination fields */
2258 memcpy(data_to_checksum
, saved_ip_header
+ 12, 8);
2260 if ((txdw0
& CP_TX_TCPCS
) && ip_protocol
== IP_PROTO_TCP
)
2262 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len
));
2264 ip_pseudo_header
*p_tcpip_hdr
= (ip_pseudo_header
*)data_to_checksum
;
2265 p_tcpip_hdr
->zeros
= 0;
2266 p_tcpip_hdr
->ip_proto
= IP_PROTO_TCP
;
2267 p_tcpip_hdr
->ip_payload
= cpu_to_be16(ip_data_len
);
2269 tcp_header
* p_tcp_hdr
= (tcp_header
*) (data_to_checksum
+12);
2271 p_tcp_hdr
->th_sum
= 0;
2273 int tcp_checksum
= ip_checksum(data_to_checksum
, ip_data_len
+ 12);
2274 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum
));
2276 p_tcp_hdr
->th_sum
= tcp_checksum
;
2278 else if ((txdw0
& CP_TX_UDPCS
) && ip_protocol
== IP_PROTO_UDP
)
2280 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len
));
2282 ip_pseudo_header
*p_udpip_hdr
= (ip_pseudo_header
*)data_to_checksum
;
2283 p_udpip_hdr
->zeros
= 0;
2284 p_udpip_hdr
->ip_proto
= IP_PROTO_UDP
;
2285 p_udpip_hdr
->ip_payload
= cpu_to_be16(ip_data_len
);
2287 udp_header
*p_udp_hdr
= (udp_header
*) (data_to_checksum
+12);
2289 p_udp_hdr
->uh_sum
= 0;
2291 int udp_checksum
= ip_checksum(data_to_checksum
, ip_data_len
+ 12);
2292 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum
));
2294 p_udp_hdr
->uh_sum
= udp_checksum
;
2297 /* restore IP header */
2298 memcpy(eth_payload_data
, saved_ip_header
, hlen
);
2303 /* update tally counter */
2304 ++s
->tally_counters
.TxOk
;
2306 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size
));
2308 rtl8139_transfer_frame(s
, saved_buffer
, saved_size
, 1);
2310 /* restore card space if there was no recursion and reset offset */
2311 if (!s
->cplus_txbuffer
)
2313 s
->cplus_txbuffer
= saved_buffer
;
2314 s
->cplus_txbuffer_len
= saved_buffer_len
;
2315 s
->cplus_txbuffer_offset
= 0;
2324 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
2330 static void rtl8139_cplus_transmit(RTL8139State
*s
)
2334 while (rtl8139_cplus_transmit_one(s
))
2339 /* Mark transfer completed */
2342 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2343 s
->currCPlusTxDesc
));
2347 /* update interrupt status */
2348 s
->IntrStatus
|= TxOK
;
2349 rtl8139_update_irq(s
);
2353 static void rtl8139_transmit(RTL8139State
*s
)
2355 int descriptor
= s
->currTxDesc
, txcount
= 0;
2358 if (rtl8139_transmit_one(s
, descriptor
))
2365 /* Mark transfer completed */
2368 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s
->currTxDesc
));
2372 static void rtl8139_TxStatus_write(RTL8139State
*s
, uint32_t txRegOffset
, uint32_t val
)
2375 int descriptor
= txRegOffset
/4;
2377 /* handle C+ transmit mode register configuration */
2379 if (s
->cplus_enabled
)
2381 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset
, val
, descriptor
));
2383 /* handle Dump Tally Counters command */
2384 s
->TxStatus
[descriptor
] = val
;
2386 if (descriptor
== 0 && (val
& 0x8))
2388 target_phys_addr_t tc_addr
= rtl8139_addr64(s
->TxStatus
[0] & ~0x3f, s
->TxStatus
[1]);
2390 /* dump tally counters to specified memory location */
2391 RTL8139TallyCounters_physical_memory_write( tc_addr
, &s
->tally_counters
);
2393 /* mark dump completed */
2394 s
->TxStatus
[0] &= ~0x8;
2400 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset
, val
, descriptor
));
2402 /* mask only reserved bits */
2403 val
&= ~0xff00c000; /* these bits are reset on write */
2404 val
= SET_MASKED(val
, 0x00c00000, s
->TxStatus
[descriptor
]);
2406 s
->TxStatus
[descriptor
] = val
;
2408 /* attempt to start transmission */
2409 rtl8139_transmit(s
);
2412 static uint32_t rtl8139_TxStatus_read(RTL8139State
*s
, uint32_t txRegOffset
)
2414 uint32_t ret
= s
->TxStatus
[txRegOffset
/4];
2416 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset
, ret
));
2421 static uint16_t rtl8139_TSAD_read(RTL8139State
*s
)
2425 /* Simulate TSAD, it is read only anyway */
2427 ret
= ((s
->TxStatus
[3] & TxStatOK
)?TSAD_TOK3
:0)
2428 |((s
->TxStatus
[2] & TxStatOK
)?TSAD_TOK2
:0)
2429 |((s
->TxStatus
[1] & TxStatOK
)?TSAD_TOK1
:0)
2430 |((s
->TxStatus
[0] & TxStatOK
)?TSAD_TOK0
:0)
2432 |((s
->TxStatus
[3] & TxUnderrun
)?TSAD_TUN3
:0)
2433 |((s
->TxStatus
[2] & TxUnderrun
)?TSAD_TUN2
:0)
2434 |((s
->TxStatus
[1] & TxUnderrun
)?TSAD_TUN1
:0)
2435 |((s
->TxStatus
[0] & TxUnderrun
)?TSAD_TUN0
:0)
2437 |((s
->TxStatus
[3] & TxAborted
)?TSAD_TABT3
:0)
2438 |((s
->TxStatus
[2] & TxAborted
)?TSAD_TABT2
:0)
2439 |((s
->TxStatus
[1] & TxAborted
)?TSAD_TABT1
:0)
2440 |((s
->TxStatus
[0] & TxAborted
)?TSAD_TABT0
:0)
2442 |((s
->TxStatus
[3] & TxHostOwns
)?TSAD_OWN3
:0)
2443 |((s
->TxStatus
[2] & TxHostOwns
)?TSAD_OWN2
:0)
2444 |((s
->TxStatus
[1] & TxHostOwns
)?TSAD_OWN1
:0)
2445 |((s
->TxStatus
[0] & TxHostOwns
)?TSAD_OWN0
:0) ;
2448 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret
));
2453 static uint16_t rtl8139_CSCR_read(RTL8139State
*s
)
2455 uint16_t ret
= s
->CSCR
;
2457 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret
));
2462 static void rtl8139_TxAddr_write(RTL8139State
*s
, uint32_t txAddrOffset
, uint32_t val
)
2464 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset
, val
));
2466 s
->TxAddr
[txAddrOffset
/4] = val
;
2469 static uint32_t rtl8139_TxAddr_read(RTL8139State
*s
, uint32_t txAddrOffset
)
2471 uint32_t ret
= s
->TxAddr
[txAddrOffset
/4];
2473 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset
, ret
));
2478 static void rtl8139_RxBufPtr_write(RTL8139State
*s
, uint32_t val
)
2480 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val
));
2482 /* this value is off by 16 */
2483 s
->RxBufPtr
= MOD2(val
+ 0x10, s
->RxBufferSize
);
2485 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2486 s
->RxBufferSize
, s
->RxBufAddr
, s
->RxBufPtr
));
2489 static uint32_t rtl8139_RxBufPtr_read(RTL8139State
*s
)
2491 /* this value is off by 16 */
2492 uint32_t ret
= s
->RxBufPtr
- 0x10;
2494 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret
));
2499 static uint32_t rtl8139_RxBufAddr_read(RTL8139State
*s
)
2501 /* this value is NOT off by 16 */
2502 uint32_t ret
= s
->RxBufAddr
;
2504 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret
));
2509 static void rtl8139_RxBuf_write(RTL8139State
*s
, uint32_t val
)
2511 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val
));
2515 /* may need to reset rxring here */
2518 static uint32_t rtl8139_RxBuf_read(RTL8139State
*s
)
2520 uint32_t ret
= s
->RxBuf
;
2522 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret
));
2527 static void rtl8139_IntrMask_write(RTL8139State
*s
, uint32_t val
)
2529 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val
));
2531 /* mask unwriteable bits */
2532 val
= SET_MASKED(val
, 0x1e00, s
->IntrMask
);
2536 rtl8139_update_irq(s
);
2539 static uint32_t rtl8139_IntrMask_read(RTL8139State
*s
)
2541 uint32_t ret
= s
->IntrMask
;
2543 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret
));
2548 static void rtl8139_IntrStatus_write(RTL8139State
*s
, uint32_t val
)
2550 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val
));
2554 /* writing to ISR has no effect */
2559 uint16_t newStatus
= s
->IntrStatus
& ~val
;
2561 /* mask unwriteable bits */
2562 newStatus
= SET_MASKED(newStatus
, 0x1e00, s
->IntrStatus
);
2564 /* writing 1 to interrupt status register bit clears it */
2566 rtl8139_update_irq(s
);
2568 s
->IntrStatus
= newStatus
;
2569 rtl8139_update_irq(s
);
2573 static uint32_t rtl8139_IntrStatus_read(RTL8139State
*s
)
2575 uint32_t ret
= s
->IntrStatus
;
2577 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret
));
2581 /* reading ISR clears all interrupts */
2584 rtl8139_update_irq(s
);
2591 static void rtl8139_MultiIntr_write(RTL8139State
*s
, uint32_t val
)
2593 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val
));
2595 /* mask unwriteable bits */
2596 val
= SET_MASKED(val
, 0xf000, s
->MultiIntr
);
2601 static uint32_t rtl8139_MultiIntr_read(RTL8139State
*s
)
2603 uint32_t ret
= s
->MultiIntr
;
2605 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret
));
2610 static void rtl8139_io_writeb(void *opaque
, uint8_t addr
, uint32_t val
)
2612 RTL8139State
*s
= opaque
;
2618 case MAC0
... MAC0
+5:
2619 s
->phys
[addr
- MAC0
] = val
;
2621 case MAC0
+6 ... MAC0
+7:
2624 case MAR0
... MAR0
+7:
2625 s
->mult
[addr
- MAR0
] = val
;
2628 rtl8139_ChipCmd_write(s
, val
);
2631 rtl8139_Cfg9346_write(s
, val
);
2633 case TxConfig
: /* windows driver sometimes writes using byte-lenth call */
2634 rtl8139_TxConfig_writeb(s
, val
);
2637 rtl8139_Config0_write(s
, val
);
2640 rtl8139_Config1_write(s
, val
);
2643 rtl8139_Config3_write(s
, val
);
2646 rtl8139_Config4_write(s
, val
);
2649 rtl8139_Config5_write(s
, val
);
2653 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val
));
2657 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val
));
2660 s
->clock_enabled
= 1;
2662 else if (val
== 'H')
2664 s
->clock_enabled
= 0;
2669 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val
));
2674 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val
));
2677 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
2678 //rtl8139_cplus_transmit(s);
2682 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
2683 rtl8139_cplus_transmit(s
);
2689 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr
, val
));
2694 static void rtl8139_io_writew(void *opaque
, uint8_t addr
, uint32_t val
)
2696 RTL8139State
*s
= opaque
;
2703 rtl8139_IntrMask_write(s
, val
);
2707 rtl8139_IntrStatus_write(s
, val
);
2711 rtl8139_MultiIntr_write(s
, val
);
2715 rtl8139_RxBufPtr_write(s
, val
);
2719 rtl8139_BasicModeCtrl_write(s
, val
);
2721 case BasicModeStatus
:
2722 rtl8139_BasicModeStatus_write(s
, val
);
2725 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val
));
2726 s
->NWayAdvert
= val
;
2729 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val
));
2732 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val
));
2733 s
->NWayExpansion
= val
;
2737 rtl8139_CpCmd_write(s
, val
);
2741 rtl8139_IntrMitigate_write(s
, val
);
2745 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr
, val
));
2747 rtl8139_io_writeb(opaque
, addr
, val
& 0xff);
2748 rtl8139_io_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2753 static void rtl8139_io_writel(void *opaque
, uint8_t addr
, uint32_t val
)
2755 RTL8139State
*s
= opaque
;
2762 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
2767 rtl8139_TxConfig_write(s
, val
);
2771 rtl8139_RxConfig_write(s
, val
);
2774 case TxStatus0
... TxStatus0
+4*4-1:
2775 rtl8139_TxStatus_write(s
, addr
-TxStatus0
, val
);
2778 case TxAddr0
... TxAddr0
+4*4-1:
2779 rtl8139_TxAddr_write(s
, addr
-TxAddr0
, val
);
2783 rtl8139_RxBuf_write(s
, val
);
2787 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val
));
2788 s
->RxRingAddrLO
= val
;
2792 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val
));
2793 s
->RxRingAddrHI
= val
;
2797 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2799 s
->TCTR_base
= qemu_get_clock(vm_clock
);
2803 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val
));
2808 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr
, val
));
2809 rtl8139_io_writeb(opaque
, addr
, val
& 0xff);
2810 rtl8139_io_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2811 rtl8139_io_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2812 rtl8139_io_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2817 static uint32_t rtl8139_io_readb(void *opaque
, uint8_t addr
)
2819 RTL8139State
*s
= opaque
;
2826 case MAC0
... MAC0
+5:
2827 ret
= s
->phys
[addr
- MAC0
];
2829 case MAC0
+6 ... MAC0
+7:
2832 case MAR0
... MAR0
+7:
2833 ret
= s
->mult
[addr
- MAR0
];
2836 ret
= rtl8139_ChipCmd_read(s
);
2839 ret
= rtl8139_Cfg9346_read(s
);
2842 ret
= rtl8139_Config0_read(s
);
2845 ret
= rtl8139_Config1_read(s
);
2848 ret
= rtl8139_Config3_read(s
);
2851 ret
= rtl8139_Config4_read(s
);
2854 ret
= rtl8139_Config5_read(s
);
2859 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret
));
2863 ret
= s
->clock_enabled
;
2864 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret
));
2868 ret
= RTL8139_PCI_REVID
;
2869 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret
));
2874 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret
));
2877 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2878 ret
= s
->TxConfig
>> 24;
2879 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret
));
2883 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr
));
2891 static uint32_t rtl8139_io_readw(void *opaque
, uint8_t addr
)
2893 RTL8139State
*s
= opaque
;
2896 addr
&= 0xfe; /* mask lower bit */
2901 ret
= rtl8139_IntrMask_read(s
);
2905 ret
= rtl8139_IntrStatus_read(s
);
2909 ret
= rtl8139_MultiIntr_read(s
);
2913 ret
= rtl8139_RxBufPtr_read(s
);
2917 ret
= rtl8139_RxBufAddr_read(s
);
2921 ret
= rtl8139_BasicModeCtrl_read(s
);
2923 case BasicModeStatus
:
2924 ret
= rtl8139_BasicModeStatus_read(s
);
2927 ret
= s
->NWayAdvert
;
2928 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret
));
2932 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret
));
2935 ret
= s
->NWayExpansion
;
2936 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret
));
2940 ret
= rtl8139_CpCmd_read(s
);
2944 ret
= rtl8139_IntrMitigate_read(s
);
2948 ret
= rtl8139_TSAD_read(s
);
2952 ret
= rtl8139_CSCR_read(s
);
2956 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr
));
2958 ret
= rtl8139_io_readb(opaque
, addr
);
2959 ret
|= rtl8139_io_readb(opaque
, addr
+ 1) << 8;
2961 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr
, ret
));
2968 static uint32_t rtl8139_io_readl(void *opaque
, uint8_t addr
)
2970 RTL8139State
*s
= opaque
;
2973 addr
&= 0xfc; /* also mask low 2 bits */
2980 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret
));
2984 ret
= rtl8139_TxConfig_read(s
);
2988 ret
= rtl8139_RxConfig_read(s
);
2991 case TxStatus0
... TxStatus0
+4*4-1:
2992 ret
= rtl8139_TxStatus_read(s
, addr
-TxStatus0
);
2995 case TxAddr0
... TxAddr0
+4*4-1:
2996 ret
= rtl8139_TxAddr_read(s
, addr
-TxAddr0
);
3000 ret
= rtl8139_RxBuf_read(s
);
3004 ret
= s
->RxRingAddrLO
;
3005 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret
));
3009 ret
= s
->RxRingAddrHI
;
3010 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret
));
3015 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret
));
3020 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret
));
3024 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr
));
3026 ret
= rtl8139_io_readb(opaque
, addr
);
3027 ret
|= rtl8139_io_readb(opaque
, addr
+ 1) << 8;
3028 ret
|= rtl8139_io_readb(opaque
, addr
+ 2) << 16;
3029 ret
|= rtl8139_io_readb(opaque
, addr
+ 3) << 24;
3031 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr
, ret
));
3040 static void rtl8139_ioport_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
3042 rtl8139_io_writeb(opaque
, addr
& 0xFF, val
);
3045 static void rtl8139_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
3047 rtl8139_io_writew(opaque
, addr
& 0xFF, val
);
3050 static void rtl8139_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
3052 rtl8139_io_writel(opaque
, addr
& 0xFF, val
);
3055 static uint32_t rtl8139_ioport_readb(void *opaque
, uint32_t addr
)
3057 return rtl8139_io_readb(opaque
, addr
& 0xFF);
3060 static uint32_t rtl8139_ioport_readw(void *opaque
, uint32_t addr
)
3062 return rtl8139_io_readw(opaque
, addr
& 0xFF);
3065 static uint32_t rtl8139_ioport_readl(void *opaque
, uint32_t addr
)
3067 return rtl8139_io_readl(opaque
, addr
& 0xFF);
3072 static void rtl8139_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
3074 rtl8139_io_writeb(opaque
, addr
& 0xFF, val
);
3077 static void rtl8139_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
3079 #ifdef TARGET_WORDS_BIGENDIAN
3082 rtl8139_io_writew(opaque
, addr
& 0xFF, val
);
3085 static void rtl8139_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
3087 #ifdef TARGET_WORDS_BIGENDIAN
3090 rtl8139_io_writel(opaque
, addr
& 0xFF, val
);
3093 static uint32_t rtl8139_mmio_readb(void *opaque
, target_phys_addr_t addr
)
3095 return rtl8139_io_readb(opaque
, addr
& 0xFF);
3098 static uint32_t rtl8139_mmio_readw(void *opaque
, target_phys_addr_t addr
)
3100 uint32_t val
= rtl8139_io_readw(opaque
, addr
& 0xFF);
3101 #ifdef TARGET_WORDS_BIGENDIAN
3107 static uint32_t rtl8139_mmio_readl(void *opaque
, target_phys_addr_t addr
)
3109 uint32_t val
= rtl8139_io_readl(opaque
, addr
& 0xFF);
3110 #ifdef TARGET_WORDS_BIGENDIAN
3118 static void rtl8139_save(QEMUFile
* f
,void* opaque
)
3120 RTL8139State
* s
= opaque
;
3123 pci_device_save(&s
->dev
, f
);
3125 qemu_put_buffer(f
, s
->phys
, 6);
3126 qemu_put_buffer(f
, s
->mult
, 8);
3130 qemu_put_be32s(f
, &s
->TxStatus
[i
]); /* TxStatus0 */
3134 qemu_put_be32s(f
, &s
->TxAddr
[i
]); /* TxAddr0 */
3137 qemu_put_be32s(f
, &s
->RxBuf
); /* Receive buffer */
3138 qemu_put_be32s(f
, &s
->RxBufferSize
);/* internal variable, receive ring buffer size in C mode */
3139 qemu_put_be32s(f
, &s
->RxBufPtr
);
3140 qemu_put_be32s(f
, &s
->RxBufAddr
);
3142 qemu_put_be16s(f
, &s
->IntrStatus
);
3143 qemu_put_be16s(f
, &s
->IntrMask
);
3145 qemu_put_be32s(f
, &s
->TxConfig
);
3146 qemu_put_be32s(f
, &s
->RxConfig
);
3147 qemu_put_be32s(f
, &s
->RxMissed
);
3148 qemu_put_be16s(f
, &s
->CSCR
);
3150 qemu_put_8s(f
, &s
->Cfg9346
);
3151 qemu_put_8s(f
, &s
->Config0
);
3152 qemu_put_8s(f
, &s
->Config1
);
3153 qemu_put_8s(f
, &s
->Config3
);
3154 qemu_put_8s(f
, &s
->Config4
);
3155 qemu_put_8s(f
, &s
->Config5
);
3157 qemu_put_8s(f
, &s
->clock_enabled
);
3158 qemu_put_8s(f
, &s
->bChipCmdState
);
3160 qemu_put_be16s(f
, &s
->MultiIntr
);
3162 qemu_put_be16s(f
, &s
->BasicModeCtrl
);
3163 qemu_put_be16s(f
, &s
->BasicModeStatus
);
3164 qemu_put_be16s(f
, &s
->NWayAdvert
);
3165 qemu_put_be16s(f
, &s
->NWayLPAR
);
3166 qemu_put_be16s(f
, &s
->NWayExpansion
);
3168 qemu_put_be16s(f
, &s
->CpCmd
);
3169 qemu_put_8s(f
, &s
->TxThresh
);
3172 qemu_put_be32s(f
, &i
); /* unused. */
3173 qemu_put_buffer(f
, s
->conf
.macaddr
.a
, 6);
3174 qemu_put_be32(f
, s
->rtl8139_mmio_io_addr
);
3176 qemu_put_be32s(f
, &s
->currTxDesc
);
3177 qemu_put_be32s(f
, &s
->currCPlusRxDesc
);
3178 qemu_put_be32s(f
, &s
->currCPlusTxDesc
);
3179 qemu_put_be32s(f
, &s
->RxRingAddrLO
);
3180 qemu_put_be32s(f
, &s
->RxRingAddrHI
);
3182 for (i
=0; i
<EEPROM_9346_SIZE
; ++i
)
3184 qemu_put_be16s(f
, &s
->eeprom
.contents
[i
]);
3186 qemu_put_be32(f
, s
->eeprom
.mode
);
3187 qemu_put_be32s(f
, &s
->eeprom
.tick
);
3188 qemu_put_8s(f
, &s
->eeprom
.address
);
3189 qemu_put_be16s(f
, &s
->eeprom
.input
);
3190 qemu_put_be16s(f
, &s
->eeprom
.output
);
3192 qemu_put_8s(f
, &s
->eeprom
.eecs
);
3193 qemu_put_8s(f
, &s
->eeprom
.eesk
);
3194 qemu_put_8s(f
, &s
->eeprom
.eedi
);
3195 qemu_put_8s(f
, &s
->eeprom
.eedo
);
3197 qemu_put_be32s(f
, &s
->TCTR
);
3198 qemu_put_be32s(f
, &s
->TimerInt
);
3199 qemu_put_be64(f
, s
->TCTR_base
);
3201 RTL8139TallyCounters_save(f
, &s
->tally_counters
);
3203 qemu_put_be32s(f
, &s
->cplus_enabled
);
3206 static int rtl8139_load(QEMUFile
* f
,void* opaque
,int version_id
)
3208 RTL8139State
* s
= opaque
;
3212 /* just 2 versions for now */
3216 if (version_id
>= 3) {
3217 ret
= pci_device_load(&s
->dev
, f
);
3222 /* saved since version 1 */
3223 qemu_get_buffer(f
, s
->phys
, 6);
3224 qemu_get_buffer(f
, s
->mult
, 8);
3228 qemu_get_be32s(f
, &s
->TxStatus
[i
]); /* TxStatus0 */
3232 qemu_get_be32s(f
, &s
->TxAddr
[i
]); /* TxAddr0 */
3235 qemu_get_be32s(f
, &s
->RxBuf
); /* Receive buffer */
3236 qemu_get_be32s(f
, &s
->RxBufferSize
);/* internal variable, receive ring buffer size in C mode */
3237 qemu_get_be32s(f
, &s
->RxBufPtr
);
3238 qemu_get_be32s(f
, &s
->RxBufAddr
);
3240 qemu_get_be16s(f
, &s
->IntrStatus
);
3241 qemu_get_be16s(f
, &s
->IntrMask
);
3243 qemu_get_be32s(f
, &s
->TxConfig
);
3244 qemu_get_be32s(f
, &s
->RxConfig
);
3245 qemu_get_be32s(f
, &s
->RxMissed
);
3246 qemu_get_be16s(f
, &s
->CSCR
);
3248 qemu_get_8s(f
, &s
->Cfg9346
);
3249 qemu_get_8s(f
, &s
->Config0
);
3250 qemu_get_8s(f
, &s
->Config1
);
3251 qemu_get_8s(f
, &s
->Config3
);
3252 qemu_get_8s(f
, &s
->Config4
);
3253 qemu_get_8s(f
, &s
->Config5
);
3255 qemu_get_8s(f
, &s
->clock_enabled
);
3256 qemu_get_8s(f
, &s
->bChipCmdState
);
3258 qemu_get_be16s(f
, &s
->MultiIntr
);
3260 qemu_get_be16s(f
, &s
->BasicModeCtrl
);
3261 qemu_get_be16s(f
, &s
->BasicModeStatus
);
3262 qemu_get_be16s(f
, &s
->NWayAdvert
);
3263 qemu_get_be16s(f
, &s
->NWayLPAR
);
3264 qemu_get_be16s(f
, &s
->NWayExpansion
);
3266 qemu_get_be16s(f
, &s
->CpCmd
);
3267 qemu_get_8s(f
, &s
->TxThresh
);
3269 qemu_get_be32s(f
, &i
); /* unused. */
3270 qemu_get_buffer(f
, s
->conf
.macaddr
.a
, 6);
3271 s
->rtl8139_mmio_io_addr
=qemu_get_be32(f
);
3273 qemu_get_be32s(f
, &s
->currTxDesc
);
3274 qemu_get_be32s(f
, &s
->currCPlusRxDesc
);
3275 qemu_get_be32s(f
, &s
->currCPlusTxDesc
);
3276 qemu_get_be32s(f
, &s
->RxRingAddrLO
);
3277 qemu_get_be32s(f
, &s
->RxRingAddrHI
);
3279 for (i
=0; i
<EEPROM_9346_SIZE
; ++i
)
3281 qemu_get_be16s(f
, &s
->eeprom
.contents
[i
]);
3283 s
->eeprom
.mode
=qemu_get_be32(f
);
3284 qemu_get_be32s(f
, &s
->eeprom
.tick
);
3285 qemu_get_8s(f
, &s
->eeprom
.address
);
3286 qemu_get_be16s(f
, &s
->eeprom
.input
);
3287 qemu_get_be16s(f
, &s
->eeprom
.output
);
3289 qemu_get_8s(f
, &s
->eeprom
.eecs
);
3290 qemu_get_8s(f
, &s
->eeprom
.eesk
);
3291 qemu_get_8s(f
, &s
->eeprom
.eedi
);
3292 qemu_get_8s(f
, &s
->eeprom
.eedo
);
3294 /* saved since version 2 */
3295 if (version_id
>= 2)
3297 qemu_get_be32s(f
, &s
->TCTR
);
3298 qemu_get_be32s(f
, &s
->TimerInt
);
3299 s
->TCTR_base
=qemu_get_be64(f
);
3301 RTL8139TallyCounters_load(f
, &s
->tally_counters
);
3305 /* not saved, use default */
3310 RTL8139TallyCounters_clear(&s
->tally_counters
);
3313 if (version_id
>= 4) {
3314 qemu_get_be32s(f
, &s
->cplus_enabled
);
3316 s
->cplus_enabled
= s
->CpCmd
!= 0;
3322 /***********************************************************/
3323 /* PCI RTL8139 definitions */
3325 static void rtl8139_mmio_map(PCIDevice
*pci_dev
, int region_num
,
3326 uint32_t addr
, uint32_t size
, int type
)
3328 RTL8139State
*s
= DO_UPCAST(RTL8139State
, dev
, pci_dev
);
3330 cpu_register_physical_memory(addr
+ 0, 0x100, s
->rtl8139_mmio_io_addr
);
3333 static void rtl8139_ioport_map(PCIDevice
*pci_dev
, int region_num
,
3334 uint32_t addr
, uint32_t size
, int type
)
3336 RTL8139State
*s
= DO_UPCAST(RTL8139State
, dev
, pci_dev
);
3338 register_ioport_write(addr
, 0x100, 1, rtl8139_ioport_writeb
, s
);
3339 register_ioport_read( addr
, 0x100, 1, rtl8139_ioport_readb
, s
);
3341 register_ioport_write(addr
, 0x100, 2, rtl8139_ioport_writew
, s
);
3342 register_ioport_read( addr
, 0x100, 2, rtl8139_ioport_readw
, s
);
3344 register_ioport_write(addr
, 0x100, 4, rtl8139_ioport_writel
, s
);
3345 register_ioport_read( addr
, 0x100, 4, rtl8139_ioport_readl
, s
);
3348 static CPUReadMemoryFunc
* const rtl8139_mmio_read
[3] = {
3354 static CPUWriteMemoryFunc
* const rtl8139_mmio_write
[3] = {
3355 rtl8139_mmio_writeb
,
3356 rtl8139_mmio_writew
,
3357 rtl8139_mmio_writel
,
3360 static inline int64_t rtl8139_get_next_tctr_time(RTL8139State
*s
, int64_t current_time
)
3362 int64_t next_time
= current_time
+
3363 muldiv64(1, get_ticks_per_sec(), PCI_FREQUENCY
);
3364 if (next_time
<= current_time
)
3365 next_time
= current_time
+ 1;
3369 #ifdef RTL8139_ONBOARD_TIMER
3370 static void rtl8139_timer(void *opaque
)
3372 RTL8139State
*s
= opaque
;
3379 if (!s
->clock_enabled
)
3381 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3385 curr_time
= qemu_get_clock(vm_clock
);
3387 curr_tick
= muldiv64(curr_time
- s
->TCTR_base
, PCI_FREQUENCY
,
3388 get_ticks_per_sec());
3390 if (s
->TimerInt
&& curr_tick
>= s
->TimerInt
)
3392 if (s
->TCTR
< s
->TimerInt
|| curr_tick
< s
->TCTR
)
3398 s
->TCTR
= curr_tick
;
3400 // DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR));
3404 DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s
->TCTR
));
3405 s
->IntrStatus
|= PCSTimeout
;
3406 rtl8139_update_irq(s
);
3409 qemu_mod_timer(s
->timer
,
3410 rtl8139_get_next_tctr_time(s
,curr_time
));
3412 #endif /* RTL8139_ONBOARD_TIMER */
3414 static void rtl8139_cleanup(VLANClientState
*vc
)
3416 RTL8139State
*s
= vc
->opaque
;
3421 static int pci_rtl8139_uninit(PCIDevice
*dev
)
3423 RTL8139State
*s
= DO_UPCAST(RTL8139State
, dev
, dev
);
3425 cpu_unregister_io_memory(s
->rtl8139_mmio_io_addr
);
3426 if (s
->cplus_txbuffer
) {
3427 qemu_free(s
->cplus_txbuffer
);
3428 s
->cplus_txbuffer
= NULL
;
3430 #ifdef RTL8139_ONBOARD_TIMER
3431 qemu_del_timer(s
->timer
);
3432 qemu_free_timer(s
->timer
);
3434 unregister_savevm("rtl8139", s
);
3435 qemu_del_vlan_client(s
->vc
);
3439 static int pci_rtl8139_init(PCIDevice
*dev
)
3441 RTL8139State
* s
= DO_UPCAST(RTL8139State
, dev
, dev
);
3444 pci_conf
= s
->dev
.config
;
3445 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_REALTEK
);
3446 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_REALTEK_8139
);
3447 pci_conf
[0x04] = 0x05; /* command = I/O space, Bus Master */
3448 pci_conf
[0x08] = RTL8139_PCI_REVID
; /* PCI revision ID; >=0x20 is for 8139C+ */
3449 pci_config_set_class(pci_conf
, PCI_CLASS_NETWORK_ETHERNET
);
3450 pci_conf
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_NORMAL
; /* header_type */
3451 pci_conf
[0x3d] = 1; /* interrupt pin 0 */
3452 pci_conf
[0x34] = 0xdc;
3454 /* I/O handler for memory-mapped I/O */
3455 s
->rtl8139_mmio_io_addr
=
3456 cpu_register_io_memory(rtl8139_mmio_read
, rtl8139_mmio_write
, s
);
3458 pci_register_bar(&s
->dev
, 0, 0x100,
3459 PCI_ADDRESS_SPACE_IO
, rtl8139_ioport_map
);
3461 pci_register_bar(&s
->dev
, 1, 0x100,
3462 PCI_ADDRESS_SPACE_MEM
, rtl8139_mmio_map
);
3464 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
3465 rtl8139_reset(&s
->dev
.qdev
);
3466 s
->vc
= qemu_new_vlan_client(NET_CLIENT_TYPE_NIC
,
3467 s
->conf
.vlan
, s
->conf
.peer
,
3468 dev
->qdev
.info
->name
, dev
->qdev
.id
,
3469 rtl8139_can_receive
, rtl8139_receive
, NULL
,
3470 NULL
, rtl8139_cleanup
, s
);
3471 qemu_format_nic_info_str(s
->vc
, s
->conf
.macaddr
.a
);
3473 s
->cplus_txbuffer
= NULL
;
3474 s
->cplus_txbuffer_len
= 0;
3475 s
->cplus_txbuffer_offset
= 0;
3477 register_savevm("rtl8139", -1, 4, rtl8139_save
, rtl8139_load
, s
);
3479 #ifdef RTL8139_ONBOARD_TIMER
3480 s
->timer
= qemu_new_timer(vm_clock
, rtl8139_timer
, s
);
3482 qemu_mod_timer(s
->timer
,
3483 rtl8139_get_next_tctr_time(s
,qemu_get_clock(vm_clock
)));
3484 #endif /* RTL8139_ONBOARD_TIMER */
3486 if (!dev
->qdev
.hotplugged
) {
3487 static int loaded
= 0;
3489 rom_add_option("pxe-rtl8139.bin");
3496 static PCIDeviceInfo rtl8139_info
= {
3497 .qdev
.name
= "rtl8139",
3498 .qdev
.size
= sizeof(RTL8139State
),
3499 .qdev
.reset
= rtl8139_reset
,
3500 .init
= pci_rtl8139_init
,
3501 .exit
= pci_rtl8139_uninit
,
3502 .qdev
.props
= (Property
[]) {
3503 DEFINE_NIC_PROPERTIES(RTL8139State
, conf
),
3504 DEFINE_PROP_END_OF_LIST(),
3508 static void rtl8139_register_devices(void)
3510 pci_qdev_register(&rtl8139_info
);
3513 device_init(rtl8139_register_devices
)