2 * Channel subsystem base support.
4 * Copyright 2012 IBM Corp.
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
8 * your option) any later version. See the COPYING file in the top-level
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "qapi/visitor.h"
16 #include "qemu/error-report.h"
17 #include "qemu/bitops.h"
18 #include "qemu/error-report.h"
19 #include "exec/address-spaces.h"
21 #include "hw/s390x/ioinst.h"
22 #include "hw/s390x/css.h"
24 #include "hw/s390x/s390_flic.h"
25 #include "hw/s390x/s390-virtio-ccw.h"
27 typedef struct CrwContainer
{
29 QTAILQ_ENTRY(CrwContainer
) sibling
;
32 static const VMStateDescription vmstate_crw
= {
35 .minimum_version_id
= 1,
36 .fields
= (VMStateField
[]) {
37 VMSTATE_UINT16(flags
, CRW
),
38 VMSTATE_UINT16(rsid
, CRW
),
43 static const VMStateDescription vmstate_crw_container
= {
44 .name
= "s390_crw_container",
46 .minimum_version_id
= 1,
47 .fields
= (VMStateField
[]) {
48 VMSTATE_STRUCT(crw
, CrwContainer
, 0, vmstate_crw
, CRW
),
53 typedef struct ChpInfo
{
59 static const VMStateDescription vmstate_chp_info
= {
60 .name
= "s390_chp_info",
62 .minimum_version_id
= 1,
63 .fields
= (VMStateField
[]) {
64 VMSTATE_UINT8(in_use
, ChpInfo
),
65 VMSTATE_UINT8(type
, ChpInfo
),
66 VMSTATE_UINT8(is_virtual
, ChpInfo
),
71 typedef struct SubchSet
{
72 SubchDev
*sch
[MAX_SCHID
+ 1];
73 unsigned long schids_used
[BITS_TO_LONGS(MAX_SCHID
+ 1)];
74 unsigned long devnos_used
[BITS_TO_LONGS(MAX_SCHID
+ 1)];
77 static const VMStateDescription vmstate_scsw
= {
80 .minimum_version_id
= 1,
81 .fields
= (VMStateField
[]) {
82 VMSTATE_UINT16(flags
, SCSW
),
83 VMSTATE_UINT16(ctrl
, SCSW
),
84 VMSTATE_UINT32(cpa
, SCSW
),
85 VMSTATE_UINT8(dstat
, SCSW
),
86 VMSTATE_UINT8(cstat
, SCSW
),
87 VMSTATE_UINT16(count
, SCSW
),
92 static const VMStateDescription vmstate_pmcw
= {
95 .minimum_version_id
= 1,
96 .fields
= (VMStateField
[]) {
97 VMSTATE_UINT32(intparm
, PMCW
),
98 VMSTATE_UINT16(flags
, PMCW
),
99 VMSTATE_UINT16(devno
, PMCW
),
100 VMSTATE_UINT8(lpm
, PMCW
),
101 VMSTATE_UINT8(pnom
, PMCW
),
102 VMSTATE_UINT8(lpum
, PMCW
),
103 VMSTATE_UINT8(pim
, PMCW
),
104 VMSTATE_UINT16(mbi
, PMCW
),
105 VMSTATE_UINT8(pom
, PMCW
),
106 VMSTATE_UINT8(pam
, PMCW
),
107 VMSTATE_UINT8_ARRAY(chpid
, PMCW
, 8),
108 VMSTATE_UINT32(chars
, PMCW
),
109 VMSTATE_END_OF_LIST()
113 static const VMStateDescription vmstate_schib
= {
114 .name
= "s390_schib",
116 .minimum_version_id
= 1,
117 .fields
= (VMStateField
[]) {
118 VMSTATE_STRUCT(pmcw
, SCHIB
, 0, vmstate_pmcw
, PMCW
),
119 VMSTATE_STRUCT(scsw
, SCHIB
, 0, vmstate_scsw
, SCSW
),
120 VMSTATE_UINT64(mba
, SCHIB
),
121 VMSTATE_UINT8_ARRAY(mda
, SCHIB
, 4),
122 VMSTATE_END_OF_LIST()
127 static const VMStateDescription vmstate_ccw1
= {
130 .minimum_version_id
= 1,
131 .fields
= (VMStateField
[]) {
132 VMSTATE_UINT8(cmd_code
, CCW1
),
133 VMSTATE_UINT8(flags
, CCW1
),
134 VMSTATE_UINT16(count
, CCW1
),
135 VMSTATE_UINT32(cda
, CCW1
),
136 VMSTATE_END_OF_LIST()
140 static const VMStateDescription vmstate_ciw
= {
143 .minimum_version_id
= 1,
144 .fields
= (VMStateField
[]) {
145 VMSTATE_UINT8(type
, CIW
),
146 VMSTATE_UINT8(command
, CIW
),
147 VMSTATE_UINT16(count
, CIW
),
148 VMSTATE_END_OF_LIST()
152 static const VMStateDescription vmstate_sense_id
= {
153 .name
= "s390_sense_id",
155 .minimum_version_id
= 1,
156 .fields
= (VMStateField
[]) {
157 VMSTATE_UINT8(reserved
, SenseId
),
158 VMSTATE_UINT16(cu_type
, SenseId
),
159 VMSTATE_UINT8(cu_model
, SenseId
),
160 VMSTATE_UINT16(dev_type
, SenseId
),
161 VMSTATE_UINT8(dev_model
, SenseId
),
162 VMSTATE_UINT8(unused
, SenseId
),
163 VMSTATE_STRUCT_ARRAY(ciw
, SenseId
, MAX_CIWS
, 0, vmstate_ciw
, CIW
),
164 VMSTATE_END_OF_LIST()
168 static const VMStateDescription vmstate_orb
= {
171 .minimum_version_id
= 1,
172 .fields
= (VMStateField
[]) {
173 VMSTATE_UINT32(intparm
, ORB
),
174 VMSTATE_UINT16(ctrl0
, ORB
),
175 VMSTATE_UINT8(lpm
, ORB
),
176 VMSTATE_UINT8(ctrl1
, ORB
),
177 VMSTATE_UINT32(cpa
, ORB
),
178 VMSTATE_END_OF_LIST()
182 static bool vmstate_schdev_orb_needed(void *opaque
)
184 return css_migration_enabled();
187 static const VMStateDescription vmstate_schdev_orb
= {
188 .name
= "s390_subch_dev/orb",
190 .minimum_version_id
= 1,
191 .needed
= vmstate_schdev_orb_needed
,
192 .fields
= (VMStateField
[]) {
193 VMSTATE_STRUCT(orb
, SubchDev
, 1, vmstate_orb
, ORB
),
194 VMSTATE_END_OF_LIST()
198 static int subch_dev_post_load(void *opaque
, int version_id
);
199 static int subch_dev_pre_save(void *opaque
);
201 const char err_hint_devno
[] = "Devno mismatch, tried to load wrong section!"
202 " Likely reason: some sequences of plug and unplug can break"
203 " migration for machine versions prior to 2.7 (known design flaw).";
205 const VMStateDescription vmstate_subch_dev
= {
206 .name
= "s390_subch_dev",
208 .minimum_version_id
= 1,
209 .post_load
= subch_dev_post_load
,
210 .pre_save
= subch_dev_pre_save
,
211 .fields
= (VMStateField
[]) {
212 VMSTATE_UINT8_EQUAL(cssid
, SubchDev
, "Bug!"),
213 VMSTATE_UINT8_EQUAL(ssid
, SubchDev
, "Bug!"),
214 VMSTATE_UINT16(migrated_schid
, SubchDev
),
215 VMSTATE_UINT16_EQUAL(devno
, SubchDev
, err_hint_devno
),
216 VMSTATE_BOOL(thinint_active
, SubchDev
),
217 VMSTATE_STRUCT(curr_status
, SubchDev
, 0, vmstate_schib
, SCHIB
),
218 VMSTATE_UINT8_ARRAY(sense_data
, SubchDev
, 32),
219 VMSTATE_UINT64(channel_prog
, SubchDev
),
220 VMSTATE_STRUCT(last_cmd
, SubchDev
, 0, vmstate_ccw1
, CCW1
),
221 VMSTATE_BOOL(last_cmd_valid
, SubchDev
),
222 VMSTATE_STRUCT(id
, SubchDev
, 0, vmstate_sense_id
, SenseId
),
223 VMSTATE_BOOL(ccw_fmt_1
, SubchDev
),
224 VMSTATE_UINT8(ccw_no_data_cnt
, SubchDev
),
225 VMSTATE_END_OF_LIST()
227 .subsections
= (const VMStateDescription
* []) {
233 typedef struct IndAddrPtrTmp
{
239 static int post_load_ind_addr(void *opaque
, int version_id
)
241 IndAddrPtrTmp
*ptmp
= opaque
;
242 IndAddr
**ind_addr
= ptmp
->parent
;
244 if (ptmp
->len
!= 0) {
245 *ind_addr
= get_indicator(ptmp
->addr
, ptmp
->len
);
252 static int pre_save_ind_addr(void *opaque
)
254 IndAddrPtrTmp
*ptmp
= opaque
;
255 IndAddr
*ind_addr
= *(ptmp
->parent
);
257 if (ind_addr
!= NULL
) {
258 ptmp
->len
= ind_addr
->len
;
259 ptmp
->addr
= ind_addr
->addr
;
268 const VMStateDescription vmstate_ind_addr_tmp
= {
269 .name
= "s390_ind_addr_tmp",
270 .pre_save
= pre_save_ind_addr
,
271 .post_load
= post_load_ind_addr
,
273 .fields
= (VMStateField
[]) {
274 VMSTATE_INT32(len
, IndAddrPtrTmp
),
275 VMSTATE_UINT64(addr
, IndAddrPtrTmp
),
276 VMSTATE_END_OF_LIST()
280 const VMStateDescription vmstate_ind_addr
= {
281 .name
= "s390_ind_addr_tmp",
282 .fields
= (VMStateField
[]) {
283 VMSTATE_WITH_TMP(IndAddr
*, IndAddrPtrTmp
, vmstate_ind_addr_tmp
),
284 VMSTATE_END_OF_LIST()
288 typedef struct CssImage
{
289 SubchSet
*sch_set
[MAX_SSID
+ 1];
290 ChpInfo chpids
[MAX_CHPID
+ 1];
293 static const VMStateDescription vmstate_css_img
= {
294 .name
= "s390_css_img",
296 .minimum_version_id
= 1,
297 .fields
= (VMStateField
[]) {
298 /* Subchannel sets have no relevant state. */
299 VMSTATE_STRUCT_ARRAY(chpids
, CssImage
, MAX_CHPID
+ 1, 0,
300 vmstate_chp_info
, ChpInfo
),
301 VMSTATE_END_OF_LIST()
306 typedef struct IoAdapter
{
313 typedef struct ChannelSubSys
{
314 QTAILQ_HEAD(, CrwContainer
) pending_crws
;
321 uint64_t chnmon_area
;
322 CssImage
*css
[MAX_CSSID
+ 1];
323 uint8_t default_cssid
;
324 /* don't migrate, see css_register_io_adapters */
325 IoAdapter
*io_adapters
[CSS_IO_ADAPTER_TYPE_NUMS
][MAX_ISC
+ 1];
326 /* don't migrate, see get_indicator and IndAddrPtrTmp */
327 QTAILQ_HEAD(, IndAddr
) indicator_addresses
;
330 static const VMStateDescription vmstate_css
= {
333 .minimum_version_id
= 1,
334 .fields
= (VMStateField
[]) {
335 VMSTATE_QTAILQ_V(pending_crws
, ChannelSubSys
, 1, vmstate_crw_container
,
336 CrwContainer
, sibling
),
337 VMSTATE_BOOL(sei_pending
, ChannelSubSys
),
338 VMSTATE_BOOL(do_crw_mchk
, ChannelSubSys
),
339 VMSTATE_BOOL(crws_lost
, ChannelSubSys
),
340 /* These were kind of migrated by virtio */
341 VMSTATE_UINT8(max_cssid
, ChannelSubSys
),
342 VMSTATE_UINT8(max_ssid
, ChannelSubSys
),
343 VMSTATE_BOOL(chnmon_active
, ChannelSubSys
),
344 VMSTATE_UINT64(chnmon_area
, ChannelSubSys
),
345 VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css
, ChannelSubSys
, MAX_CSSID
+ 1,
346 0, vmstate_css_img
, CssImage
),
347 VMSTATE_UINT8(default_cssid
, ChannelSubSys
),
348 VMSTATE_END_OF_LIST()
352 static ChannelSubSys channel_subsys
= {
353 .pending_crws
= QTAILQ_HEAD_INITIALIZER(channel_subsys
.pending_crws
),
355 .sei_pending
= false,
358 .chnmon_active
= false,
359 .indicator_addresses
=
360 QTAILQ_HEAD_INITIALIZER(channel_subsys
.indicator_addresses
),
363 static int subch_dev_pre_save(void *opaque
)
365 SubchDev
*s
= opaque
;
367 /* Prepare remote_schid for save */
368 s
->migrated_schid
= s
->schid
;
373 static int subch_dev_post_load(void *opaque
, int version_id
)
376 SubchDev
*s
= opaque
;
378 /* Re-assign the subchannel to remote_schid if necessary */
379 if (s
->migrated_schid
!= s
->schid
) {
380 if (css_find_subch(true, s
->cssid
, s
->ssid
, s
->schid
) == s
) {
382 * Cleanup the slot before moving to s->migrated_schid provided
383 * it still belongs to us, i.e. it was not changed by previous
384 * invocation of this function.
386 css_subch_assign(s
->cssid
, s
->ssid
, s
->schid
, s
->devno
, NULL
);
388 /* It's OK to re-assign without a prior de-assign. */
389 s
->schid
= s
->migrated_schid
;
390 css_subch_assign(s
->cssid
, s
->ssid
, s
->schid
, s
->devno
, s
);
393 if (css_migration_enabled()) {
394 /* No compat voodoo to do ;) */
398 * Hack alert. If we don't migrate the channel subsystem status
399 * we still need to find out if the guest enabled mss/mcss-e.
400 * If the subchannel is enabled, it certainly was able to access it,
401 * so adjust the max_ssid/max_cssid values for relevant ssid/cssid
402 * values. This is not watertight, but better than nothing.
404 if (s
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_ENA
) {
406 channel_subsys
.max_ssid
= MAX_SSID
;
408 if (s
->cssid
!= channel_subsys
.default_cssid
) {
409 channel_subsys
.max_cssid
= MAX_CSSID
;
415 void css_register_vmstate(void)
417 vmstate_register(NULL
, 0, &vmstate_css
, &channel_subsys
);
420 IndAddr
*get_indicator(hwaddr ind_addr
, int len
)
424 QTAILQ_FOREACH(indicator
, &channel_subsys
.indicator_addresses
, sibling
) {
425 if (indicator
->addr
== ind_addr
) {
430 indicator
= g_new0(IndAddr
, 1);
431 indicator
->addr
= ind_addr
;
432 indicator
->len
= len
;
433 indicator
->refcnt
= 1;
434 QTAILQ_INSERT_TAIL(&channel_subsys
.indicator_addresses
,
439 static int s390_io_adapter_map(AdapterInfo
*adapter
, uint64_t map_addr
,
442 S390FLICState
*fs
= s390_get_flic();
443 S390FLICStateClass
*fsc
= S390_FLIC_COMMON_GET_CLASS(fs
);
445 return fsc
->io_adapter_map(fs
, adapter
->adapter_id
, map_addr
, do_map
);
448 void release_indicator(AdapterInfo
*adapter
, IndAddr
*indicator
)
450 assert(indicator
->refcnt
> 0);
452 if (indicator
->refcnt
> 0) {
455 QTAILQ_REMOVE(&channel_subsys
.indicator_addresses
, indicator
, sibling
);
456 if (indicator
->map
) {
457 s390_io_adapter_map(adapter
, indicator
->map
, false);
462 int map_indicator(AdapterInfo
*adapter
, IndAddr
*indicator
)
466 if (indicator
->map
) {
467 return 0; /* already mapped is not an error */
469 indicator
->map
= indicator
->addr
;
470 ret
= s390_io_adapter_map(adapter
, indicator
->map
, true);
471 if ((ret
!= 0) && (ret
!= -ENOSYS
)) {
481 int css_create_css_image(uint8_t cssid
, bool default_image
)
483 trace_css_new_image(cssid
, default_image
? "(default)" : "");
484 /* 255 is reserved */
488 if (channel_subsys
.css
[cssid
]) {
491 channel_subsys
.css
[cssid
] = g_new0(CssImage
, 1);
493 channel_subsys
.default_cssid
= cssid
;
498 uint32_t css_get_adapter_id(CssIoAdapterType type
, uint8_t isc
)
500 if (type
>= CSS_IO_ADAPTER_TYPE_NUMS
|| isc
> MAX_ISC
||
501 !channel_subsys
.io_adapters
[type
][isc
]) {
505 return channel_subsys
.io_adapters
[type
][isc
]->id
;
509 * css_register_io_adapters: Register I/O adapters per ISC during init
511 * @swap: an indication if byte swap is needed.
512 * @maskable: an indication if the adapter is subject to the mask operation.
513 * @flags: further characteristics of the adapter.
514 * e.g. suppressible, an indication if the adapter is subject to AIS.
515 * @errp: location to store error information.
517 void css_register_io_adapters(CssIoAdapterType type
, bool swap
, bool maskable
,
518 uint8_t flags
, Error
**errp
)
523 S390FLICState
*fs
= s390_get_flic();
524 S390FLICStateClass
*fsc
= S390_FLIC_COMMON_GET_CLASS(fs
);
527 * Disallow multiple registrations for the same device type.
528 * Report an error if registering for an already registered type.
530 if (channel_subsys
.io_adapters
[type
][0]) {
531 error_setg(errp
, "Adapters for type %d already registered", type
);
534 for (isc
= 0; isc
<= MAX_ISC
; isc
++) {
535 id
= (type
<< 3) | isc
;
536 ret
= fsc
->register_io_adapter(fs
, id
, isc
, swap
, maskable
, flags
);
538 adapter
= g_new0(IoAdapter
, 1);
541 adapter
->type
= type
;
542 adapter
->flags
= flags
;
543 channel_subsys
.io_adapters
[type
][isc
] = adapter
;
545 error_setg_errno(errp
, -ret
, "Unexpected error %d when "
546 "registering adapter %d", ret
, id
);
552 * No need to free registered adapters in kvm: kvm will clean up
553 * when the machine goes away.
556 for (isc
--; isc
>= 0; isc
--) {
557 g_free(channel_subsys
.io_adapters
[type
][isc
]);
558 channel_subsys
.io_adapters
[type
][isc
] = NULL
;
564 static void css_clear_io_interrupt(uint16_t subchannel_id
,
565 uint16_t subchannel_nr
)
568 static bool no_clear_irq
;
569 S390FLICState
*fs
= s390_get_flic();
570 S390FLICStateClass
*fsc
= S390_FLIC_COMMON_GET_CLASS(fs
);
573 if (unlikely(no_clear_irq
)) {
576 r
= fsc
->clear_io_irq(fs
, subchannel_id
, subchannel_nr
);
583 * Ignore unavailability, as the user can't do anything
588 error_setg_errno(&err
, -r
, "unexpected error condition");
589 error_propagate(&error_abort
, err
);
593 static inline uint16_t css_do_build_subchannel_id(uint8_t cssid
, uint8_t ssid
)
595 if (channel_subsys
.max_cssid
> 0) {
596 return (cssid
<< 8) | (1 << 3) | (ssid
<< 1) | 1;
598 return (ssid
<< 1) | 1;
601 uint16_t css_build_subchannel_id(SubchDev
*sch
)
603 return css_do_build_subchannel_id(sch
->cssid
, sch
->ssid
);
606 void css_inject_io_interrupt(SubchDev
*sch
)
608 uint8_t isc
= (sch
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_ISC
) >> 11;
610 trace_css_io_interrupt(sch
->cssid
, sch
->ssid
, sch
->schid
,
611 sch
->curr_status
.pmcw
.intparm
, isc
, "");
612 s390_io_interrupt(css_build_subchannel_id(sch
),
614 sch
->curr_status
.pmcw
.intparm
,
618 void css_conditional_io_interrupt(SubchDev
*sch
)
621 * If the subchannel is not currently status pending, make it pending
624 if (!(sch
->curr_status
.scsw
.ctrl
& SCSW_STCTL_STATUS_PEND
)) {
625 uint8_t isc
= (sch
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_ISC
) >> 11;
627 trace_css_io_interrupt(sch
->cssid
, sch
->ssid
, sch
->schid
,
628 sch
->curr_status
.pmcw
.intparm
, isc
,
630 sch
->curr_status
.scsw
.ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
631 sch
->curr_status
.scsw
.ctrl
|=
632 SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
;
633 /* Inject an I/O interrupt. */
634 s390_io_interrupt(css_build_subchannel_id(sch
),
636 sch
->curr_status
.pmcw
.intparm
,
641 int css_do_sic(CPUS390XState
*env
, uint8_t isc
, uint16_t mode
)
643 S390FLICState
*fs
= s390_get_flic();
644 S390FLICStateClass
*fsc
= S390_FLIC_COMMON_GET_CLASS(fs
);
647 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
652 trace_css_do_sic(mode
, isc
);
654 case SIC_IRQ_MODE_ALL
:
655 case SIC_IRQ_MODE_SINGLE
:
662 r
= fsc
->modify_ais_mode(fs
, isc
, mode
) ? -PGM_OPERATION
: 0;
667 void css_adapter_interrupt(CssIoAdapterType type
, uint8_t isc
)
669 S390FLICState
*fs
= s390_get_flic();
670 S390FLICStateClass
*fsc
= S390_FLIC_COMMON_GET_CLASS(fs
);
671 uint32_t io_int_word
= (isc
<< 27) | IO_INT_WORD_AI
;
672 IoAdapter
*adapter
= channel_subsys
.io_adapters
[type
][isc
];
678 trace_css_adapter_interrupt(isc
);
679 if (fs
->ais_supported
) {
680 if (fsc
->inject_airq(fs
, type
, isc
, adapter
->flags
)) {
681 error_report("Failed to inject airq with AIS supported");
685 s390_io_interrupt(0, 0, 0, io_int_word
);
689 static void sch_handle_clear_func(SubchDev
*sch
)
691 PMCW
*p
= &sch
->curr_status
.pmcw
;
692 SCSW
*s
= &sch
->curr_status
.scsw
;
695 /* Path management: In our simple css, we always choose the only path. */
698 /* Reset values prior to 'issuing the clear signal'. */
701 s
->flags
&= ~SCSW_FLAGS_MASK_PNO
;
703 /* We always 'attempt to issue the clear signal', and we always succeed. */
704 sch
->channel_prog
= 0x0;
705 sch
->last_cmd_valid
= false;
706 s
->ctrl
&= ~SCSW_ACTL_CLEAR_PEND
;
707 s
->ctrl
|= SCSW_STCTL_STATUS_PEND
;
715 static void sch_handle_halt_func(SubchDev
*sch
)
718 PMCW
*p
= &sch
->curr_status
.pmcw
;
719 SCSW
*s
= &sch
->curr_status
.scsw
;
720 hwaddr curr_ccw
= sch
->channel_prog
;
723 /* Path management: In our simple css, we always choose the only path. */
726 /* We always 'attempt to issue the halt signal', and we always succeed. */
727 sch
->channel_prog
= 0x0;
728 sch
->last_cmd_valid
= false;
729 s
->ctrl
&= ~SCSW_ACTL_HALT_PEND
;
730 s
->ctrl
|= SCSW_STCTL_STATUS_PEND
;
732 if ((s
->ctrl
& (SCSW_ACTL_SUBCH_ACTIVE
| SCSW_ACTL_DEVICE_ACTIVE
)) ||
733 !((s
->ctrl
& SCSW_ACTL_START_PEND
) ||
734 (s
->ctrl
& SCSW_ACTL_SUSP
))) {
735 s
->dstat
= SCSW_DSTAT_DEVICE_END
;
737 if ((s
->ctrl
& (SCSW_ACTL_SUBCH_ACTIVE
| SCSW_ACTL_DEVICE_ACTIVE
)) ||
738 (s
->ctrl
& SCSW_ACTL_SUSP
)) {
739 s
->cpa
= curr_ccw
+ 8;
746 static void copy_sense_id_to_guest(SenseId
*dest
, SenseId
*src
)
750 dest
->reserved
= src
->reserved
;
751 dest
->cu_type
= cpu_to_be16(src
->cu_type
);
752 dest
->cu_model
= src
->cu_model
;
753 dest
->dev_type
= cpu_to_be16(src
->dev_type
);
754 dest
->dev_model
= src
->dev_model
;
755 dest
->unused
= src
->unused
;
756 for (i
= 0; i
< ARRAY_SIZE(dest
->ciw
); i
++) {
757 dest
->ciw
[i
].type
= src
->ciw
[i
].type
;
758 dest
->ciw
[i
].command
= src
->ciw
[i
].command
;
759 dest
->ciw
[i
].count
= cpu_to_be16(src
->ciw
[i
].count
);
763 static CCW1
copy_ccw_from_guest(hwaddr addr
, bool fmt1
)
770 cpu_physical_memory_read(addr
, &tmp1
, sizeof(tmp1
));
771 ret
.cmd_code
= tmp1
.cmd_code
;
772 ret
.flags
= tmp1
.flags
;
773 ret
.count
= be16_to_cpu(tmp1
.count
);
774 ret
.cda
= be32_to_cpu(tmp1
.cda
);
776 cpu_physical_memory_read(addr
, &tmp0
, sizeof(tmp0
));
777 if ((tmp0
.cmd_code
& 0x0f) == CCW_CMD_TIC
) {
778 ret
.cmd_code
= CCW_CMD_TIC
;
782 ret
.cmd_code
= tmp0
.cmd_code
;
783 ret
.flags
= tmp0
.flags
;
784 ret
.count
= be16_to_cpu(tmp0
.count
);
786 ret
.cda
= be16_to_cpu(tmp0
.cda1
) | (tmp0
.cda0
<< 16);
791 * If out of bounds marks the stream broken. If broken returns -EINVAL,
792 * otherwise the requested length (may be zero)
794 static inline int cds_check_len(CcwDataStream
*cds
, int len
)
796 if (cds
->at_byte
+ len
> cds
->count
) {
797 cds
->flags
|= CDS_F_STREAM_BROKEN
;
799 return cds
->flags
& CDS_F_STREAM_BROKEN
? -EINVAL
: len
;
802 static inline bool cds_ccw_addrs_ok(hwaddr addr
, int len
, bool ccw_fmt1
)
804 return (addr
+ len
) < (ccw_fmt1
? (1UL << 31) : (1UL << 24));
807 static int ccw_dstream_rw_noflags(CcwDataStream
*cds
, void *buff
, int len
,
812 ret
= cds_check_len(cds
, len
);
816 if (!cds_ccw_addrs_ok(cds
->cda
, len
, cds
->flags
& CDS_F_FMT
)) {
817 return -EINVAL
; /* channel program check */
819 if (op
== CDS_OP_A
) {
822 ret
= address_space_rw(&address_space_memory
, cds
->cda
,
823 MEMTXATTRS_UNSPECIFIED
, buff
, len
, op
);
824 if (ret
!= MEMTX_OK
) {
825 cds
->flags
|= CDS_F_STREAM_BROKEN
;
834 /* returns values between 1 and bsz, where bsz is a power of 2 */
835 static inline uint16_t ida_continuous_left(hwaddr cda
, uint64_t bsz
)
837 return bsz
- (cda
& (bsz
- 1));
840 static inline uint64_t ccw_ida_block_size(uint8_t flags
)
842 if ((flags
& CDS_F_C64
) && !(flags
& CDS_F_I2K
)) {
848 static inline int ida_read_next_idaw(CcwDataStream
*cds
)
850 union {uint64_t fmt2
; uint32_t fmt1
; } idaw
;
853 bool idaw_fmt2
= cds
->flags
& CDS_F_C64
;
854 bool ccw_fmt1
= cds
->flags
& CDS_F_FMT
;
857 idaw_addr
= cds
->cda_orig
+ sizeof(idaw
.fmt2
) * cds
->at_idaw
;
858 if (idaw_addr
& 0x07 || !cds_ccw_addrs_ok(idaw_addr
, 0, ccw_fmt1
)) {
859 return -EINVAL
; /* channel program check */
861 ret
= address_space_rw(&address_space_memory
, idaw_addr
,
862 MEMTXATTRS_UNSPECIFIED
, (void *) &idaw
.fmt2
,
863 sizeof(idaw
.fmt2
), false);
864 cds
->cda
= be64_to_cpu(idaw
.fmt2
);
866 idaw_addr
= cds
->cda_orig
+ sizeof(idaw
.fmt1
) * cds
->at_idaw
;
867 if (idaw_addr
& 0x03 || !cds_ccw_addrs_ok(idaw_addr
, 0, ccw_fmt1
)) {
868 return -EINVAL
; /* channel program check */
870 ret
= address_space_rw(&address_space_memory
, idaw_addr
,
871 MEMTXATTRS_UNSPECIFIED
, (void *) &idaw
.fmt1
,
872 sizeof(idaw
.fmt1
), false);
873 cds
->cda
= be64_to_cpu(idaw
.fmt1
);
874 if (cds
->cda
& 0x80000000) {
875 return -EINVAL
; /* channel program check */
879 if (ret
!= MEMTX_OK
) {
880 /* assume inaccessible address */
881 return -EINVAL
; /* channel program check */
886 static int ccw_dstream_rw_ida(CcwDataStream
*cds
, void *buff
, int len
,
889 uint64_t bsz
= ccw_ida_block_size(cds
->flags
);
891 uint16_t cont_left
, iter_len
;
893 ret
= cds_check_len(cds
, len
);
898 /* read first idaw */
899 ret
= ida_read_next_idaw(cds
);
903 cont_left
= ida_continuous_left(cds
->cda
, bsz
);
905 cont_left
= ida_continuous_left(cds
->cda
, bsz
);
906 if (cont_left
== bsz
) {
907 ret
= ida_read_next_idaw(cds
);
911 if (cds
->cda
& (bsz
- 1)) {
912 ret
= -EINVAL
; /* channel program check */
918 iter_len
= MIN(len
, cont_left
);
919 if (op
!= CDS_OP_A
) {
920 ret
= address_space_rw(&address_space_memory
, cds
->cda
,
921 MEMTXATTRS_UNSPECIFIED
, buff
, iter_len
, op
);
922 if (ret
!= MEMTX_OK
) {
923 /* assume inaccessible address */
924 ret
= -EINVAL
; /* channel program check */
928 cds
->at_byte
+= iter_len
;
929 cds
->cda
+= iter_len
;
934 ret
= ida_read_next_idaw(cds
);
942 cds
->flags
|= CDS_F_STREAM_BROKEN
;
946 void ccw_dstream_init(CcwDataStream
*cds
, CCW1
const *ccw
, ORB
const *orb
)
949 * We don't support MIDA (an optional facility) yet and we
950 * catch this earlier. Just for expressing the precondition.
952 g_assert(!(orb
->ctrl1
& ORB_CTRL1_MASK_MIDAW
));
953 cds
->flags
= (orb
->ctrl0
& ORB_CTRL0_MASK_I2K
? CDS_F_I2K
: 0) |
954 (orb
->ctrl0
& ORB_CTRL0_MASK_C64
? CDS_F_C64
: 0) |
955 (orb
->ctrl0
& ORB_CTRL0_MASK_FMT
? CDS_F_FMT
: 0) |
956 (ccw
->flags
& CCW_FLAG_IDA
? CDS_F_IDA
: 0);
958 cds
->count
= ccw
->count
;
959 cds
->cda_orig
= ccw
->cda
;
960 ccw_dstream_rewind(cds
);
961 if (!(cds
->flags
& CDS_F_IDA
)) {
962 cds
->op_handler
= ccw_dstream_rw_noflags
;
964 cds
->op_handler
= ccw_dstream_rw_ida
;
968 static int css_interpret_ccw(SubchDev
*sch
, hwaddr ccw_addr
,
969 bool suspend_allowed
)
977 return -EINVAL
; /* channel-program check */
979 /* Check doubleword aligned and 31 or 24 (fmt 0) bit addressable. */
980 if (ccw_addr
& (sch
->ccw_fmt_1
? 0x80000007 : 0xff000007)) {
984 /* Translate everything to format-1 ccws - the information is the same. */
985 ccw
= copy_ccw_from_guest(ccw_addr
, sch
->ccw_fmt_1
);
987 /* Check for invalid command codes. */
988 if ((ccw
.cmd_code
& 0x0f) == 0) {
991 if (((ccw
.cmd_code
& 0x0f) == CCW_CMD_TIC
) &&
992 ((ccw
.cmd_code
& 0xf0) != 0)) {
995 if (!sch
->ccw_fmt_1
&& (ccw
.count
== 0) &&
996 (ccw
.cmd_code
!= CCW_CMD_TIC
)) {
1000 /* We don't support MIDA. */
1001 if (ccw
.flags
& CCW_FLAG_MIDA
) {
1005 if (ccw
.flags
& CCW_FLAG_SUSPEND
) {
1006 return suspend_allowed
? -EINPROGRESS
: -EINVAL
;
1009 check_len
= !((ccw
.flags
& CCW_FLAG_SLI
) && !(ccw
.flags
& CCW_FLAG_DC
));
1012 if (sch
->ccw_no_data_cnt
== 255) {
1015 sch
->ccw_no_data_cnt
++;
1018 /* Look at the command. */
1019 ccw_dstream_init(&sch
->cds
, &ccw
, &(sch
->orb
));
1020 switch (ccw
.cmd_code
) {
1022 /* Nothing to do. */
1025 case CCW_CMD_BASIC_SENSE
:
1027 if (ccw
.count
!= sizeof(sch
->sense_data
)) {
1032 len
= MIN(ccw
.count
, sizeof(sch
->sense_data
));
1033 ccw_dstream_write_buf(&sch
->cds
, sch
->sense_data
, len
);
1034 sch
->curr_status
.scsw
.count
= ccw_dstream_residual_count(&sch
->cds
);
1035 memset(sch
->sense_data
, 0, sizeof(sch
->sense_data
));
1038 case CCW_CMD_SENSE_ID
:
1042 copy_sense_id_to_guest(&sense_id
, &sch
->id
);
1043 /* Sense ID information is device specific. */
1045 if (ccw
.count
!= sizeof(sense_id
)) {
1050 len
= MIN(ccw
.count
, sizeof(sense_id
));
1052 * Only indicate 0xff in the first sense byte if we actually
1053 * have enough place to store at least bytes 0-3.
1056 sense_id
.reserved
= 0xff;
1058 sense_id
.reserved
= 0;
1060 ccw_dstream_write_buf(&sch
->cds
, &sense_id
, len
);
1061 sch
->curr_status
.scsw
.count
= ccw_dstream_residual_count(&sch
->cds
);
1066 if (sch
->last_cmd_valid
&& (sch
->last_cmd
.cmd_code
== CCW_CMD_TIC
)) {
1070 if (ccw
.flags
|| ccw
.count
) {
1071 /* We have already sanitized these if converted from fmt 0. */
1075 sch
->channel_prog
= ccw
.cda
;
1080 /* Handle device specific commands. */
1081 ret
= sch
->ccw_cb(sch
, ccw
);
1087 sch
->last_cmd
= ccw
;
1088 sch
->last_cmd_valid
= true;
1090 if (ccw
.flags
& CCW_FLAG_CC
) {
1091 sch
->channel_prog
+= 8;
1099 static void sch_handle_start_func_virtual(SubchDev
*sch
)
1102 PMCW
*p
= &sch
->curr_status
.pmcw
;
1103 SCSW
*s
= &sch
->curr_status
.scsw
;
1106 bool suspend_allowed
;
1108 /* Path management: In our simple css, we always choose the only path. */
1111 if (!(s
->ctrl
& SCSW_ACTL_SUSP
)) {
1112 /* Start Function triggered via ssch, i.e. we have an ORB */
1113 ORB
*orb
= &sch
->orb
;
1116 /* Look at the orb and try to execute the channel program. */
1117 p
->intparm
= orb
->intparm
;
1118 if (!(orb
->lpm
& path
)) {
1119 /* Generate a deferred cc 3 condition. */
1120 s
->flags
|= SCSW_FLAGS_MASK_CC
;
1121 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
1122 s
->ctrl
|= (SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
);
1125 sch
->ccw_fmt_1
= !!(orb
->ctrl0
& ORB_CTRL0_MASK_FMT
);
1126 s
->flags
|= (sch
->ccw_fmt_1
) ? SCSW_FLAGS_MASK_FMT
: 0;
1127 sch
->ccw_no_data_cnt
= 0;
1128 suspend_allowed
= !!(orb
->ctrl0
& ORB_CTRL0_MASK_SPND
);
1130 /* Start Function resumed via rsch */
1131 s
->ctrl
&= ~(SCSW_ACTL_SUSP
| SCSW_ACTL_RESUME_PEND
);
1132 /* The channel program had been suspended before. */
1133 suspend_allowed
= true;
1135 sch
->last_cmd_valid
= false;
1137 ret
= css_interpret_ccw(sch
, sch
->channel_prog
, suspend_allowed
);
1140 /* ccw chain, continue processing */
1144 s
->ctrl
&= ~SCSW_ACTL_START_PEND
;
1145 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
1146 s
->ctrl
|= SCSW_STCTL_PRIMARY
| SCSW_STCTL_SECONDARY
|
1147 SCSW_STCTL_STATUS_PEND
;
1148 s
->dstat
= SCSW_DSTAT_CHANNEL_END
| SCSW_DSTAT_DEVICE_END
;
1149 s
->cpa
= sch
->channel_prog
+ 8;
1152 /* I/O errors, status depends on specific devices */
1155 /* unsupported command, generate unit check (command reject) */
1156 s
->ctrl
&= ~SCSW_ACTL_START_PEND
;
1157 s
->dstat
= SCSW_DSTAT_UNIT_CHECK
;
1158 /* Set sense bit 0 in ecw0. */
1159 sch
->sense_data
[0] = 0x80;
1160 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
1161 s
->ctrl
|= SCSW_STCTL_PRIMARY
| SCSW_STCTL_SECONDARY
|
1162 SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
;
1163 s
->cpa
= sch
->channel_prog
+ 8;
1166 /* channel program has been suspended */
1167 s
->ctrl
&= ~SCSW_ACTL_START_PEND
;
1168 s
->ctrl
|= SCSW_ACTL_SUSP
;
1171 /* error, generate channel program check */
1172 s
->ctrl
&= ~SCSW_ACTL_START_PEND
;
1173 s
->cstat
= SCSW_CSTAT_PROG_CHECK
;
1174 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
1175 s
->ctrl
|= SCSW_STCTL_PRIMARY
| SCSW_STCTL_SECONDARY
|
1176 SCSW_STCTL_ALERT
| SCSW_STCTL_STATUS_PEND
;
1177 s
->cpa
= sch
->channel_prog
+ 8;
1180 } while (ret
== -EAGAIN
);
1184 static IOInstEnding
sch_handle_start_func_passthrough(SubchDev
*sch
)
1187 PMCW
*p
= &sch
->curr_status
.pmcw
;
1188 SCSW
*s
= &sch
->curr_status
.scsw
;
1190 ORB
*orb
= &sch
->orb
;
1191 if (!(s
->ctrl
& SCSW_ACTL_SUSP
)) {
1192 assert(orb
!= NULL
);
1193 p
->intparm
= orb
->intparm
;
1197 * Only support prefetch enable mode.
1198 * Only support 64bit addressing idal.
1200 if (!(orb
->ctrl0
& ORB_CTRL0_MASK_PFCH
) ||
1201 !(orb
->ctrl0
& ORB_CTRL0_MASK_C64
)) {
1202 warn_report("vfio-ccw requires PFCH and C64 flags set");
1203 sch_gen_unit_exception(sch
);
1204 css_inject_io_interrupt(sch
);
1205 return IOINST_CC_EXPECTED
;
1207 return s390_ccw_cmd_request(sch
);
1211 * On real machines, this would run asynchronously to the main vcpus.
1212 * We might want to make some parts of the ssch handling (interpreting
1213 * read/writes) asynchronous later on if we start supporting more than
1214 * our current very simple devices.
1216 IOInstEnding
do_subchannel_work_virtual(SubchDev
*sch
)
1219 SCSW
*s
= &sch
->curr_status
.scsw
;
1221 if (s
->ctrl
& SCSW_FCTL_CLEAR_FUNC
) {
1222 sch_handle_clear_func(sch
);
1223 } else if (s
->ctrl
& SCSW_FCTL_HALT_FUNC
) {
1224 sch_handle_halt_func(sch
);
1225 } else if (s
->ctrl
& SCSW_FCTL_START_FUNC
) {
1226 /* Triggered by both ssch and rsch. */
1227 sch_handle_start_func_virtual(sch
);
1229 css_inject_io_interrupt(sch
);
1230 /* inst must succeed if this func is called */
1231 return IOINST_CC_EXPECTED
;
1234 IOInstEnding
do_subchannel_work_passthrough(SubchDev
*sch
)
1236 SCSW
*s
= &sch
->curr_status
.scsw
;
1238 if (s
->ctrl
& SCSW_FCTL_CLEAR_FUNC
) {
1239 /* TODO: Clear handling */
1240 sch_handle_clear_func(sch
);
1241 } else if (s
->ctrl
& SCSW_FCTL_HALT_FUNC
) {
1242 /* TODO: Halt handling */
1243 sch_handle_halt_func(sch
);
1244 } else if (s
->ctrl
& SCSW_FCTL_START_FUNC
) {
1245 return sch_handle_start_func_passthrough(sch
);
1247 return IOINST_CC_EXPECTED
;
1250 static IOInstEnding
do_subchannel_work(SubchDev
*sch
)
1252 if (!sch
->do_subchannel_work
) {
1253 return IOINST_CC_STATUS_PRESENT
;
1255 g_assert(sch
->curr_status
.scsw
.ctrl
& SCSW_CTRL_MASK_FCTL
);
1256 return sch
->do_subchannel_work(sch
);
1259 static void copy_pmcw_to_guest(PMCW
*dest
, const PMCW
*src
)
1263 dest
->intparm
= cpu_to_be32(src
->intparm
);
1264 dest
->flags
= cpu_to_be16(src
->flags
);
1265 dest
->devno
= cpu_to_be16(src
->devno
);
1266 dest
->lpm
= src
->lpm
;
1267 dest
->pnom
= src
->pnom
;
1268 dest
->lpum
= src
->lpum
;
1269 dest
->pim
= src
->pim
;
1270 dest
->mbi
= cpu_to_be16(src
->mbi
);
1271 dest
->pom
= src
->pom
;
1272 dest
->pam
= src
->pam
;
1273 for (i
= 0; i
< ARRAY_SIZE(dest
->chpid
); i
++) {
1274 dest
->chpid
[i
] = src
->chpid
[i
];
1276 dest
->chars
= cpu_to_be32(src
->chars
);
1279 void copy_scsw_to_guest(SCSW
*dest
, const SCSW
*src
)
1281 dest
->flags
= cpu_to_be16(src
->flags
);
1282 dest
->ctrl
= cpu_to_be16(src
->ctrl
);
1283 dest
->cpa
= cpu_to_be32(src
->cpa
);
1284 dest
->dstat
= src
->dstat
;
1285 dest
->cstat
= src
->cstat
;
1286 dest
->count
= cpu_to_be16(src
->count
);
1289 static void copy_schib_to_guest(SCHIB
*dest
, const SCHIB
*src
)
1293 copy_pmcw_to_guest(&dest
->pmcw
, &src
->pmcw
);
1294 copy_scsw_to_guest(&dest
->scsw
, &src
->scsw
);
1295 dest
->mba
= cpu_to_be64(src
->mba
);
1296 for (i
= 0; i
< ARRAY_SIZE(dest
->mda
); i
++) {
1297 dest
->mda
[i
] = src
->mda
[i
];
1301 int css_do_stsch(SubchDev
*sch
, SCHIB
*schib
)
1303 /* Use current status. */
1304 copy_schib_to_guest(schib
, &sch
->curr_status
);
1308 static void copy_pmcw_from_guest(PMCW
*dest
, const PMCW
*src
)
1312 dest
->intparm
= be32_to_cpu(src
->intparm
);
1313 dest
->flags
= be16_to_cpu(src
->flags
);
1314 dest
->devno
= be16_to_cpu(src
->devno
);
1315 dest
->lpm
= src
->lpm
;
1316 dest
->pnom
= src
->pnom
;
1317 dest
->lpum
= src
->lpum
;
1318 dest
->pim
= src
->pim
;
1319 dest
->mbi
= be16_to_cpu(src
->mbi
);
1320 dest
->pom
= src
->pom
;
1321 dest
->pam
= src
->pam
;
1322 for (i
= 0; i
< ARRAY_SIZE(dest
->chpid
); i
++) {
1323 dest
->chpid
[i
] = src
->chpid
[i
];
1325 dest
->chars
= be32_to_cpu(src
->chars
);
1328 static void copy_scsw_from_guest(SCSW
*dest
, const SCSW
*src
)
1330 dest
->flags
= be16_to_cpu(src
->flags
);
1331 dest
->ctrl
= be16_to_cpu(src
->ctrl
);
1332 dest
->cpa
= be32_to_cpu(src
->cpa
);
1333 dest
->dstat
= src
->dstat
;
1334 dest
->cstat
= src
->cstat
;
1335 dest
->count
= be16_to_cpu(src
->count
);
1338 static void copy_schib_from_guest(SCHIB
*dest
, const SCHIB
*src
)
1342 copy_pmcw_from_guest(&dest
->pmcw
, &src
->pmcw
);
1343 copy_scsw_from_guest(&dest
->scsw
, &src
->scsw
);
1344 dest
->mba
= be64_to_cpu(src
->mba
);
1345 for (i
= 0; i
< ARRAY_SIZE(dest
->mda
); i
++) {
1346 dest
->mda
[i
] = src
->mda
[i
];
1350 int css_do_msch(SubchDev
*sch
, const SCHIB
*orig_schib
)
1352 SCSW
*s
= &sch
->curr_status
.scsw
;
1353 PMCW
*p
= &sch
->curr_status
.pmcw
;
1358 if (!(sch
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_DNV
)) {
1363 if (s
->ctrl
& SCSW_STCTL_STATUS_PEND
) {
1369 (SCSW_FCTL_START_FUNC
|SCSW_FCTL_HALT_FUNC
|SCSW_FCTL_CLEAR_FUNC
)) {
1374 copy_schib_from_guest(&schib
, orig_schib
);
1375 /* Only update the program-modifiable fields. */
1376 p
->intparm
= schib
.pmcw
.intparm
;
1377 oldflags
= p
->flags
;
1378 p
->flags
&= ~(PMCW_FLAGS_MASK_ISC
| PMCW_FLAGS_MASK_ENA
|
1379 PMCW_FLAGS_MASK_LM
| PMCW_FLAGS_MASK_MME
|
1380 PMCW_FLAGS_MASK_MP
);
1381 p
->flags
|= schib
.pmcw
.flags
&
1382 (PMCW_FLAGS_MASK_ISC
| PMCW_FLAGS_MASK_ENA
|
1383 PMCW_FLAGS_MASK_LM
| PMCW_FLAGS_MASK_MME
|
1384 PMCW_FLAGS_MASK_MP
);
1385 p
->lpm
= schib
.pmcw
.lpm
;
1386 p
->mbi
= schib
.pmcw
.mbi
;
1387 p
->pom
= schib
.pmcw
.pom
;
1388 p
->chars
&= ~(PMCW_CHARS_MASK_MBFC
| PMCW_CHARS_MASK_CSENSE
);
1389 p
->chars
|= schib
.pmcw
.chars
&
1390 (PMCW_CHARS_MASK_MBFC
| PMCW_CHARS_MASK_CSENSE
);
1391 sch
->curr_status
.mba
= schib
.mba
;
1393 /* Has the channel been disabled? */
1394 if (sch
->disable_cb
&& (oldflags
& PMCW_FLAGS_MASK_ENA
) != 0
1395 && (p
->flags
& PMCW_FLAGS_MASK_ENA
) == 0) {
1396 sch
->disable_cb(sch
);
1405 IOInstEnding
css_do_xsch(SubchDev
*sch
)
1407 SCSW
*s
= &sch
->curr_status
.scsw
;
1408 PMCW
*p
= &sch
->curr_status
.pmcw
;
1410 if (~(p
->flags
) & (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
)) {
1411 return IOINST_CC_NOT_OPERATIONAL
;
1414 if (s
->ctrl
& SCSW_CTRL_MASK_STCTL
) {
1415 return IOINST_CC_STATUS_PRESENT
;
1418 if (!(s
->ctrl
& SCSW_CTRL_MASK_FCTL
) ||
1419 ((s
->ctrl
& SCSW_CTRL_MASK_FCTL
) != SCSW_FCTL_START_FUNC
) ||
1421 (SCSW_ACTL_RESUME_PEND
| SCSW_ACTL_START_PEND
| SCSW_ACTL_SUSP
))) ||
1422 (s
->ctrl
& SCSW_ACTL_SUBCH_ACTIVE
)) {
1423 return IOINST_CC_BUSY
;
1426 /* Cancel the current operation. */
1427 s
->ctrl
&= ~(SCSW_FCTL_START_FUNC
|
1428 SCSW_ACTL_RESUME_PEND
|
1429 SCSW_ACTL_START_PEND
|
1431 sch
->channel_prog
= 0x0;
1432 sch
->last_cmd_valid
= false;
1435 return IOINST_CC_EXPECTED
;
1438 IOInstEnding
css_do_csch(SubchDev
*sch
)
1440 SCSW
*s
= &sch
->curr_status
.scsw
;
1441 PMCW
*p
= &sch
->curr_status
.pmcw
;
1443 if (~(p
->flags
) & (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
)) {
1444 return IOINST_CC_NOT_OPERATIONAL
;
1447 /* Trigger the clear function. */
1448 s
->ctrl
&= ~(SCSW_CTRL_MASK_FCTL
| SCSW_CTRL_MASK_ACTL
);
1449 s
->ctrl
|= SCSW_FCTL_CLEAR_FUNC
| SCSW_ACTL_CLEAR_PEND
;
1451 return do_subchannel_work(sch
);
1454 int css_do_hsch(SubchDev
*sch
)
1456 SCSW
*s
= &sch
->curr_status
.scsw
;
1457 PMCW
*p
= &sch
->curr_status
.pmcw
;
1460 if (~(p
->flags
) & (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
)) {
1465 if (((s
->ctrl
& SCSW_CTRL_MASK_STCTL
) == SCSW_STCTL_STATUS_PEND
) ||
1466 (s
->ctrl
& (SCSW_STCTL_PRIMARY
|
1467 SCSW_STCTL_SECONDARY
|
1468 SCSW_STCTL_ALERT
))) {
1473 if (s
->ctrl
& (SCSW_FCTL_HALT_FUNC
| SCSW_FCTL_CLEAR_FUNC
)) {
1478 /* Trigger the halt function. */
1479 s
->ctrl
|= SCSW_FCTL_HALT_FUNC
;
1480 s
->ctrl
&= ~SCSW_FCTL_START_FUNC
;
1481 if (((s
->ctrl
& SCSW_CTRL_MASK_ACTL
) ==
1482 (SCSW_ACTL_SUBCH_ACTIVE
| SCSW_ACTL_DEVICE_ACTIVE
)) &&
1483 ((s
->ctrl
& SCSW_CTRL_MASK_STCTL
) == SCSW_STCTL_INTERMEDIATE
)) {
1484 s
->ctrl
&= ~SCSW_STCTL_STATUS_PEND
;
1486 s
->ctrl
|= SCSW_ACTL_HALT_PEND
;
1488 do_subchannel_work(sch
);
1495 static void css_update_chnmon(SubchDev
*sch
)
1497 if (!(sch
->curr_status
.pmcw
.flags
& PMCW_FLAGS_MASK_MME
)) {
1501 /* The counter is conveniently located at the beginning of the struct. */
1502 if (sch
->curr_status
.pmcw
.chars
& PMCW_CHARS_MASK_MBFC
) {
1503 /* Format 1, per-subchannel area. */
1506 count
= address_space_ldl(&address_space_memory
,
1507 sch
->curr_status
.mba
,
1508 MEMTXATTRS_UNSPECIFIED
,
1511 address_space_stl(&address_space_memory
, sch
->curr_status
.mba
, count
,
1512 MEMTXATTRS_UNSPECIFIED
, NULL
);
1514 /* Format 0, global area. */
1518 offset
= sch
->curr_status
.pmcw
.mbi
<< 5;
1519 count
= address_space_lduw(&address_space_memory
,
1520 channel_subsys
.chnmon_area
+ offset
,
1521 MEMTXATTRS_UNSPECIFIED
,
1524 address_space_stw(&address_space_memory
,
1525 channel_subsys
.chnmon_area
+ offset
, count
,
1526 MEMTXATTRS_UNSPECIFIED
, NULL
);
1530 IOInstEnding
css_do_ssch(SubchDev
*sch
, ORB
*orb
)
1532 SCSW
*s
= &sch
->curr_status
.scsw
;
1533 PMCW
*p
= &sch
->curr_status
.pmcw
;
1535 if (~(p
->flags
) & (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
)) {
1536 return IOINST_CC_NOT_OPERATIONAL
;
1539 if (s
->ctrl
& SCSW_STCTL_STATUS_PEND
) {
1540 return IOINST_CC_STATUS_PRESENT
;
1543 if (s
->ctrl
& (SCSW_FCTL_START_FUNC
|
1544 SCSW_FCTL_HALT_FUNC
|
1545 SCSW_FCTL_CLEAR_FUNC
)) {
1546 return IOINST_CC_BUSY
;
1549 /* If monitoring is active, update counter. */
1550 if (channel_subsys
.chnmon_active
) {
1551 css_update_chnmon(sch
);
1554 sch
->channel_prog
= orb
->cpa
;
1555 /* Trigger the start function. */
1556 s
->ctrl
|= (SCSW_FCTL_START_FUNC
| SCSW_ACTL_START_PEND
);
1557 s
->flags
&= ~SCSW_FLAGS_MASK_PNO
;
1559 return do_subchannel_work(sch
);
1562 static void copy_irb_to_guest(IRB
*dest
, const IRB
*src
, PMCW
*pmcw
,
1566 uint16_t stctl
= src
->scsw
.ctrl
& SCSW_CTRL_MASK_STCTL
;
1567 uint16_t actl
= src
->scsw
.ctrl
& SCSW_CTRL_MASK_ACTL
;
1569 copy_scsw_to_guest(&dest
->scsw
, &src
->scsw
);
1571 for (i
= 0; i
< ARRAY_SIZE(dest
->esw
); i
++) {
1572 dest
->esw
[i
] = cpu_to_be32(src
->esw
[i
]);
1574 for (i
= 0; i
< ARRAY_SIZE(dest
->ecw
); i
++) {
1575 dest
->ecw
[i
] = cpu_to_be32(src
->ecw
[i
]);
1577 *irb_len
= sizeof(*dest
) - sizeof(dest
->emw
);
1579 /* extended measurements enabled? */
1580 if ((src
->scsw
.flags
& SCSW_FLAGS_MASK_ESWF
) ||
1581 !(pmcw
->flags
& PMCW_FLAGS_MASK_TF
) ||
1582 !(pmcw
->chars
& PMCW_CHARS_MASK_XMWME
)) {
1585 /* extended measurements pending? */
1586 if (!(stctl
& SCSW_STCTL_STATUS_PEND
)) {
1589 if ((stctl
& SCSW_STCTL_PRIMARY
) ||
1590 (stctl
== SCSW_STCTL_SECONDARY
) ||
1591 ((stctl
& SCSW_STCTL_INTERMEDIATE
) && (actl
& SCSW_ACTL_SUSP
))) {
1592 for (i
= 0; i
< ARRAY_SIZE(dest
->emw
); i
++) {
1593 dest
->emw
[i
] = cpu_to_be32(src
->emw
[i
]);
1596 *irb_len
= sizeof(*dest
);
1599 int css_do_tsch_get_irb(SubchDev
*sch
, IRB
*target_irb
, int *irb_len
)
1601 SCSW
*s
= &sch
->curr_status
.scsw
;
1602 PMCW
*p
= &sch
->curr_status
.pmcw
;
1606 if (~(p
->flags
) & (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
)) {
1610 stctl
= s
->ctrl
& SCSW_CTRL_MASK_STCTL
;
1612 /* Prepare the irb for the guest. */
1613 memset(&irb
, 0, sizeof(IRB
));
1615 /* Copy scsw from current status. */
1616 memcpy(&irb
.scsw
, s
, sizeof(SCSW
));
1617 if (stctl
& SCSW_STCTL_STATUS_PEND
) {
1618 if (s
->cstat
& (SCSW_CSTAT_DATA_CHECK
|
1619 SCSW_CSTAT_CHN_CTRL_CHK
|
1620 SCSW_CSTAT_INTF_CTRL_CHK
)) {
1621 irb
.scsw
.flags
|= SCSW_FLAGS_MASK_ESWF
;
1622 irb
.esw
[0] = 0x04804000;
1624 irb
.esw
[0] = 0x00800000;
1626 /* If a unit check is pending, copy sense data. */
1627 if ((s
->dstat
& SCSW_DSTAT_UNIT_CHECK
) &&
1628 (p
->chars
& PMCW_CHARS_MASK_CSENSE
)) {
1631 irb
.scsw
.flags
|= SCSW_FLAGS_MASK_ESWF
| SCSW_FLAGS_MASK_ECTL
;
1632 /* Attention: sense_data is already BE! */
1633 memcpy(irb
.ecw
, sch
->sense_data
, sizeof(sch
->sense_data
));
1634 for (i
= 0; i
< ARRAY_SIZE(irb
.ecw
); i
++) {
1635 irb
.ecw
[i
] = be32_to_cpu(irb
.ecw
[i
]);
1637 irb
.esw
[1] = 0x01000000 | (sizeof(sch
->sense_data
) << 8);
1640 /* Store the irb to the guest. */
1641 copy_irb_to_guest(target_irb
, &irb
, p
, irb_len
);
1643 return ((stctl
& SCSW_STCTL_STATUS_PEND
) == 0);
1646 void css_do_tsch_update_subch(SubchDev
*sch
)
1648 SCSW
*s
= &sch
->curr_status
.scsw
;
1649 PMCW
*p
= &sch
->curr_status
.pmcw
;
1654 stctl
= s
->ctrl
& SCSW_CTRL_MASK_STCTL
;
1655 fctl
= s
->ctrl
& SCSW_CTRL_MASK_FCTL
;
1656 actl
= s
->ctrl
& SCSW_CTRL_MASK_ACTL
;
1658 /* Clear conditions on subchannel, if applicable. */
1659 if (stctl
& SCSW_STCTL_STATUS_PEND
) {
1660 s
->ctrl
&= ~SCSW_CTRL_MASK_STCTL
;
1661 if ((stctl
!= (SCSW_STCTL_INTERMEDIATE
| SCSW_STCTL_STATUS_PEND
)) ||
1662 ((fctl
& SCSW_FCTL_HALT_FUNC
) &&
1663 (actl
& SCSW_ACTL_SUSP
))) {
1664 s
->ctrl
&= ~SCSW_CTRL_MASK_FCTL
;
1666 if (stctl
!= (SCSW_STCTL_INTERMEDIATE
| SCSW_STCTL_STATUS_PEND
)) {
1667 s
->flags
&= ~SCSW_FLAGS_MASK_PNO
;
1668 s
->ctrl
&= ~(SCSW_ACTL_RESUME_PEND
|
1669 SCSW_ACTL_START_PEND
|
1670 SCSW_ACTL_HALT_PEND
|
1671 SCSW_ACTL_CLEAR_PEND
|
1674 if ((actl
& SCSW_ACTL_SUSP
) &&
1675 (fctl
& SCSW_FCTL_START_FUNC
)) {
1676 s
->flags
&= ~SCSW_FLAGS_MASK_PNO
;
1677 if (fctl
& SCSW_FCTL_HALT_FUNC
) {
1678 s
->ctrl
&= ~(SCSW_ACTL_RESUME_PEND
|
1679 SCSW_ACTL_START_PEND
|
1680 SCSW_ACTL_HALT_PEND
|
1681 SCSW_ACTL_CLEAR_PEND
|
1684 s
->ctrl
&= ~SCSW_ACTL_RESUME_PEND
;
1688 /* Clear pending sense data. */
1689 if (p
->chars
& PMCW_CHARS_MASK_CSENSE
) {
1690 memset(sch
->sense_data
, 0 , sizeof(sch
->sense_data
));
1695 static void copy_crw_to_guest(CRW
*dest
, const CRW
*src
)
1697 dest
->flags
= cpu_to_be16(src
->flags
);
1698 dest
->rsid
= cpu_to_be16(src
->rsid
);
1701 int css_do_stcrw(CRW
*crw
)
1703 CrwContainer
*crw_cont
;
1706 crw_cont
= QTAILQ_FIRST(&channel_subsys
.pending_crws
);
1708 QTAILQ_REMOVE(&channel_subsys
.pending_crws
, crw_cont
, sibling
);
1709 copy_crw_to_guest(crw
, &crw_cont
->crw
);
1713 /* List was empty, turn crw machine checks on again. */
1714 memset(crw
, 0, sizeof(*crw
));
1715 channel_subsys
.do_crw_mchk
= true;
1722 static void copy_crw_from_guest(CRW
*dest
, const CRW
*src
)
1724 dest
->flags
= be16_to_cpu(src
->flags
);
1725 dest
->rsid
= be16_to_cpu(src
->rsid
);
1728 void css_undo_stcrw(CRW
*crw
)
1730 CrwContainer
*crw_cont
;
1732 crw_cont
= g_try_new0(CrwContainer
, 1);
1734 channel_subsys
.crws_lost
= true;
1737 copy_crw_from_guest(&crw_cont
->crw
, crw
);
1739 QTAILQ_INSERT_HEAD(&channel_subsys
.pending_crws
, crw_cont
, sibling
);
1742 int css_do_tpi(IOIntCode
*int_code
, int lowcore
)
1744 /* No pending interrupts for !KVM. */
1748 int css_collect_chp_desc(int m
, uint8_t cssid
, uint8_t f_chpid
, uint8_t l_chpid
,
1749 int rfmt
, void *buf
)
1753 uint32_t chpid_type_word
;
1757 css
= channel_subsys
.css
[channel_subsys
.default_cssid
];
1759 css
= channel_subsys
.css
[cssid
];
1765 for (i
= f_chpid
; i
<= l_chpid
; i
++) {
1766 if (css
->chpids
[i
].in_use
) {
1767 chpid_type_word
= 0x80000000 | (css
->chpids
[i
].type
<< 8) | i
;
1769 words
[0] = cpu_to_be32(chpid_type_word
);
1771 memcpy(buf
+ desc_size
, words
, 8);
1773 } else if (rfmt
== 1) {
1774 words
[0] = cpu_to_be32(chpid_type_word
);
1782 memcpy(buf
+ desc_size
, words
, 32);
1790 void css_do_schm(uint8_t mbk
, int update
, int dct
, uint64_t mbo
)
1792 /* dct is currently ignored (not really meaningful for our devices) */
1793 /* TODO: Don't ignore mbk. */
1794 if (update
&& !channel_subsys
.chnmon_active
) {
1795 /* Enable measuring. */
1796 channel_subsys
.chnmon_area
= mbo
;
1797 channel_subsys
.chnmon_active
= true;
1799 if (!update
&& channel_subsys
.chnmon_active
) {
1800 /* Disable measuring. */
1801 channel_subsys
.chnmon_area
= 0;
1802 channel_subsys
.chnmon_active
= false;
1806 IOInstEnding
css_do_rsch(SubchDev
*sch
)
1808 SCSW
*s
= &sch
->curr_status
.scsw
;
1809 PMCW
*p
= &sch
->curr_status
.pmcw
;
1811 if (~(p
->flags
) & (PMCW_FLAGS_MASK_DNV
| PMCW_FLAGS_MASK_ENA
)) {
1812 return IOINST_CC_NOT_OPERATIONAL
;
1815 if (s
->ctrl
& SCSW_STCTL_STATUS_PEND
) {
1816 return IOINST_CC_STATUS_PRESENT
;
1819 if (((s
->ctrl
& SCSW_CTRL_MASK_FCTL
) != SCSW_FCTL_START_FUNC
) ||
1820 (s
->ctrl
& SCSW_ACTL_RESUME_PEND
) ||
1821 (!(s
->ctrl
& SCSW_ACTL_SUSP
))) {
1822 return IOINST_CC_BUSY
;
1825 /* If monitoring is active, update counter. */
1826 if (channel_subsys
.chnmon_active
) {
1827 css_update_chnmon(sch
);
1830 s
->ctrl
|= SCSW_ACTL_RESUME_PEND
;
1831 return do_subchannel_work(sch
);
1834 int css_do_rchp(uint8_t cssid
, uint8_t chpid
)
1838 if (cssid
> channel_subsys
.max_cssid
) {
1841 if (channel_subsys
.max_cssid
== 0) {
1842 real_cssid
= channel_subsys
.default_cssid
;
1846 if (!channel_subsys
.css
[real_cssid
]) {
1850 if (!channel_subsys
.css
[real_cssid
]->chpids
[chpid
].in_use
) {
1854 if (!channel_subsys
.css
[real_cssid
]->chpids
[chpid
].is_virtual
) {
1856 "rchp unsupported for non-virtual chpid %x.%02x!\n",
1861 /* We don't really use a channel path, so we're done here. */
1862 css_queue_crw(CRW_RSC_CHP
, CRW_ERC_INIT
, 1,
1863 channel_subsys
.max_cssid
> 0 ? 1 : 0, chpid
);
1864 if (channel_subsys
.max_cssid
> 0) {
1865 css_queue_crw(CRW_RSC_CHP
, CRW_ERC_INIT
, 1, 0, real_cssid
<< 8);
1870 bool css_schid_final(int m
, uint8_t cssid
, uint8_t ssid
, uint16_t schid
)
1875 real_cssid
= (!m
&& (cssid
== 0)) ? channel_subsys
.default_cssid
: cssid
;
1876 if (ssid
> MAX_SSID
||
1877 !channel_subsys
.css
[real_cssid
] ||
1878 !channel_subsys
.css
[real_cssid
]->sch_set
[ssid
]) {
1881 set
= channel_subsys
.css
[real_cssid
]->sch_set
[ssid
];
1882 return schid
> find_last_bit(set
->schids_used
,
1883 (MAX_SCHID
+ 1) / sizeof(unsigned long));
1886 unsigned int css_find_free_chpid(uint8_t cssid
)
1888 CssImage
*css
= channel_subsys
.css
[cssid
];
1892 return MAX_CHPID
+ 1;
1895 for (chpid
= 0; chpid
<= MAX_CHPID
; chpid
++) {
1896 /* skip reserved chpid */
1897 if (chpid
== VIRTIO_CCW_CHPID
) {
1900 if (!css
->chpids
[chpid
].in_use
) {
1904 return MAX_CHPID
+ 1;
1907 static int css_add_chpid(uint8_t cssid
, uint8_t chpid
, uint8_t type
,
1912 trace_css_chpid_add(cssid
, chpid
, type
);
1913 css
= channel_subsys
.css
[cssid
];
1917 if (css
->chpids
[chpid
].in_use
) {
1920 css
->chpids
[chpid
].in_use
= 1;
1921 css
->chpids
[chpid
].type
= type
;
1922 css
->chpids
[chpid
].is_virtual
= is_virt
;
1924 css_generate_chp_crws(cssid
, chpid
);
1929 void css_sch_build_virtual_schib(SubchDev
*sch
, uint8_t chpid
, uint8_t type
)
1931 PMCW
*p
= &sch
->curr_status
.pmcw
;
1932 SCSW
*s
= &sch
->curr_status
.scsw
;
1934 CssImage
*css
= channel_subsys
.css
[sch
->cssid
];
1936 assert(css
!= NULL
);
1937 memset(p
, 0, sizeof(PMCW
));
1938 p
->flags
|= PMCW_FLAGS_MASK_DNV
;
1939 p
->devno
= sch
->devno
;
1944 p
->chpid
[0] = chpid
;
1945 if (!css
->chpids
[chpid
].in_use
) {
1946 css_add_chpid(sch
->cssid
, chpid
, type
, true);
1949 memset(s
, 0, sizeof(SCSW
));
1950 sch
->curr_status
.mba
= 0;
1951 for (i
= 0; i
< ARRAY_SIZE(sch
->curr_status
.mda
); i
++) {
1952 sch
->curr_status
.mda
[i
] = 0;
1956 SubchDev
*css_find_subch(uint8_t m
, uint8_t cssid
, uint8_t ssid
, uint16_t schid
)
1960 real_cssid
= (!m
&& (cssid
== 0)) ? channel_subsys
.default_cssid
: cssid
;
1962 if (!channel_subsys
.css
[real_cssid
]) {
1966 if (!channel_subsys
.css
[real_cssid
]->sch_set
[ssid
]) {
1970 return channel_subsys
.css
[real_cssid
]->sch_set
[ssid
]->sch
[schid
];
1974 * Return free device number in subchannel set.
1976 * Return index of the first free device number in the subchannel set
1977 * identified by @p cssid and @p ssid, beginning the search at @p
1978 * start and wrapping around at MAX_DEVNO. Return a value exceeding
1979 * MAX_SCHID if there are no free device numbers in the subchannel
1982 static uint32_t css_find_free_devno(uint8_t cssid
, uint8_t ssid
,
1987 for (round
= 0; round
<= MAX_DEVNO
; round
++) {
1988 uint16_t devno
= (start
+ round
) % MAX_DEVNO
;
1990 if (!css_devno_used(cssid
, ssid
, devno
)) {
1994 return MAX_DEVNO
+ 1;
1998 * Return first free subchannel (id) in subchannel set.
2000 * Return index of the first free subchannel in the subchannel set
2001 * identified by @p cssid and @p ssid, if there is any. Return a value
2002 * exceeding MAX_SCHID if there are no free subchannels in the
2005 static uint32_t css_find_free_subch(uint8_t cssid
, uint8_t ssid
)
2009 for (schid
= 0; schid
<= MAX_SCHID
; schid
++) {
2010 if (!css_find_subch(1, cssid
, ssid
, schid
)) {
2014 return MAX_SCHID
+ 1;
2018 * Return first free subchannel (id) in subchannel set for a device number
2020 * Verify the device number @p devno is not used yet in the subchannel
2021 * set identified by @p cssid and @p ssid. Set @p schid to the index
2022 * of the first free subchannel in the subchannel set, if there is
2023 * any. Return true if everything succeeded and false otherwise.
2025 static bool css_find_free_subch_for_devno(uint8_t cssid
, uint8_t ssid
,
2026 uint16_t devno
, uint16_t *schid
,
2029 uint32_t free_schid
;
2032 if (css_devno_used(cssid
, ssid
, devno
)) {
2033 error_setg(errp
, "Device %x.%x.%04x already exists",
2034 cssid
, ssid
, devno
);
2037 free_schid
= css_find_free_subch(cssid
, ssid
);
2038 if (free_schid
> MAX_SCHID
) {
2039 error_setg(errp
, "No free subchannel found for %x.%x.%04x",
2040 cssid
, ssid
, devno
);
2043 *schid
= free_schid
;
2048 * Return first free subchannel (id) and device number
2050 * Locate the first free subchannel and first free device number in
2051 * any of the subchannel sets of the channel subsystem identified by
2052 * @p cssid. Return false if no free subchannel / device number could
2053 * be found. Otherwise set @p ssid, @p devno and @p schid to identify
2054 * the available subchannel and device number and return true.
2056 * May modify @p ssid, @p devno and / or @p schid even if no free
2057 * subchannel / device number could be found.
2059 static bool css_find_free_subch_and_devno(uint8_t cssid
, uint8_t *ssid
,
2060 uint16_t *devno
, uint16_t *schid
,
2063 uint32_t free_schid
, free_devno
;
2065 assert(ssid
&& devno
&& schid
);
2066 for (*ssid
= 0; *ssid
<= MAX_SSID
; (*ssid
)++) {
2067 free_schid
= css_find_free_subch(cssid
, *ssid
);
2068 if (free_schid
> MAX_SCHID
) {
2071 free_devno
= css_find_free_devno(cssid
, *ssid
, free_schid
);
2072 if (free_devno
> MAX_DEVNO
) {
2075 *schid
= free_schid
;
2076 *devno
= free_devno
;
2079 error_setg(errp
, "Virtual channel subsystem is full!");
2083 bool css_subch_visible(SubchDev
*sch
)
2085 if (sch
->ssid
> channel_subsys
.max_ssid
) {
2089 if (sch
->cssid
!= channel_subsys
.default_cssid
) {
2090 return (channel_subsys
.max_cssid
> 0);
2096 bool css_present(uint8_t cssid
)
2098 return (channel_subsys
.css
[cssid
] != NULL
);
2101 bool css_devno_used(uint8_t cssid
, uint8_t ssid
, uint16_t devno
)
2103 if (!channel_subsys
.css
[cssid
]) {
2106 if (!channel_subsys
.css
[cssid
]->sch_set
[ssid
]) {
2110 return !!test_bit(devno
,
2111 channel_subsys
.css
[cssid
]->sch_set
[ssid
]->devnos_used
);
2114 void css_subch_assign(uint8_t cssid
, uint8_t ssid
, uint16_t schid
,
2115 uint16_t devno
, SubchDev
*sch
)
2120 trace_css_assign_subch(sch
? "assign" : "deassign", cssid
, ssid
, schid
,
2122 if (!channel_subsys
.css
[cssid
]) {
2124 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n",
2125 __func__
, cssid
, ssid
, schid
);
2128 css
= channel_subsys
.css
[cssid
];
2130 if (!css
->sch_set
[ssid
]) {
2131 css
->sch_set
[ssid
] = g_new0(SubchSet
, 1);
2133 s_set
= css
->sch_set
[ssid
];
2135 s_set
->sch
[schid
] = sch
;
2137 set_bit(schid
, s_set
->schids_used
);
2138 set_bit(devno
, s_set
->devnos_used
);
2140 clear_bit(schid
, s_set
->schids_used
);
2141 clear_bit(devno
, s_set
->devnos_used
);
2145 void css_queue_crw(uint8_t rsc
, uint8_t erc
, int solicited
,
2146 int chain
, uint16_t rsid
)
2148 CrwContainer
*crw_cont
;
2150 trace_css_crw(rsc
, erc
, rsid
, chain
? "(chained)" : "");
2151 /* TODO: Maybe use a static crw pool? */
2152 crw_cont
= g_try_new0(CrwContainer
, 1);
2154 channel_subsys
.crws_lost
= true;
2157 crw_cont
->crw
.flags
= (rsc
<< 8) | erc
;
2159 crw_cont
->crw
.flags
|= CRW_FLAGS_MASK_S
;
2162 crw_cont
->crw
.flags
|= CRW_FLAGS_MASK_C
;
2164 crw_cont
->crw
.rsid
= rsid
;
2165 if (channel_subsys
.crws_lost
) {
2166 crw_cont
->crw
.flags
|= CRW_FLAGS_MASK_R
;
2167 channel_subsys
.crws_lost
= false;
2170 QTAILQ_INSERT_TAIL(&channel_subsys
.pending_crws
, crw_cont
, sibling
);
2172 if (channel_subsys
.do_crw_mchk
) {
2173 channel_subsys
.do_crw_mchk
= false;
2174 /* Inject crw pending machine check. */
2179 void css_generate_sch_crws(uint8_t cssid
, uint8_t ssid
, uint16_t schid
,
2180 int hotplugged
, int add
)
2182 uint8_t guest_cssid
;
2185 if (add
&& !hotplugged
) {
2188 if (channel_subsys
.max_cssid
== 0) {
2189 /* Default cssid shows up as 0. */
2190 guest_cssid
= (cssid
== channel_subsys
.default_cssid
) ? 0 : cssid
;
2192 /* Show real cssid to the guest. */
2193 guest_cssid
= cssid
;
2196 * Only notify for higher subchannel sets/channel subsystems if the
2197 * guest has enabled it.
2199 if ((ssid
> channel_subsys
.max_ssid
) ||
2200 (guest_cssid
> channel_subsys
.max_cssid
) ||
2201 ((channel_subsys
.max_cssid
== 0) &&
2202 (cssid
!= channel_subsys
.default_cssid
))) {
2205 chain_crw
= (channel_subsys
.max_ssid
> 0) ||
2206 (channel_subsys
.max_cssid
> 0);
2207 css_queue_crw(CRW_RSC_SUBCH
, CRW_ERC_IPI
, 0, chain_crw
? 1 : 0, schid
);
2209 css_queue_crw(CRW_RSC_SUBCH
, CRW_ERC_IPI
, 0, 0,
2210 (guest_cssid
<< 8) | (ssid
<< 4));
2212 /* RW_ERC_IPI --> clear pending interrupts */
2213 css_clear_io_interrupt(css_do_build_subchannel_id(cssid
, ssid
), schid
);
2216 void css_generate_chp_crws(uint8_t cssid
, uint8_t chpid
)
2221 void css_generate_css_crws(uint8_t cssid
)
2223 if (!channel_subsys
.sei_pending
) {
2224 css_queue_crw(CRW_RSC_CSS
, CRW_ERC_EVENT
, 0, 0, cssid
);
2226 channel_subsys
.sei_pending
= true;
2229 void css_clear_sei_pending(void)
2231 channel_subsys
.sei_pending
= false;
2234 int css_enable_mcsse(void)
2236 trace_css_enable_facility("mcsse");
2237 channel_subsys
.max_cssid
= MAX_CSSID
;
2241 int css_enable_mss(void)
2243 trace_css_enable_facility("mss");
2244 channel_subsys
.max_ssid
= MAX_SSID
;
2248 void css_reset_sch(SubchDev
*sch
)
2250 PMCW
*p
= &sch
->curr_status
.pmcw
;
2252 if ((p
->flags
& PMCW_FLAGS_MASK_ENA
) != 0 && sch
->disable_cb
) {
2253 sch
->disable_cb(sch
);
2257 p
->flags
&= ~(PMCW_FLAGS_MASK_ISC
| PMCW_FLAGS_MASK_ENA
|
2258 PMCW_FLAGS_MASK_LM
| PMCW_FLAGS_MASK_MME
|
2259 PMCW_FLAGS_MASK_MP
| PMCW_FLAGS_MASK_TF
);
2260 p
->flags
|= PMCW_FLAGS_MASK_DNV
;
2261 p
->devno
= sch
->devno
;
2269 p
->chars
&= ~(PMCW_CHARS_MASK_MBFC
| PMCW_CHARS_MASK_XMWME
|
2270 PMCW_CHARS_MASK_CSENSE
);
2272 memset(&sch
->curr_status
.scsw
, 0, sizeof(sch
->curr_status
.scsw
));
2273 sch
->curr_status
.mba
= 0;
2275 sch
->channel_prog
= 0x0;
2276 sch
->last_cmd_valid
= false;
2277 sch
->thinint_active
= false;
2280 void css_reset(void)
2282 CrwContainer
*crw_cont
;
2284 /* Clean up monitoring. */
2285 channel_subsys
.chnmon_active
= false;
2286 channel_subsys
.chnmon_area
= 0;
2288 /* Clear pending CRWs. */
2289 while ((crw_cont
= QTAILQ_FIRST(&channel_subsys
.pending_crws
))) {
2290 QTAILQ_REMOVE(&channel_subsys
.pending_crws
, crw_cont
, sibling
);
2293 channel_subsys
.sei_pending
= false;
2294 channel_subsys
.do_crw_mchk
= true;
2295 channel_subsys
.crws_lost
= false;
2297 /* Reset maximum ids. */
2298 channel_subsys
.max_cssid
= 0;
2299 channel_subsys
.max_ssid
= 0;
2302 static void get_css_devid(Object
*obj
, Visitor
*v
, const char *name
,
2303 void *opaque
, Error
**errp
)
2305 DeviceState
*dev
= DEVICE(obj
);
2306 Property
*prop
= opaque
;
2307 CssDevId
*dev_id
= qdev_get_prop_ptr(dev
, prop
);
2308 char buffer
[] = "xx.x.xxxx";
2312 if (dev_id
->valid
) {
2314 r
= snprintf(buffer
, sizeof(buffer
), "%02x.%1x.%04x", dev_id
->cssid
,
2315 dev_id
->ssid
, dev_id
->devid
);
2316 assert(r
== sizeof(buffer
) - 1);
2318 /* drop leading zero */
2319 if (dev_id
->cssid
<= 0xf) {
2323 snprintf(buffer
, sizeof(buffer
), "<unset>");
2326 visit_type_str(v
, name
, &p
, errp
);
2330 * parse <cssid>.<ssid>.<devid> and assert valid range for cssid/ssid
2332 static void set_css_devid(Object
*obj
, Visitor
*v
, const char *name
,
2333 void *opaque
, Error
**errp
)
2335 DeviceState
*dev
= DEVICE(obj
);
2336 Property
*prop
= opaque
;
2337 CssDevId
*dev_id
= qdev_get_prop_ptr(dev
, prop
);
2338 Error
*local_err
= NULL
;
2341 unsigned int cssid
, ssid
, devid
;
2343 if (dev
->realized
) {
2344 qdev_prop_set_after_realize(dev
, name
, errp
);
2348 visit_type_str(v
, name
, &str
, &local_err
);
2350 error_propagate(errp
, local_err
);
2354 num
= sscanf(str
, "%2x.%1x%n.%4x%n", &cssid
, &ssid
, &n1
, &devid
, &n2
);
2355 if (num
!= 3 || (n2
- n1
) != 5 || strlen(str
) != n2
) {
2356 error_set_from_qdev_prop_error(errp
, EINVAL
, dev
, prop
, str
);
2359 if ((cssid
> MAX_CSSID
) || (ssid
> MAX_SSID
)) {
2360 error_setg(errp
, "Invalid cssid or ssid: cssid %x, ssid %x",
2365 dev_id
->cssid
= cssid
;
2366 dev_id
->ssid
= ssid
;
2367 dev_id
->devid
= devid
;
2368 dev_id
->valid
= true;
2374 const PropertyInfo css_devid_propinfo
= {
2376 .description
= "Identifier of an I/O device in the channel "
2377 "subsystem, example: fe.1.23ab",
2378 .get
= get_css_devid
,
2379 .set
= set_css_devid
,
2382 const PropertyInfo css_devid_ro_propinfo
= {
2384 .description
= "Read-only identifier of an I/O device in the channel "
2385 "subsystem, example: fe.1.23ab",
2386 .get
= get_css_devid
,
2389 SubchDev
*css_create_sch(CssDevId bus_id
, bool is_virtual
, bool squash_mcss
,
2396 if (is_virtual
!= (bus_id
.cssid
== VIRTUAL_CSSID
)) {
2397 error_setg(errp
, "cssid %hhx not valid for %s devices",
2399 (is_virtual
? "virtual" : "non-virtual"));
2406 bus_id
.cssid
= channel_subsys
.default_cssid
;
2407 } else if (!channel_subsys
.css
[bus_id
.cssid
]) {
2408 css_create_css_image(bus_id
.cssid
, false);
2411 if (!css_find_free_subch_for_devno(bus_id
.cssid
, bus_id
.ssid
,
2412 bus_id
.devid
, &schid
, errp
)) {
2415 } else if (squash_mcss
|| is_virtual
) {
2416 bus_id
.cssid
= channel_subsys
.default_cssid
;
2418 if (!css_find_free_subch_and_devno(bus_id
.cssid
, &bus_id
.ssid
,
2419 &bus_id
.devid
, &schid
, errp
)) {
2423 for (bus_id
.cssid
= 0; bus_id
.cssid
< MAX_CSSID
; ++bus_id
.cssid
) {
2424 if (bus_id
.cssid
== VIRTUAL_CSSID
) {
2428 if (!channel_subsys
.css
[bus_id
.cssid
]) {
2429 css_create_css_image(bus_id
.cssid
, false);
2432 if (css_find_free_subch_and_devno(bus_id
.cssid
, &bus_id
.ssid
,
2433 &bus_id
.devid
, &schid
,
2437 if (bus_id
.cssid
== MAX_CSSID
) {
2438 error_setg(errp
, "Virtual channel subsystem is full!");
2444 sch
= g_new0(SubchDev
, 1);
2445 sch
->cssid
= bus_id
.cssid
;
2446 sch
->ssid
= bus_id
.ssid
;
2447 sch
->devno
= bus_id
.devid
;
2449 css_subch_assign(sch
->cssid
, sch
->ssid
, schid
, sch
->devno
, sch
);
2453 static int css_sch_get_chpids(SubchDev
*sch
, CssDevId
*dev_id
)
2459 PMCW
*p
= &sch
->curr_status
.pmcw
;
2461 fid_path
= g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/chpids",
2462 dev_id
->cssid
, dev_id
->ssid
, dev_id
->devid
);
2463 fd
= fopen(fid_path
, "r");
2465 error_report("%s: open %s failed", __func__
, fid_path
);
2470 if (fscanf(fd
, "%x %x %x %x %x %x %x %x",
2471 &chpid
[0], &chpid
[1], &chpid
[2], &chpid
[3],
2472 &chpid
[4], &chpid
[5], &chpid
[6], &chpid
[7]) != 8) {
2478 for (i
= 0; i
< ARRAY_SIZE(p
->chpid
); i
++) {
2479 p
->chpid
[i
] = chpid
[i
];
2488 static int css_sch_get_path_masks(SubchDev
*sch
, CssDevId
*dev_id
)
2492 uint32_t pim
, pam
, pom
;
2493 PMCW
*p
= &sch
->curr_status
.pmcw
;
2495 fid_path
= g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/pimpampom",
2496 dev_id
->cssid
, dev_id
->ssid
, dev_id
->devid
);
2497 fd
= fopen(fid_path
, "r");
2499 error_report("%s: open %s failed", __func__
, fid_path
);
2504 if (fscanf(fd
, "%x %x %x", &pim
, &pam
, &pom
) != 3) {
2519 static int css_sch_get_chpid_type(uint8_t chpid
, uint32_t *type
,
2525 fid_path
= g_strdup_printf("/sys/devices/css%x/chp0.%02x/type",
2526 dev_id
->cssid
, chpid
);
2527 fd
= fopen(fid_path
, "r");
2529 error_report("%s: open %s failed", __func__
, fid_path
);
2534 if (fscanf(fd
, "%x", type
) != 1) {
2547 * We currently retrieve the real device information from sysfs to build the
2548 * guest subchannel information block without considering the migration feature.
2549 * We need to revisit this problem when we want to add migration support.
2551 int css_sch_build_schib(SubchDev
*sch
, CssDevId
*dev_id
)
2553 CssImage
*css
= channel_subsys
.css
[sch
->cssid
];
2554 PMCW
*p
= &sch
->curr_status
.pmcw
;
2555 SCSW
*s
= &sch
->curr_status
.scsw
;
2559 assert(css
!= NULL
);
2560 memset(p
, 0, sizeof(PMCW
));
2561 p
->flags
|= PMCW_FLAGS_MASK_DNV
;
2562 /* We are dealing with I/O subchannels only. */
2563 p
->devno
= sch
->devno
;
2565 /* Grab path mask from sysfs. */
2566 ret
= css_sch_get_path_masks(sch
, dev_id
);
2571 /* Grab chpids from sysfs. */
2572 ret
= css_sch_get_chpids(sch
, dev_id
);
2577 /* Build chpid type. */
2578 for (i
= 0; i
< ARRAY_SIZE(p
->chpid
); i
++) {
2579 if (p
->chpid
[i
] && !css
->chpids
[p
->chpid
[i
]].in_use
) {
2580 ret
= css_sch_get_chpid_type(p
->chpid
[i
], &type
, dev_id
);
2584 css_add_chpid(sch
->cssid
, p
->chpid
[i
], type
, false);
2588 memset(s
, 0, sizeof(SCSW
));
2589 sch
->curr_status
.mba
= 0;
2590 for (i
= 0; i
< ARRAY_SIZE(sch
->curr_status
.mda
); i
++) {
2591 sch
->curr_status
.mda
[i
] = 0;