4 * Copyright 2014 IBM Corp.
5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
6 * Hong Bo Li <lihbbj@cn.ibm.com>
7 * Yi Min Zhao <zyimin@cn.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or (at
10 * your option) any later version. See the COPYING file in the top-level
14 #include "qemu/osdep.h"
15 #include "qemu-common.h"
17 #include "s390-pci-bus.h"
18 #include <hw/pci/pci_bus.h>
19 #include <hw/pci/msi.h>
20 #include <qemu/error-report.h>
22 /* #define DEBUG_S390PCI_BUS */
23 #ifdef DEBUG_S390PCI_BUS
24 #define DPRINTF(fmt, ...) \
25 do { fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); } while (0)
27 #define DPRINTF(fmt, ...) \
31 int chsc_sei_nt2_get_event(void *res
)
33 ChscSeiNt2Res
*nt2_res
= (ChscSeiNt2Res
*)res
;
37 SeiContainer
*sei_cont
;
38 S390pciState
*s
= S390_PCI_HOST_BRIDGE(
39 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE
, NULL
));
45 sei_cont
= QTAILQ_FIRST(&s
->pending_sei
);
47 QTAILQ_REMOVE(&s
->pending_sei
, sei_cont
, link
);
49 nt2_res
->cc
= sei_cont
->cc
;
50 nt2_res
->length
= cpu_to_be16(sizeof(ChscSeiNt2Res
));
51 switch (sei_cont
->cc
) {
52 case 1: /* error event */
53 eccdf
= (PciCcdfErr
*)nt2_res
->ccdf
;
54 eccdf
->fid
= cpu_to_be32(sei_cont
->fid
);
55 eccdf
->fh
= cpu_to_be32(sei_cont
->fh
);
56 eccdf
->e
= cpu_to_be32(sei_cont
->e
);
57 eccdf
->faddr
= cpu_to_be64(sei_cont
->faddr
);
58 eccdf
->pec
= cpu_to_be16(sei_cont
->pec
);
60 case 2: /* availability event */
61 accdf
= (PciCcdfAvail
*)nt2_res
->ccdf
;
62 accdf
->fid
= cpu_to_be32(sei_cont
->fid
);
63 accdf
->fh
= cpu_to_be32(sei_cont
->fh
);
64 accdf
->pec
= cpu_to_be16(sei_cont
->pec
);
76 int chsc_sei_nt2_have_event(void)
78 S390pciState
*s
= S390_PCI_HOST_BRIDGE(
79 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE
, NULL
));
85 return !QTAILQ_EMPTY(&s
->pending_sei
);
88 S390PCIBusDevice
*s390_pci_find_dev_by_fid(uint32_t fid
)
90 S390PCIBusDevice
*pbdev
;
92 S390pciState
*s
= S390_PCI_HOST_BRIDGE(
93 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE
, NULL
));
99 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
100 pbdev
= &s
->pbdev
[i
];
101 if ((pbdev
->fh
!= 0) && (pbdev
->fid
== fid
)) {
109 void s390_pci_sclp_configure(int configure
, SCCB
*sccb
)
111 PciCfgSccb
*psccb
= (PciCfgSccb
*)sccb
;
112 S390PCIBusDevice
*pbdev
= s390_pci_find_dev_by_fid(be32_to_cpu(psccb
->aid
));
116 if ((configure
== 1 && pbdev
->configured
== true) ||
117 (configure
== 0 && pbdev
->configured
== false)) {
118 rc
= SCLP_RC_NO_ACTION_REQUIRED
;
120 pbdev
->configured
= !pbdev
->configured
;
121 rc
= SCLP_RC_NORMAL_COMPLETION
;
124 DPRINTF("sclp config %d no dev found\n", configure
);
125 rc
= SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED
;
128 psccb
->header
.response_code
= cpu_to_be16(rc
);
131 static uint32_t s390_pci_get_pfid(PCIDevice
*pdev
)
133 return PCI_SLOT(pdev
->devfn
);
136 static uint32_t s390_pci_get_pfh(PCIDevice
*pdev
)
138 return PCI_SLOT(pdev
->devfn
) | FH_VIRT
;
141 S390PCIBusDevice
*s390_pci_find_dev_by_idx(uint32_t idx
)
143 S390PCIBusDevice
*pbdev
;
146 S390pciState
*s
= S390_PCI_HOST_BRIDGE(
147 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE
, NULL
));
153 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
154 pbdev
= &s
->pbdev
[i
];
156 if (pbdev
->fh
== 0) {
169 S390PCIBusDevice
*s390_pci_find_dev_by_fh(uint32_t fh
)
171 S390PCIBusDevice
*pbdev
;
173 S390pciState
*s
= S390_PCI_HOST_BRIDGE(
174 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE
, NULL
));
180 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
181 pbdev
= &s
->pbdev
[i
];
182 if (pbdev
->fh
== fh
) {
190 static void s390_pci_generate_event(uint8_t cc
, uint16_t pec
, uint32_t fh
,
191 uint32_t fid
, uint64_t faddr
, uint32_t e
)
193 SeiContainer
*sei_cont
;
194 S390pciState
*s
= S390_PCI_HOST_BRIDGE(
195 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE
, NULL
));
201 sei_cont
= g_malloc0(sizeof(SeiContainer
));
206 sei_cont
->faddr
= faddr
;
209 QTAILQ_INSERT_TAIL(&s
->pending_sei
, sei_cont
, link
);
210 css_generate_css_crws(0);
213 static void s390_pci_generate_plug_event(uint16_t pec
, uint32_t fh
,
216 s390_pci_generate_event(2, pec
, fh
, fid
, 0, 0);
219 static void s390_pci_generate_error_event(uint16_t pec
, uint32_t fh
,
220 uint32_t fid
, uint64_t faddr
,
223 s390_pci_generate_event(1, pec
, fh
, fid
, faddr
, e
);
226 static void s390_pci_set_irq(void *opaque
, int irq
, int level
)
231 static int s390_pci_map_irq(PCIDevice
*pci_dev
, int irq_num
)
237 static uint64_t s390_pci_get_table_origin(uint64_t iota
)
239 return iota
& ~ZPCI_IOTA_RTTO_FLAG
;
242 static unsigned int calc_rtx(dma_addr_t ptr
)
244 return ((unsigned long) ptr
>> ZPCI_RT_SHIFT
) & ZPCI_INDEX_MASK
;
247 static unsigned int calc_sx(dma_addr_t ptr
)
249 return ((unsigned long) ptr
>> ZPCI_ST_SHIFT
) & ZPCI_INDEX_MASK
;
252 static unsigned int calc_px(dma_addr_t ptr
)
254 return ((unsigned long) ptr
>> PAGE_SHIFT
) & ZPCI_PT_MASK
;
257 static uint64_t get_rt_sto(uint64_t entry
)
259 return ((entry
& ZPCI_TABLE_TYPE_MASK
) == ZPCI_TABLE_TYPE_RTX
)
260 ? (entry
& ZPCI_RTE_ADDR_MASK
)
264 static uint64_t get_st_pto(uint64_t entry
)
266 return ((entry
& ZPCI_TABLE_TYPE_MASK
) == ZPCI_TABLE_TYPE_SX
)
267 ? (entry
& ZPCI_STE_ADDR_MASK
)
271 static uint64_t s390_guest_io_table_walk(uint64_t guest_iota
,
272 uint64_t guest_dma_address
)
274 uint64_t sto_a
, pto_a
, px_a
;
275 uint64_t sto
, pto
, pte
;
276 uint32_t rtx
, sx
, px
;
278 rtx
= calc_rtx(guest_dma_address
);
279 sx
= calc_sx(guest_dma_address
);
280 px
= calc_px(guest_dma_address
);
282 sto_a
= guest_iota
+ rtx
* sizeof(uint64_t);
283 sto
= address_space_ldq(&address_space_memory
, sto_a
,
284 MEMTXATTRS_UNSPECIFIED
, NULL
);
285 sto
= get_rt_sto(sto
);
291 pto_a
= sto
+ sx
* sizeof(uint64_t);
292 pto
= address_space_ldq(&address_space_memory
, pto_a
,
293 MEMTXATTRS_UNSPECIFIED
, NULL
);
294 pto
= get_st_pto(pto
);
300 px_a
= pto
+ px
* sizeof(uint64_t);
301 pte
= address_space_ldq(&address_space_memory
, px_a
,
302 MEMTXATTRS_UNSPECIFIED
, NULL
);
308 static IOMMUTLBEntry
s390_translate_iommu(MemoryRegion
*iommu
, hwaddr addr
,
313 S390PCIBusDevice
*pbdev
= container_of(iommu
, S390PCIBusDevice
, iommu_mr
);
315 IOMMUTLBEntry ret
= {
316 .target_as
= &address_space_memory
,
318 .translated_addr
= 0,
319 .addr_mask
= ~(hwaddr
)0,
323 if (!pbdev
->configured
|| !pbdev
->pdev
|| !(pbdev
->fh
& FH_ENABLED
)) {
327 DPRINTF("iommu trans addr 0x%" PRIx64
"\n", addr
);
329 s
= S390_PCI_HOST_BRIDGE(pci_device_root_bus(pbdev
->pdev
)->qbus
.parent
);
330 /* s390 does not have an APIC mapped to main storage so we use
331 * a separate AddressSpace only for msix notifications
333 if (addr
== ZPCI_MSI_ADDR
) {
334 ret
.target_as
= &s
->msix_notify_as
;
336 ret
.translated_addr
= addr
;
337 ret
.addr_mask
= 0xfff;
342 if (!pbdev
->g_iota
) {
343 pbdev
->error_state
= true;
344 pbdev
->lgstg_blocked
= true;
345 s390_pci_generate_error_event(ERR_EVENT_INVALAS
, pbdev
->fh
, pbdev
->fid
,
350 if (addr
< pbdev
->pba
|| addr
> pbdev
->pal
) {
351 pbdev
->error_state
= true;
352 pbdev
->lgstg_blocked
= true;
353 s390_pci_generate_error_event(ERR_EVENT_OORANGE
, pbdev
->fh
, pbdev
->fid
,
358 pte
= s390_guest_io_table_walk(s390_pci_get_table_origin(pbdev
->g_iota
),
362 pbdev
->error_state
= true;
363 pbdev
->lgstg_blocked
= true;
364 s390_pci_generate_error_event(ERR_EVENT_SERR
, pbdev
->fh
, pbdev
->fid
,
365 addr
, ERR_EVENT_Q_BIT
);
369 flags
= pte
& ZPCI_PTE_FLAG_MASK
;
371 ret
.translated_addr
= pte
& ZPCI_PTE_ADDR_MASK
;
372 ret
.addr_mask
= 0xfff;
374 if (flags
& ZPCI_PTE_INVALID
) {
375 ret
.perm
= IOMMU_NONE
;
383 static const MemoryRegionIOMMUOps s390_iommu_ops
= {
384 .translate
= s390_translate_iommu
,
387 static AddressSpace
*s390_pci_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
389 S390pciState
*s
= opaque
;
391 return &s
->pbdev
[PCI_SLOT(devfn
)].as
;
394 static uint8_t set_ind_atomic(uint64_t ind_loc
, uint8_t to_be_set
)
396 uint8_t ind_old
, ind_new
;
400 ind_addr
= cpu_physical_memory_map(ind_loc
, &len
, 1);
402 s390_pci_generate_error_event(ERR_EVENT_AIRERR
, 0, 0, 0, 0);
407 ind_new
= ind_old
| to_be_set
;
408 } while (atomic_cmpxchg(ind_addr
, ind_old
, ind_new
) != ind_old
);
409 cpu_physical_memory_unmap(ind_addr
, len
, 1, len
);
414 static void s390_msi_ctrl_write(void *opaque
, hwaddr addr
, uint64_t data
,
417 S390PCIBusDevice
*pbdev
;
418 uint32_t io_int_word
;
419 uint32_t fid
= data
>> ZPCI_MSI_VEC_BITS
;
420 uint32_t vec
= data
& ZPCI_MSI_VEC_MASK
;
425 DPRINTF("write_msix data 0x%" PRIx64
" fid %d vec 0x%x\n", data
, fid
, vec
);
427 pbdev
= s390_pci_find_dev_by_fid(fid
);
429 e
|= (vec
<< ERR_EVENT_MVN_OFFSET
);
430 s390_pci_generate_error_event(ERR_EVENT_NOMSI
, 0, fid
, addr
, e
);
434 if (!(pbdev
->fh
& FH_ENABLED
)) {
438 ind_bit
= pbdev
->routes
.adapter
.ind_offset
;
439 sum_bit
= pbdev
->routes
.adapter
.summary_offset
;
441 set_ind_atomic(pbdev
->routes
.adapter
.ind_addr
+ (ind_bit
+ vec
) / 8,
442 0x80 >> ((ind_bit
+ vec
) % 8));
443 if (!set_ind_atomic(pbdev
->routes
.adapter
.summary_addr
+ sum_bit
/ 8,
444 0x80 >> (sum_bit
% 8))) {
445 io_int_word
= (pbdev
->isc
<< 27) | IO_INT_WORD_AI
;
446 s390_io_interrupt(0, 0, 0, io_int_word
);
450 static uint64_t s390_msi_ctrl_read(void *opaque
, hwaddr addr
, unsigned size
)
455 static const MemoryRegionOps s390_msi_ctrl_ops
= {
456 .write
= s390_msi_ctrl_write
,
457 .read
= s390_msi_ctrl_read
,
458 .endianness
= DEVICE_LITTLE_ENDIAN
,
461 void s390_pcihost_iommu_configure(S390PCIBusDevice
*pbdev
, bool enable
)
463 pbdev
->configured
= false;
466 uint64_t size
= pbdev
->pal
- pbdev
->pba
+ 1;
467 memory_region_init_iommu(&pbdev
->iommu_mr
, OBJECT(&pbdev
->mr
),
468 &s390_iommu_ops
, "iommu-s390", size
);
469 memory_region_add_subregion(&pbdev
->mr
, pbdev
->pba
, &pbdev
->iommu_mr
);
471 memory_region_del_subregion(&pbdev
->mr
, &pbdev
->iommu_mr
);
474 pbdev
->configured
= true;
477 static void s390_pcihost_init_as(S390pciState
*s
)
480 S390PCIBusDevice
*pbdev
;
482 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
483 pbdev
= &s
->pbdev
[i
];
484 memory_region_init(&pbdev
->mr
, OBJECT(s
),
485 "iommu-root-s390", UINT64_MAX
);
486 address_space_init(&pbdev
->as
, &pbdev
->mr
, "iommu-pci");
489 memory_region_init_io(&s
->msix_notify_mr
, OBJECT(s
),
490 &s390_msi_ctrl_ops
, s
, "msix-s390", UINT64_MAX
);
491 address_space_init(&s
->msix_notify_as
, &s
->msix_notify_mr
, "msix-pci");
494 static int s390_pcihost_init(SysBusDevice
*dev
)
498 PCIHostState
*phb
= PCI_HOST_BRIDGE(dev
);
499 S390pciState
*s
= S390_PCI_HOST_BRIDGE(dev
);
501 DPRINTF("host_init\n");
503 b
= pci_register_bus(DEVICE(dev
), NULL
,
504 s390_pci_set_irq
, s390_pci_map_irq
, NULL
,
505 get_system_memory(), get_system_io(), 0, 64,
507 s390_pcihost_init_as(s
);
508 pci_setup_iommu(b
, s390_pci_dma_iommu
, s
);
511 qbus_set_hotplug_handler(bus
, DEVICE(dev
), NULL
);
513 QTAILQ_INIT(&s
->pending_sei
);
517 static int s390_pcihost_setup_msix(S390PCIBusDevice
*pbdev
)
523 pos
= pci_find_capability(pbdev
->pdev
, PCI_CAP_ID_MSIX
);
525 pbdev
->msix
.available
= false;
529 ctrl
= pci_host_config_read_common(pbdev
->pdev
, pos
+ PCI_MSIX_FLAGS
,
530 pci_config_size(pbdev
->pdev
), sizeof(ctrl
));
531 table
= pci_host_config_read_common(pbdev
->pdev
, pos
+ PCI_MSIX_TABLE
,
532 pci_config_size(pbdev
->pdev
), sizeof(table
));
533 pba
= pci_host_config_read_common(pbdev
->pdev
, pos
+ PCI_MSIX_PBA
,
534 pci_config_size(pbdev
->pdev
), sizeof(pba
));
536 pbdev
->msix
.table_bar
= table
& PCI_MSIX_FLAGS_BIRMASK
;
537 pbdev
->msix
.table_offset
= table
& ~PCI_MSIX_FLAGS_BIRMASK
;
538 pbdev
->msix
.pba_bar
= pba
& PCI_MSIX_FLAGS_BIRMASK
;
539 pbdev
->msix
.pba_offset
= pba
& ~PCI_MSIX_FLAGS_BIRMASK
;
540 pbdev
->msix
.entries
= (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
541 pbdev
->msix
.available
= true;
545 static void s390_pcihost_hot_plug(HotplugHandler
*hotplug_dev
,
546 DeviceState
*dev
, Error
**errp
)
548 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
549 S390PCIBusDevice
*pbdev
;
550 S390pciState
*s
= S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev
)
553 pbdev
= &s
->pbdev
[PCI_SLOT(pci_dev
->devfn
)];
555 pbdev
->fid
= s390_pci_get_pfid(pci_dev
);
556 pbdev
->pdev
= pci_dev
;
557 pbdev
->configured
= true;
558 pbdev
->fh
= s390_pci_get_pfh(pci_dev
);
560 s390_pcihost_setup_msix(pbdev
);
562 if (dev
->hotplugged
) {
563 s390_pci_generate_plug_event(HP_EVENT_RESERVED_TO_STANDBY
,
564 pbdev
->fh
, pbdev
->fid
);
565 s390_pci_generate_plug_event(HP_EVENT_TO_CONFIGURED
,
566 pbdev
->fh
, pbdev
->fid
);
570 static void s390_pcihost_hot_unplug(HotplugHandler
*hotplug_dev
,
571 DeviceState
*dev
, Error
**errp
)
573 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
574 S390pciState
*s
= S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev
)
576 S390PCIBusDevice
*pbdev
= &s
->pbdev
[PCI_SLOT(pci_dev
->devfn
)];
578 if (pbdev
->configured
) {
579 pbdev
->configured
= false;
580 s390_pci_generate_plug_event(HP_EVENT_CONFIGURED_TO_STBRES
,
581 pbdev
->fh
, pbdev
->fid
);
584 s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED
,
585 pbdev
->fh
, pbdev
->fid
);
589 object_unparent(OBJECT(pci_dev
));
592 static void s390_pcihost_class_init(ObjectClass
*klass
, void *data
)
594 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
595 DeviceClass
*dc
= DEVICE_CLASS(klass
);
596 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(klass
);
598 dc
->cannot_instantiate_with_device_add_yet
= true;
599 k
->init
= s390_pcihost_init
;
600 hc
->plug
= s390_pcihost_hot_plug
;
601 hc
->unplug
= s390_pcihost_hot_unplug
;
602 msi_nonbroken
= true;
605 static const TypeInfo s390_pcihost_info
= {
606 .name
= TYPE_S390_PCI_HOST_BRIDGE
,
607 .parent
= TYPE_PCI_HOST_BRIDGE
,
608 .instance_size
= sizeof(S390pciState
),
609 .class_init
= s390_pcihost_class_init
,
610 .interfaces
= (InterfaceInfo
[]) {
611 { TYPE_HOTPLUG_HANDLER
},
616 static void s390_pci_register_types(void)
618 type_register_static(&s390_pcihost_info
);
621 type_init(s390_pci_register_types
)