hw/s390x/s390-pci-bus.c

   1 /*
   2  * s390 PCI BUS
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #include "s390-pci-bus.h"
  15 #include <hw/pci/pci_bus.h>
  16 #include <hw/pci/msi.h>
  17 #include <qemu/error-report.h>
  18
  19 /* #define DEBUG_S390PCI_BUS */
  20 #ifdef DEBUG_S390PCI_BUS
  21 #define DPRINTF(fmt, ...) \
  22     do { fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); } while (0)
  23 #else
  24 #define DPRINTF(fmt, ...) \
  25     do { } while (0)
  26 #endif
  27
  28 int chsc_sei_nt2_get_event(void *res)
  29 {
  30     ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res;
  31     PciCcdfAvail *accdf;
  32     PciCcdfErr *eccdf;
  33     int rc = 1;
  34     SeiContainer *sei_cont;
  35     S390pciState *s = S390_PCI_HOST_BRIDGE(
  36         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  37
  38     if (!s) {
  39         return rc;
  40     }
  41
  42     sei_cont = QTAILQ_FIRST(&s->pending_sei);
  43     if (sei_cont) {
  44         QTAILQ_REMOVE(&s->pending_sei, sei_cont, link);
  45         nt2_res->nt = 2;
  46         nt2_res->cc = sei_cont->cc;
  47         switch (sei_cont->cc) {
  48         case 1: /* error event */
  49             eccdf = (PciCcdfErr *)nt2_res->ccdf;
  50             eccdf->fid = cpu_to_be32(sei_cont->fid);
  51             eccdf->fh = cpu_to_be32(sei_cont->fh);
  52             eccdf->e = cpu_to_be32(sei_cont->e);
  53             eccdf->faddr = cpu_to_be64(sei_cont->faddr);
  54             eccdf->pec = cpu_to_be16(sei_cont->pec);
  55             break;
  56         case 2: /* availability event */
  57             accdf = (PciCcdfAvail *)nt2_res->ccdf;
  58             accdf->fid = cpu_to_be32(sei_cont->fid);
  59             accdf->fh = cpu_to_be32(sei_cont->fh);
  60             accdf->pec = cpu_to_be16(sei_cont->pec);
  61             break;
  62         default:
  63             abort();
  64         }
  65         g_free(sei_cont);
  66         rc = 0;
  67     }
  68
  69     return rc;
  70 }
  71
  72 int chsc_sei_nt2_have_event(void)
  73 {
  74     S390pciState *s = S390_PCI_HOST_BRIDGE(
  75         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  76
  77     if (!s) {
  78         return 0;
  79     }
  80
  81     return !QTAILQ_EMPTY(&s->pending_sei);
  82 }
  83
  84 S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid)
  85 {
  86     S390PCIBusDevice *pbdev;
  87     int i;
  88     S390pciState *s = S390_PCI_HOST_BRIDGE(
  89         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  90
  91     if (!s) {
  92         return NULL;
  93     }
  94
  95     for (i = 0; i < PCI_SLOT_MAX; i++) {
  96         pbdev = &s->pbdev[i];
  97         if ((pbdev->fh != 0) && (pbdev->fid == fid)) {
  98             return pbdev;
  99         }
 100     }
 101
 102     return NULL;
 103 }
 104
 105 void s390_pci_sclp_configure(int configure, SCCB *sccb)
 106 {
 107     PciCfgSccb *psccb = (PciCfgSccb *)sccb;
 108     S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(be32_to_cpu(psccb->aid));
 109     uint16_t rc;
 110
 111     if (pbdev) {
 112         if ((configure == 1 && pbdev->configured == true) ||
 113             (configure == 0 && pbdev->configured == false)) {
 114             rc = SCLP_RC_NO_ACTION_REQUIRED;
 115         } else {
 116             pbdev->configured = !pbdev->configured;
 117             rc = SCLP_RC_NORMAL_COMPLETION;
 118         }
 119     } else {
 120         DPRINTF("sclp config %d no dev found\n", configure);
 121         rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
 122     }
 123
 124     psccb->header.response_code = cpu_to_be16(rc);
 125     return;
 126 }
 127
 128 static uint32_t s390_pci_get_pfid(PCIDevice *pdev)
 129 {
 130     return PCI_SLOT(pdev->devfn);
 131 }
 132
 133 static uint32_t s390_pci_get_pfh(PCIDevice *pdev)
 134 {
 135     return PCI_SLOT(pdev->devfn) | FH_VIRT;
 136 }
 137
 138 S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx)
 139 {
 140     S390PCIBusDevice *pbdev;
 141     int i;
 142     int j = 0;
 143     S390pciState *s = S390_PCI_HOST_BRIDGE(
 144         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 145
 146     if (!s) {
 147         return NULL;
 148     }
 149
 150     for (i = 0; i < PCI_SLOT_MAX; i++) {
 151         pbdev = &s->pbdev[i];
 152
 153         if (pbdev->fh == 0) {
 154             continue;
 155         }
 156
 157         if (j == idx) {
 158             return pbdev;
 159         }
 160         j++;
 161     }
 162
 163     return NULL;
 164 }
 165
 166 S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh)
 167 {
 168     S390PCIBusDevice *pbdev;
 169     int i;
 170     S390pciState *s = S390_PCI_HOST_BRIDGE(
 171         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 172
 173     if (!s) {
 174         return NULL;
 175     }
 176
 177     for (i = 0; i < PCI_SLOT_MAX; i++) {
 178         pbdev = &s->pbdev[i];
 179         if (pbdev->fh == fh) {
 180             return pbdev;
 181         }
 182     }
 183
 184     return NULL;
 185 }
 186
 187 static void s390_pci_generate_event(uint8_t cc, uint16_t pec, uint32_t fh,
 188                                     uint32_t fid, uint64_t faddr, uint32_t e)
 189 {
 190     SeiContainer *sei_cont = g_malloc0(sizeof(SeiContainer));
 191     S390pciState *s = S390_PCI_HOST_BRIDGE(
 192         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 193
 194     if (!s) {
 195         return;
 196     }
 197
 198     sei_cont->fh = fh;
 199     sei_cont->fid = fid;
 200     sei_cont->cc = cc;
 201     sei_cont->pec = pec;
 202     sei_cont->faddr = faddr;
 203     sei_cont->e = e;
 204
 205     QTAILQ_INSERT_TAIL(&s->pending_sei, sei_cont, link);
 206     css_generate_css_crws(0);
 207 }
 208
 209 static void s390_pci_generate_plug_event(uint16_t pec, uint32_t fh,
 210                                          uint32_t fid)
 211 {
 212     s390_pci_generate_event(2, pec, fh, fid, 0, 0);
 213 }
 214
 215 static void s390_pci_generate_error_event(uint16_t pec, uint32_t fh,
 216                                           uint32_t fid, uint64_t faddr,
 217                                           uint32_t e)
 218 {
 219     s390_pci_generate_event(1, pec, fh, fid, faddr, e);
 220 }
 221
 222 static void s390_pci_set_irq(void *opaque, int irq, int level)
 223 {
 224     /* nothing to do */
 225 }
 226
 227 static int s390_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 228 {
 229     /* nothing to do */
 230     return 0;
 231 }
 232
 233 static uint64_t s390_pci_get_table_origin(uint64_t iota)
 234 {
 235     return iota & ~ZPCI_IOTA_RTTO_FLAG;
 236 }
 237
 238 static unsigned int calc_rtx(dma_addr_t ptr)
 239 {
 240     return ((unsigned long) ptr >> ZPCI_RT_SHIFT) & ZPCI_INDEX_MASK;
 241 }
 242
 243 static unsigned int calc_sx(dma_addr_t ptr)
 244 {
 245     return ((unsigned long) ptr >> ZPCI_ST_SHIFT) & ZPCI_INDEX_MASK;
 246 }
 247
 248 static unsigned int calc_px(dma_addr_t ptr)
 249 {
 250     return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK;
 251 }
 252
 253 static uint64_t get_rt_sto(uint64_t entry)
 254 {
 255     return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX)
 256                 ? (entry & ZPCI_RTE_ADDR_MASK)
 257                 : 0;
 258 }
 259
 260 static uint64_t get_st_pto(uint64_t entry)
 261 {
 262     return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX)
 263             ? (entry & ZPCI_STE_ADDR_MASK)
 264             : 0;
 265 }
 266
 267 static uint64_t s390_guest_io_table_walk(uint64_t guest_iota,
 268                                   uint64_t guest_dma_address)
 269 {
 270     uint64_t sto_a, pto_a, px_a;
 271     uint64_t sto, pto, pte;
 272     uint32_t rtx, sx, px;
 273
 274     rtx = calc_rtx(guest_dma_address);
 275     sx = calc_sx(guest_dma_address);
 276     px = calc_px(guest_dma_address);
 277
 278     sto_a = guest_iota + rtx * sizeof(uint64_t);
 279     sto = ldq_phys(&address_space_memory, sto_a);
 280     sto = get_rt_sto(sto);
 281     if (!sto) {
 282         pte = 0;
 283         goto out;
 284     }
 285
 286     pto_a = sto + sx * sizeof(uint64_t);
 287     pto = ldq_phys(&address_space_memory, pto_a);
 288     pto = get_st_pto(pto);
 289     if (!pto) {
 290         pte = 0;
 291         goto out;
 292     }
 293
 294     px_a = pto + px * sizeof(uint64_t);
 295     pte = ldq_phys(&address_space_memory, px_a);
 296
 297 out:
 298     return pte;
 299 }
 300
 301 static IOMMUTLBEntry s390_translate_iommu(MemoryRegion *iommu, hwaddr addr,
 302                                           bool is_write)
 303 {
 304     uint64_t pte;
 305     uint32_t flags;
 306     S390PCIBusDevice *pbdev = container_of(iommu, S390PCIBusDevice, mr);
 307     S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pbdev->pdev)
 308                                            ->qbus.parent);
 309     IOMMUTLBEntry ret = {
 310         .target_as = &address_space_memory,
 311         .iova = 0,
 312         .translated_addr = 0,
 313         .addr_mask = ~(hwaddr)0,
 314         .perm = IOMMU_NONE,
 315     };
 316
 317     DPRINTF("iommu trans addr 0x%" PRIx64 "\n", addr);
 318
 319     /* s390 does not have an APIC mapped to main storage so we use
 320      * a separate AddressSpace only for msix notifications
 321      */
 322     if (addr == ZPCI_MSI_ADDR) {
 323         ret.target_as = &s->msix_notify_as;
 324         ret.iova = addr;
 325         ret.translated_addr = addr;
 326         ret.addr_mask = 0xfff;
 327         ret.perm = IOMMU_RW;
 328         return ret;
 329     }
 330
 331     if (!pbdev->g_iota) {
 332         pbdev->error_state = true;
 333         pbdev->lgstg_blocked = true;
 334         s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid,
 335                                       addr, 0);
 336         return ret;
 337     }
 338
 339     if (addr < pbdev->pba || addr > pbdev->pal) {
 340         pbdev->error_state = true;
 341         pbdev->lgstg_blocked = true;
 342         s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid,
 343                                       addr, 0);
 344         return ret;
 345     }
 346
 347     pte = s390_guest_io_table_walk(s390_pci_get_table_origin(pbdev->g_iota),
 348                                    addr);
 349
 350     if (!pte) {
 351         pbdev->error_state = true;
 352         pbdev->lgstg_blocked = true;
 353         s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid,
 354                                       addr, ERR_EVENT_Q_BIT);
 355         return ret;
 356     }
 357
 358     flags = pte & ZPCI_PTE_FLAG_MASK;
 359     ret.iova = addr;
 360     ret.translated_addr = pte & ZPCI_PTE_ADDR_MASK;
 361     ret.addr_mask = 0xfff;
 362
 363     if (flags & ZPCI_PTE_INVALID) {
 364         ret.perm = IOMMU_NONE;
 365     } else {
 366         ret.perm = IOMMU_RW;
 367     }
 368
 369     return ret;
 370 }
 371
 372 static const MemoryRegionIOMMUOps s390_iommu_ops = {
 373     .translate = s390_translate_iommu,
 374 };
 375
 376 static AddressSpace *s390_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
 377 {
 378     S390pciState *s = opaque;
 379
 380     return &s->pbdev[PCI_SLOT(devfn)].as;
 381 }
 382
 383 static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set)
 384 {
 385     uint8_t ind_old, ind_new;
 386     hwaddr len = 1;
 387     uint8_t *ind_addr;
 388
 389     ind_addr = cpu_physical_memory_map(ind_loc, &len, 1);
 390     if (!ind_addr) {
 391         s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0);
 392         return -1;
 393     }
 394     do {
 395         ind_old = *ind_addr;
 396         ind_new = ind_old | to_be_set;
 397     } while (atomic_cmpxchg(ind_addr, ind_old, ind_new) != ind_old);
 398     cpu_physical_memory_unmap(ind_addr, len, 1, len);
 399
 400     return ind_old;
 401 }
 402
 403 static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data,
 404                                 unsigned int size)
 405 {
 406     S390PCIBusDevice *pbdev;
 407     uint32_t io_int_word;
 408     uint32_t fid = data >> ZPCI_MSI_VEC_BITS;
 409     uint32_t vec = data & ZPCI_MSI_VEC_MASK;
 410     uint64_t ind_bit;
 411     uint32_t sum_bit;
 412     uint32_t e = 0;
 413
 414     DPRINTF("write_msix data 0x%" PRIx64 " fid %d vec 0x%x\n", data, fid, vec);
 415
 416     pbdev = s390_pci_find_dev_by_fid(fid);
 417     if (!pbdev) {
 418         e |= (vec << ERR_EVENT_MVN_OFFSET);
 419         s390_pci_generate_error_event(ERR_EVENT_NOMSI, 0, fid, addr, e);
 420         return;
 421     }
 422
 423     ind_bit = pbdev->routes.adapter.ind_offset;
 424     sum_bit = pbdev->routes.adapter.summary_offset;
 425
 426     set_ind_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8,
 427                    0x80 >> ((ind_bit + vec) % 8));
 428     if (!set_ind_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8,
 429                                        0x80 >> (sum_bit % 8))) {
 430         io_int_word = (pbdev->isc << 27) | IO_INT_WORD_AI;
 431         s390_io_interrupt(0, 0, 0, io_int_word);
 432     }
 433
 434     return;
 435 }
 436
 437 static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr addr, unsigned size)
 438 {
 439     return 0xffffffff;
 440 }
 441
 442 static const MemoryRegionOps s390_msi_ctrl_ops = {
 443     .write = s390_msi_ctrl_write,
 444     .read = s390_msi_ctrl_read,
 445     .endianness = DEVICE_LITTLE_ENDIAN,
 446 };
 447
 448 static void s390_pcihost_init_as(S390pciState *s)
 449 {
 450     int i;
 451
 452     for (i = 0; i < PCI_SLOT_MAX; i++) {
 453         memory_region_init_iommu(&s->pbdev[i].mr, OBJECT(s),
 454                                  &s390_iommu_ops, "iommu-s390", UINT64_MAX);
 455         address_space_init(&s->pbdev[i].as, &s->pbdev[i].mr, "iommu-pci");
 456     }
 457
 458     memory_region_init_io(&s->msix_notify_mr, OBJECT(s),
 459                           &s390_msi_ctrl_ops, s, "msix-s390", UINT64_MAX);
 460     address_space_init(&s->msix_notify_as, &s->msix_notify_mr, "msix-pci");
 461 }
 462
 463 static int s390_pcihost_init(SysBusDevice *dev)
 464 {
 465     PCIBus *b;
 466     BusState *bus;
 467     PCIHostState *phb = PCI_HOST_BRIDGE(dev);
 468     S390pciState *s = S390_PCI_HOST_BRIDGE(dev);
 469
 470     DPRINTF("host_init\n");
 471
 472     b = pci_register_bus(DEVICE(dev), NULL,
 473                          s390_pci_set_irq, s390_pci_map_irq, NULL,
 474                          get_system_memory(), get_system_io(), 0, 64,
 475                          TYPE_PCI_BUS);
 476     s390_pcihost_init_as(s);
 477     pci_setup_iommu(b, s390_pci_dma_iommu, s);
 478
 479     bus = BUS(b);
 480     qbus_set_hotplug_handler(bus, DEVICE(dev), NULL);
 481     phb->bus = b;
 482     QTAILQ_INIT(&s->pending_sei);
 483     return 0;
 484 }
 485
 486 static int s390_pcihost_setup_msix(S390PCIBusDevice *pbdev)
 487 {
 488     uint8_t pos;
 489     uint16_t ctrl;
 490     uint32_t table, pba;
 491
 492     pos = pci_find_capability(pbdev->pdev, PCI_CAP_ID_MSIX);
 493     if (!pos) {
 494         pbdev->msix.available = false;
 495         return 0;
 496     }
 497
 498     ctrl = pci_host_config_read_common(pbdev->pdev, pos + PCI_CAP_FLAGS,
 499              pci_config_size(pbdev->pdev), sizeof(ctrl));
 500     table = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_TABLE,
 501              pci_config_size(pbdev->pdev), sizeof(table));
 502     pba = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_PBA,
 503              pci_config_size(pbdev->pdev), sizeof(pba));
 504
 505     pbdev->msix.table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
 506     pbdev->msix.table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
 507     pbdev->msix.pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
 508     pbdev->msix.pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
 509     pbdev->msix.entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
 510     pbdev->msix.available = true;
 511     return 0;
 512 }
 513
 514 static void s390_pcihost_hot_plug(HotplugHandler *hotplug_dev,
 515                                   DeviceState *dev, Error **errp)
 516 {
 517     PCIDevice *pci_dev = PCI_DEVICE(dev);
 518     S390PCIBusDevice *pbdev;
 519     S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
 520                                            ->qbus.parent);
 521
 522     pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
 523
 524     pbdev->fid = s390_pci_get_pfid(pci_dev);
 525     pbdev->pdev = pci_dev;
 526     pbdev->configured = true;
 527     pbdev->fh = s390_pci_get_pfh(pci_dev);
 528
 529     s390_pcihost_setup_msix(pbdev);
 530
 531     if (dev->hotplugged) {
 532         s390_pci_generate_plug_event(HP_EVENT_RESERVED_TO_STANDBY,
 533                                      pbdev->fh, pbdev->fid);
 534         s390_pci_generate_plug_event(HP_EVENT_TO_CONFIGURED,
 535                                      pbdev->fh, pbdev->fid);
 536     }
 537     return;
 538 }
 539
 540 static void s390_pcihost_hot_unplug(HotplugHandler *hotplug_dev,
 541                                     DeviceState *dev, Error **errp)
 542 {
 543     PCIDevice *pci_dev = PCI_DEVICE(dev);
 544     S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
 545                                            ->qbus.parent);
 546     S390PCIBusDevice *pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
 547
 548     if (pbdev->configured) {
 549         pbdev->configured = false;
 550         s390_pci_generate_plug_event(HP_EVENT_CONFIGURED_TO_STBRES,
 551                                      pbdev->fh, pbdev->fid);
 552     }
 553
 554     s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED,
 555                                  pbdev->fh, pbdev->fid);
 556     pbdev->fh = 0;
 557     pbdev->fid = 0;
 558     pbdev->pdev = NULL;
 559     object_unparent(OBJECT(pci_dev));
 560 }
 561
 562 static void s390_pcihost_class_init(ObjectClass *klass, void *data)
 563 {
 564     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 565     DeviceClass *dc = DEVICE_CLASS(klass);
 566     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 567
 568     dc->cannot_instantiate_with_device_add_yet = true;
 569     k->init = s390_pcihost_init;
 570     hc->plug = s390_pcihost_hot_plug;
 571     hc->unplug = s390_pcihost_hot_unplug;
 572     msi_supported = true;
 573 }
 574
 575 static const TypeInfo s390_pcihost_info = {
 576     .name          = TYPE_S390_PCI_HOST_BRIDGE,
 577     .parent        = TYPE_PCI_HOST_BRIDGE,
 578     .instance_size = sizeof(S390pciState),
 579     .class_init    = s390_pcihost_class_init,
 580     .interfaces = (InterfaceInfo[]) {
 581         { TYPE_HOTPLUG_HANDLER },
 582         { }
 583     }
 584 };
 585
 586 static void s390_pci_register_types(void)
 587 {
 588     type_register_static(&s390_pcihost_info);
 589 }
 590
 591 type_init(s390_pci_register_types)