hw/s390x/s390-pci-bus.c

   1 /*
   2  * s390 PCI BUS
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu-common.h"
  16 #include "cpu.h"
  17 #include "s390-pci-bus.h"
  18 #include <hw/pci/pci_bus.h>
  19 #include <hw/pci/msi.h>
  20 #include <qemu/error-report.h>
  21
  22 /* #define DEBUG_S390PCI_BUS */
  23 #ifdef DEBUG_S390PCI_BUS
  24 #define DPRINTF(fmt, ...) \
  25     do { fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); } while (0)
  26 #else
  27 #define DPRINTF(fmt, ...) \
  28     do { } while (0)
  29 #endif
  30
  31 int chsc_sei_nt2_get_event(void *res)
  32 {
  33     ChscSeiNt2Res *nt2_res = (ChscSeiNt2Res *)res;
  34     PciCcdfAvail *accdf;
  35     PciCcdfErr *eccdf;
  36     int rc = 1;
  37     SeiContainer *sei_cont;
  38     S390pciState *s = S390_PCI_HOST_BRIDGE(
  39         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  40
  41     if (!s) {
  42         return rc;
  43     }
  44
  45     sei_cont = QTAILQ_FIRST(&s->pending_sei);
  46     if (sei_cont) {
  47         QTAILQ_REMOVE(&s->pending_sei, sei_cont, link);
  48         nt2_res->nt = 2;
  49         nt2_res->cc = sei_cont->cc;
  50         nt2_res->length = cpu_to_be16(sizeof(ChscSeiNt2Res));
  51         switch (sei_cont->cc) {
  52         case 1: /* error event */
  53             eccdf = (PciCcdfErr *)nt2_res->ccdf;
  54             eccdf->fid = cpu_to_be32(sei_cont->fid);
  55             eccdf->fh = cpu_to_be32(sei_cont->fh);
  56             eccdf->e = cpu_to_be32(sei_cont->e);
  57             eccdf->faddr = cpu_to_be64(sei_cont->faddr);
  58             eccdf->pec = cpu_to_be16(sei_cont->pec);
  59             break;
  60         case 2: /* availability event */
  61             accdf = (PciCcdfAvail *)nt2_res->ccdf;
  62             accdf->fid = cpu_to_be32(sei_cont->fid);
  63             accdf->fh = cpu_to_be32(sei_cont->fh);
  64             accdf->pec = cpu_to_be16(sei_cont->pec);
  65             break;
  66         default:
  67             abort();
  68         }
  69         g_free(sei_cont);
  70         rc = 0;
  71     }
  72
  73     return rc;
  74 }
  75
  76 int chsc_sei_nt2_have_event(void)
  77 {
  78     S390pciState *s = S390_PCI_HOST_BRIDGE(
  79         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  80
  81     if (!s) {
  82         return 0;
  83     }
  84
  85     return !QTAILQ_EMPTY(&s->pending_sei);
  86 }
  87
  88 S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid)
  89 {
  90     S390PCIBusDevice *pbdev;
  91     int i;
  92     S390pciState *s = S390_PCI_HOST_BRIDGE(
  93         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
  94
  95     if (!s) {
  96         return NULL;
  97     }
  98
  99     for (i = 0; i < PCI_SLOT_MAX; i++) {
 100         pbdev = &s->pbdev[i];
 101         if ((pbdev->fh != 0) && (pbdev->fid == fid)) {
 102             return pbdev;
 103         }
 104     }
 105
 106     return NULL;
 107 }
 108
 109 void s390_pci_sclp_configure(SCCB *sccb)
 110 {
 111     PciCfgSccb *psccb = (PciCfgSccb *)sccb;
 112     S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(be32_to_cpu(psccb->aid));
 113     uint16_t rc;
 114
 115     if (pbdev) {
 116         if (pbdev->configured) {
 117             rc = SCLP_RC_NO_ACTION_REQUIRED;
 118         } else {
 119             pbdev->configured = true;
 120             rc = SCLP_RC_NORMAL_COMPLETION;
 121         }
 122     } else {
 123         DPRINTF("sclp config no dev found\n");
 124         rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
 125     }
 126
 127     psccb->header.response_code = cpu_to_be16(rc);
 128 }
 129
 130 void s390_pci_sclp_deconfigure(SCCB *sccb)
 131 {
 132     PciCfgSccb *psccb = (PciCfgSccb *)sccb;
 133     S390PCIBusDevice *pbdev = s390_pci_find_dev_by_fid(be32_to_cpu(psccb->aid));
 134     uint16_t rc;
 135
 136     if (pbdev) {
 137         if (!pbdev->configured) {
 138             rc = SCLP_RC_NO_ACTION_REQUIRED;
 139         } else {
 140             pbdev->configured = false;
 141             rc = SCLP_RC_NORMAL_COMPLETION;
 142         }
 143     } else {
 144         DPRINTF("sclp deconfig no dev found\n");
 145         rc = SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED;
 146     }
 147
 148     psccb->header.response_code = cpu_to_be16(rc);
 149 }
 150
 151 static uint32_t s390_pci_get_pfid(PCIDevice *pdev)
 152 {
 153     return PCI_SLOT(pdev->devfn);
 154 }
 155
 156 static uint32_t s390_pci_get_pfh(PCIDevice *pdev)
 157 {
 158     return PCI_SLOT(pdev->devfn) | FH_VIRT;
 159 }
 160
 161 S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx)
 162 {
 163     S390PCIBusDevice *pbdev;
 164     int i;
 165     int j = 0;
 166     S390pciState *s = S390_PCI_HOST_BRIDGE(
 167         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 168
 169     if (!s) {
 170         return NULL;
 171     }
 172
 173     for (i = 0; i < PCI_SLOT_MAX; i++) {
 174         pbdev = &s->pbdev[i];
 175
 176         if (pbdev->fh == 0) {
 177             continue;
 178         }
 179
 180         if (j == idx) {
 181             return pbdev;
 182         }
 183         j++;
 184     }
 185
 186     return NULL;
 187 }
 188
 189 S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh)
 190 {
 191     S390PCIBusDevice *pbdev;
 192     int i;
 193     S390pciState *s = S390_PCI_HOST_BRIDGE(
 194         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 195
 196     if (!s || !fh) {
 197         return NULL;
 198     }
 199
 200     for (i = 0; i < PCI_SLOT_MAX; i++) {
 201         pbdev = &s->pbdev[i];
 202         if (pbdev->fh == fh) {
 203             return pbdev;
 204         }
 205     }
 206
 207     return NULL;
 208 }
 209
 210 static void s390_pci_generate_event(uint8_t cc, uint16_t pec, uint32_t fh,
 211                                     uint32_t fid, uint64_t faddr, uint32_t e)
 212 {
 213     SeiContainer *sei_cont;
 214     S390pciState *s = S390_PCI_HOST_BRIDGE(
 215         object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE, NULL));
 216
 217     if (!s) {
 218         return;
 219     }
 220
 221     sei_cont = g_malloc0(sizeof(SeiContainer));
 222     sei_cont->fh = fh;
 223     sei_cont->fid = fid;
 224     sei_cont->cc = cc;
 225     sei_cont->pec = pec;
 226     sei_cont->faddr = faddr;
 227     sei_cont->e = e;
 228
 229     QTAILQ_INSERT_TAIL(&s->pending_sei, sei_cont, link);
 230     css_generate_css_crws(0);
 231 }
 232
 233 static void s390_pci_generate_plug_event(uint16_t pec, uint32_t fh,
 234                                          uint32_t fid)
 235 {
 236     s390_pci_generate_event(2, pec, fh, fid, 0, 0);
 237 }
 238
 239 static void s390_pci_generate_error_event(uint16_t pec, uint32_t fh,
 240                                           uint32_t fid, uint64_t faddr,
 241                                           uint32_t e)
 242 {
 243     s390_pci_generate_event(1, pec, fh, fid, faddr, e);
 244 }
 245
 246 static void s390_pci_set_irq(void *opaque, int irq, int level)
 247 {
 248     /* nothing to do */
 249 }
 250
 251 static int s390_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 252 {
 253     /* nothing to do */
 254     return 0;
 255 }
 256
 257 static uint64_t s390_pci_get_table_origin(uint64_t iota)
 258 {
 259     return iota & ~ZPCI_IOTA_RTTO_FLAG;
 260 }
 261
 262 static unsigned int calc_rtx(dma_addr_t ptr)
 263 {
 264     return ((unsigned long) ptr >> ZPCI_RT_SHIFT) & ZPCI_INDEX_MASK;
 265 }
 266
 267 static unsigned int calc_sx(dma_addr_t ptr)
 268 {
 269     return ((unsigned long) ptr >> ZPCI_ST_SHIFT) & ZPCI_INDEX_MASK;
 270 }
 271
 272 static unsigned int calc_px(dma_addr_t ptr)
 273 {
 274     return ((unsigned long) ptr >> PAGE_SHIFT) & ZPCI_PT_MASK;
 275 }
 276
 277 static uint64_t get_rt_sto(uint64_t entry)
 278 {
 279     return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_RTX)
 280                 ? (entry & ZPCI_RTE_ADDR_MASK)
 281                 : 0;
 282 }
 283
 284 static uint64_t get_st_pto(uint64_t entry)
 285 {
 286     return ((entry & ZPCI_TABLE_TYPE_MASK) == ZPCI_TABLE_TYPE_SX)
 287             ? (entry & ZPCI_STE_ADDR_MASK)
 288             : 0;
 289 }
 290
 291 static uint64_t s390_guest_io_table_walk(uint64_t guest_iota,
 292                                   uint64_t guest_dma_address)
 293 {
 294     uint64_t sto_a, pto_a, px_a;
 295     uint64_t sto, pto, pte;
 296     uint32_t rtx, sx, px;
 297
 298     rtx = calc_rtx(guest_dma_address);
 299     sx = calc_sx(guest_dma_address);
 300     px = calc_px(guest_dma_address);
 301
 302     sto_a = guest_iota + rtx * sizeof(uint64_t);
 303     sto = address_space_ldq(&address_space_memory, sto_a,
 304                             MEMTXATTRS_UNSPECIFIED, NULL);
 305     sto = get_rt_sto(sto);
 306     if (!sto) {
 307         pte = 0;
 308         goto out;
 309     }
 310
 311     pto_a = sto + sx * sizeof(uint64_t);
 312     pto = address_space_ldq(&address_space_memory, pto_a,
 313                             MEMTXATTRS_UNSPECIFIED, NULL);
 314     pto = get_st_pto(pto);
 315     if (!pto) {
 316         pte = 0;
 317         goto out;
 318     }
 319
 320     px_a = pto + px * sizeof(uint64_t);
 321     pte = address_space_ldq(&address_space_memory, px_a,
 322                             MEMTXATTRS_UNSPECIFIED, NULL);
 323
 324 out:
 325     return pte;
 326 }
 327
 328 static IOMMUTLBEntry s390_translate_iommu(MemoryRegion *iommu, hwaddr addr,
 329                                           bool is_write)
 330 {
 331     uint64_t pte;
 332     uint32_t flags;
 333     S390PCIBusDevice *pbdev = container_of(iommu, S390PCIBusDevice, iommu_mr);
 334     S390pciState *s;
 335     IOMMUTLBEntry ret = {
 336         .target_as = &address_space_memory,
 337         .iova = 0,
 338         .translated_addr = 0,
 339         .addr_mask = ~(hwaddr)0,
 340         .perm = IOMMU_NONE,
 341     };
 342
 343     if (!pbdev->configured || !pbdev->pdev || !(pbdev->fh & FH_ENABLED)) {
 344         return ret;
 345     }
 346
 347     DPRINTF("iommu trans addr 0x%" PRIx64 "\n", addr);
 348
 349     s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pbdev->pdev)->qbus.parent);
 350     /* s390 does not have an APIC mapped to main storage so we use
 351      * a separate AddressSpace only for msix notifications
 352      */
 353     if (addr == ZPCI_MSI_ADDR) {
 354         ret.target_as = &s->msix_notify_as;
 355         ret.iova = addr;
 356         ret.translated_addr = addr;
 357         ret.addr_mask = 0xfff;
 358         ret.perm = IOMMU_RW;
 359         return ret;
 360     }
 361
 362     if (!pbdev->g_iota) {
 363         pbdev->error_state = true;
 364         pbdev->lgstg_blocked = true;
 365         s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid,
 366                                       addr, 0);
 367         return ret;
 368     }
 369
 370     if (addr < pbdev->pba || addr > pbdev->pal) {
 371         pbdev->error_state = true;
 372         pbdev->lgstg_blocked = true;
 373         s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid,
 374                                       addr, 0);
 375         return ret;
 376     }
 377
 378     pte = s390_guest_io_table_walk(s390_pci_get_table_origin(pbdev->g_iota),
 379                                    addr);
 380
 381     if (!pte) {
 382         pbdev->error_state = true;
 383         pbdev->lgstg_blocked = true;
 384         s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid,
 385                                       addr, ERR_EVENT_Q_BIT);
 386         return ret;
 387     }
 388
 389     flags = pte & ZPCI_PTE_FLAG_MASK;
 390     ret.iova = addr;
 391     ret.translated_addr = pte & ZPCI_PTE_ADDR_MASK;
 392     ret.addr_mask = 0xfff;
 393
 394     if (flags & ZPCI_PTE_INVALID) {
 395         ret.perm = IOMMU_NONE;
 396     } else {
 397         ret.perm = IOMMU_RW;
 398     }
 399
 400     return ret;
 401 }
 402
 403 static const MemoryRegionIOMMUOps s390_iommu_ops = {
 404     .translate = s390_translate_iommu,
 405 };
 406
 407 static AddressSpace *s390_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
 408 {
 409     S390pciState *s = opaque;
 410
 411     return &s->pbdev[PCI_SLOT(devfn)].as;
 412 }
 413
 414 static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set)
 415 {
 416     uint8_t ind_old, ind_new;
 417     hwaddr len = 1;
 418     uint8_t *ind_addr;
 419
 420     ind_addr = cpu_physical_memory_map(ind_loc, &len, 1);
 421     if (!ind_addr) {
 422         s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0);
 423         return -1;
 424     }
 425     do {
 426         ind_old = *ind_addr;
 427         ind_new = ind_old | to_be_set;
 428     } while (atomic_cmpxchg(ind_addr, ind_old, ind_new) != ind_old);
 429     cpu_physical_memory_unmap(ind_addr, len, 1, len);
 430
 431     return ind_old;
 432 }
 433
 434 static void s390_msi_ctrl_write(void *opaque, hwaddr addr, uint64_t data,
 435                                 unsigned int size)
 436 {
 437     S390PCIBusDevice *pbdev;
 438     uint32_t io_int_word;
 439     uint32_t fid = data >> ZPCI_MSI_VEC_BITS;
 440     uint32_t vec = data & ZPCI_MSI_VEC_MASK;
 441     uint64_t ind_bit;
 442     uint32_t sum_bit;
 443     uint32_t e = 0;
 444
 445     DPRINTF("write_msix data 0x%" PRIx64 " fid %d vec 0x%x\n", data, fid, vec);
 446
 447     pbdev = s390_pci_find_dev_by_fid(fid);
 448     if (!pbdev) {
 449         e |= (vec << ERR_EVENT_MVN_OFFSET);
 450         s390_pci_generate_error_event(ERR_EVENT_NOMSI, 0, fid, addr, e);
 451         return;
 452     }
 453
 454     if (!(pbdev->fh & FH_ENABLED)) {
 455         return;
 456     }
 457
 458     ind_bit = pbdev->routes.adapter.ind_offset;
 459     sum_bit = pbdev->routes.adapter.summary_offset;
 460
 461     set_ind_atomic(pbdev->routes.adapter.ind_addr + (ind_bit + vec) / 8,
 462                    0x80 >> ((ind_bit + vec) % 8));
 463     if (!set_ind_atomic(pbdev->routes.adapter.summary_addr + sum_bit / 8,
 464                                        0x80 >> (sum_bit % 8))) {
 465         io_int_word = (pbdev->isc << 27) | IO_INT_WORD_AI;
 466         s390_io_interrupt(0, 0, 0, io_int_word);
 467     }
 468 }
 469
 470 static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr addr, unsigned size)
 471 {
 472     return 0xffffffff;
 473 }
 474
 475 static const MemoryRegionOps s390_msi_ctrl_ops = {
 476     .write = s390_msi_ctrl_write,
 477     .read = s390_msi_ctrl_read,
 478     .endianness = DEVICE_LITTLE_ENDIAN,
 479 };
 480
 481 void s390_pcihost_iommu_configure(S390PCIBusDevice *pbdev, bool enable)
 482 {
 483     pbdev->configured = false;
 484
 485     if (enable) {
 486         uint64_t size = pbdev->pal - pbdev->pba + 1;
 487         memory_region_init_iommu(&pbdev->iommu_mr, OBJECT(&pbdev->mr),
 488                                  &s390_iommu_ops, "iommu-s390", size);
 489         memory_region_add_subregion(&pbdev->mr, pbdev->pba, &pbdev->iommu_mr);
 490     } else {
 491         memory_region_del_subregion(&pbdev->mr, &pbdev->iommu_mr);
 492     }
 493
 494     pbdev->configured = true;
 495 }
 496
 497 static void s390_pcihost_init_as(S390pciState *s)
 498 {
 499     int i;
 500     S390PCIBusDevice *pbdev;
 501
 502     for (i = 0; i < PCI_SLOT_MAX; i++) {
 503         pbdev = &s->pbdev[i];
 504         memory_region_init(&pbdev->mr, OBJECT(s),
 505                            "iommu-root-s390", UINT64_MAX);
 506         address_space_init(&pbdev->as, &pbdev->mr, "iommu-pci");
 507     }
 508
 509     memory_region_init_io(&s->msix_notify_mr, OBJECT(s),
 510                           &s390_msi_ctrl_ops, s, "msix-s390", UINT64_MAX);
 511     address_space_init(&s->msix_notify_as, &s->msix_notify_mr, "msix-pci");
 512 }
 513
 514 static int s390_pcihost_init(SysBusDevice *dev)
 515 {
 516     PCIBus *b;
 517     BusState *bus;
 518     PCIHostState *phb = PCI_HOST_BRIDGE(dev);
 519     S390pciState *s = S390_PCI_HOST_BRIDGE(dev);
 520
 521     DPRINTF("host_init\n");
 522
 523     b = pci_register_bus(DEVICE(dev), NULL,
 524                          s390_pci_set_irq, s390_pci_map_irq, NULL,
 525                          get_system_memory(), get_system_io(), 0, 64,
 526                          TYPE_PCI_BUS);
 527     s390_pcihost_init_as(s);
 528     pci_setup_iommu(b, s390_pci_dma_iommu, s);
 529
 530     bus = BUS(b);
 531     qbus_set_hotplug_handler(bus, DEVICE(dev), NULL);
 532     phb->bus = b;
 533     QTAILQ_INIT(&s->pending_sei);
 534     return 0;
 535 }
 536
 537 static int s390_pcihost_setup_msix(S390PCIBusDevice *pbdev)
 538 {
 539     uint8_t pos;
 540     uint16_t ctrl;
 541     uint32_t table, pba;
 542
 543     pos = pci_find_capability(pbdev->pdev, PCI_CAP_ID_MSIX);
 544     if (!pos) {
 545         pbdev->msix.available = false;
 546         return 0;
 547     }
 548
 549     ctrl = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_FLAGS,
 550              pci_config_size(pbdev->pdev), sizeof(ctrl));
 551     table = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_TABLE,
 552              pci_config_size(pbdev->pdev), sizeof(table));
 553     pba = pci_host_config_read_common(pbdev->pdev, pos + PCI_MSIX_PBA,
 554              pci_config_size(pbdev->pdev), sizeof(pba));
 555
 556     pbdev->msix.table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
 557     pbdev->msix.table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
 558     pbdev->msix.pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
 559     pbdev->msix.pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
 560     pbdev->msix.entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
 561     pbdev->msix.available = true;
 562     return 0;
 563 }
 564
 565 static void s390_pcihost_hot_plug(HotplugHandler *hotplug_dev,
 566                                   DeviceState *dev, Error **errp)
 567 {
 568     PCIDevice *pci_dev = PCI_DEVICE(dev);
 569     S390PCIBusDevice *pbdev;
 570     S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
 571                                            ->qbus.parent);
 572
 573     pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
 574
 575     pbdev->fid = s390_pci_get_pfid(pci_dev);
 576     pbdev->pdev = pci_dev;
 577     pbdev->configured = true;
 578     pbdev->fh = s390_pci_get_pfh(pci_dev);
 579
 580     s390_pcihost_setup_msix(pbdev);
 581
 582     if (dev->hotplugged) {
 583         s390_pci_generate_plug_event(HP_EVENT_RESERVED_TO_STANDBY,
 584                                      pbdev->fh, pbdev->fid);
 585         s390_pci_generate_plug_event(HP_EVENT_TO_CONFIGURED,
 586                                      pbdev->fh, pbdev->fid);
 587     }
 588 }
 589
 590 static void s390_pcihost_hot_unplug(HotplugHandler *hotplug_dev,
 591                                     DeviceState *dev, Error **errp)
 592 {
 593     PCIDevice *pci_dev = PCI_DEVICE(dev);
 594     S390pciState *s = S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev)
 595                                            ->qbus.parent);
 596     S390PCIBusDevice *pbdev = &s->pbdev[PCI_SLOT(pci_dev->devfn)];
 597
 598     if (pbdev->configured) {
 599         pbdev->configured = false;
 600         s390_pci_generate_plug_event(HP_EVENT_CONFIGURED_TO_STBRES,
 601                                      pbdev->fh, pbdev->fid);
 602     }
 603
 604     s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED,
 605                                  pbdev->fh, pbdev->fid);
 606     pbdev->fh = 0;
 607     pbdev->fid = 0;
 608     pbdev->pdev = NULL;
 609     object_unparent(OBJECT(pci_dev));
 610 }
 611
 612 static void s390_pcihost_class_init(ObjectClass *klass, void *data)
 613 {
 614     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 615     DeviceClass *dc = DEVICE_CLASS(klass);
 616     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 617
 618     dc->cannot_instantiate_with_device_add_yet = true;
 619     k->init = s390_pcihost_init;
 620     hc->plug = s390_pcihost_hot_plug;
 621     hc->unplug = s390_pcihost_hot_unplug;
 622     msi_nonbroken = true;
 623 }
 624
 625 static const TypeInfo s390_pcihost_info = {
 626     .name          = TYPE_S390_PCI_HOST_BRIDGE,
 627     .parent        = TYPE_PCI_HOST_BRIDGE,
 628     .instance_size = sizeof(S390pciState),
 629     .class_init    = s390_pcihost_class_init,
 630     .interfaces = (InterfaceInfo[]) {
 631         { TYPE_HOTPLUG_HANDLER },
 632         { }
 633     }
 634 };
 635
 636 static void s390_pci_register_types(void)
 637 {
 638     type_register_static(&s390_pcihost_info);
 639 }
 640
 641 type_init(s390_pci_register_types)