hw/s390x/s390-pci-bus.h

   1 /*
   2  * s390 PCI BUS definitions
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #ifndef HW_S390_PCI_BUS_H
  15 #define HW_S390_PCI_BUS_H
  16
  17 #include <hw/pci/pci.h>
  18 #include <hw/pci/pci_host.h>
  19 #include "hw/s390x/sclp.h"
  20 #include "hw/s390x/s390_flic.h"
  21 #include "hw/s390x/css.h"
  22
  23 #define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
  24 #define TYPE_S390_PCI_BUS "s390-pcibus"
  25 #define TYPE_S390_PCI_DEVICE "zpci"
  26 #define FH_MASK_ENABLE   0x80000000
  27 #define FH_MASK_INSTANCE 0x7f000000
  28 #define FH_MASK_SHM      0x00ff0000
  29 #define FH_MASK_INDEX    0x0000001f
  30 #define FH_SHM_VFIO      0x00010000
  31 #define FH_SHM_EMUL      0x00020000
  32 #define S390_PCIPT_ADAPTER 2
  33 #define ZPCI_MAX_FID 0xffffffff
  34 #define ZPCI_MAX_UID 0xffff
  35 #define UID_UNDEFINED 0
  36
  37 #define S390_PCI_HOST_BRIDGE(obj) \
  38     OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE)
  39 #define S390_PCI_BUS(obj) \
  40     OBJECT_CHECK(S390PCIBus, (obj), TYPE_S390_PCI_BUS)
  41 #define S390_PCI_DEVICE(obj) \
  42     OBJECT_CHECK(S390PCIBusDevice, (obj), TYPE_S390_PCI_DEVICE)
  43
  44 #define HP_EVENT_TO_CONFIGURED        0x0301
  45 #define HP_EVENT_RESERVED_TO_STANDBY  0x0302
  46 #define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
  47 #define HP_EVENT_STANDBY_TO_RESERVED  0x0308
  48
  49 #define ERR_EVENT_INVALAS 0x1
  50 #define ERR_EVENT_OORANGE 0x2
  51 #define ERR_EVENT_INVALTF 0x3
  52 #define ERR_EVENT_TPROTE  0x4
  53 #define ERR_EVENT_APROTE  0x5
  54 #define ERR_EVENT_KEYE    0x6
  55 #define ERR_EVENT_INVALTE 0x7
  56 #define ERR_EVENT_INVALTL 0x8
  57 #define ERR_EVENT_TT      0x9
  58 #define ERR_EVENT_INVALMS 0xa
  59 #define ERR_EVENT_SERR    0xb
  60 #define ERR_EVENT_NOMSI   0x10
  61 #define ERR_EVENT_INVALBV 0x11
  62 #define ERR_EVENT_AIBV    0x12
  63 #define ERR_EVENT_AIRERR  0x13
  64 #define ERR_EVENT_FMBA    0x2a
  65 #define ERR_EVENT_FMBUP   0x2b
  66 #define ERR_EVENT_FMBPRO  0x2c
  67 #define ERR_EVENT_CCONF   0x30
  68 #define ERR_EVENT_SERVAC  0x3a
  69 #define ERR_EVENT_PERMERR 0x3b
  70
  71 #define ERR_EVENT_Q_BIT 0x2
  72 #define ERR_EVENT_MVN_OFFSET 16
  73
  74 #define ZPCI_MSI_VEC_BITS 11
  75 #define ZPCI_MSI_VEC_MASK 0x7ff
  76
  77 #define ZPCI_MSI_ADDR  0xfe00000000000000ULL
  78 #define ZPCI_SDMA_ADDR 0x100000000ULL
  79 #define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
  80
  81 #define PAGE_SHIFT      12
  82 #define PAGE_MASK       (~(PAGE_SIZE-1))
  83 #define PAGE_DEFAULT_ACC        0
  84 #define PAGE_DEFAULT_KEY        (PAGE_DEFAULT_ACC << 4)
  85
  86 /* I/O Translation Anchor (IOTA) */
  87 enum ZpciIoatDtype {
  88     ZPCI_IOTA_STO = 0,
  89     ZPCI_IOTA_RTTO = 1,
  90     ZPCI_IOTA_RSTO = 2,
  91     ZPCI_IOTA_RFTO = 3,
  92     ZPCI_IOTA_PFAA = 4,
  93     ZPCI_IOTA_IOPFAA = 5,
  94     ZPCI_IOTA_IOPTO = 7
  95 };
  96
  97 #define ZPCI_IOTA_IOT_ENABLED           0x800ULL
  98 #define ZPCI_IOTA_DT_ST                 (ZPCI_IOTA_STO  << 2)
  99 #define ZPCI_IOTA_DT_RT                 (ZPCI_IOTA_RTTO << 2)
 100 #define ZPCI_IOTA_DT_RS                 (ZPCI_IOTA_RSTO << 2)
 101 #define ZPCI_IOTA_DT_RF                 (ZPCI_IOTA_RFTO << 2)
 102 #define ZPCI_IOTA_DT_PF                 (ZPCI_IOTA_PFAA << 2)
 103 #define ZPCI_IOTA_FS_4K                 0
 104 #define ZPCI_IOTA_FS_1M                 1
 105 #define ZPCI_IOTA_FS_2G                 2
 106 #define ZPCI_KEY                        (PAGE_DEFAULT_KEY << 5)
 107
 108 #define ZPCI_IOTA_STO_FLAG  (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
 109 #define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
 110 #define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
 111 #define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
 112 #define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
 113                              ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
 114
 115 /* I/O Region and segment tables */
 116 #define ZPCI_INDEX_MASK         0x7ffULL
 117
 118 #define ZPCI_TABLE_TYPE_MASK    0xc
 119 #define ZPCI_TABLE_TYPE_RFX     0xc
 120 #define ZPCI_TABLE_TYPE_RSX     0x8
 121 #define ZPCI_TABLE_TYPE_RTX     0x4
 122 #define ZPCI_TABLE_TYPE_SX      0x0
 123
 124 #define ZPCI_TABLE_LEN_RFX      0x3
 125 #define ZPCI_TABLE_LEN_RSX      0x3
 126 #define ZPCI_TABLE_LEN_RTX      0x3
 127
 128 #define ZPCI_TABLE_OFFSET_MASK  0xc0
 129 #define ZPCI_TABLE_SIZE         0x4000
 130 #define ZPCI_TABLE_ALIGN        ZPCI_TABLE_SIZE
 131 #define ZPCI_TABLE_ENTRY_SIZE   (sizeof(unsigned long))
 132 #define ZPCI_TABLE_ENTRIES      (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
 133
 134 #define ZPCI_TABLE_BITS         11
 135 #define ZPCI_PT_BITS            8
 136 #define ZPCI_ST_SHIFT           (ZPCI_PT_BITS + PAGE_SHIFT)
 137 #define ZPCI_RT_SHIFT           (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
 138
 139 #define ZPCI_RTE_FLAG_MASK      0x3fffULL
 140 #define ZPCI_RTE_ADDR_MASK      (~ZPCI_RTE_FLAG_MASK)
 141 #define ZPCI_STE_FLAG_MASK      0x7ffULL
 142 #define ZPCI_STE_ADDR_MASK      (~ZPCI_STE_FLAG_MASK)
 143
 144 /* I/O Page tables */
 145 #define ZPCI_PTE_VALID_MASK             0x400
 146 #define ZPCI_PTE_INVALID                0x400
 147 #define ZPCI_PTE_VALID                  0x000
 148 #define ZPCI_PT_SIZE                    0x800
 149 #define ZPCI_PT_ALIGN                   ZPCI_PT_SIZE
 150 #define ZPCI_PT_ENTRIES                 (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
 151 #define ZPCI_PT_MASK                    (ZPCI_PT_ENTRIES - 1)
 152
 153 #define ZPCI_PTE_FLAG_MASK              0xfffULL
 154 #define ZPCI_PTE_ADDR_MASK              (~ZPCI_PTE_FLAG_MASK)
 155
 156 /* Shared bits */
 157 #define ZPCI_TABLE_VALID                0x00
 158 #define ZPCI_TABLE_INVALID              0x20
 159 #define ZPCI_TABLE_PROTECTED            0x200
 160 #define ZPCI_TABLE_UNPROTECTED          0x000
 161
 162 #define ZPCI_TABLE_VALID_MASK           0x20
 163 #define ZPCI_TABLE_PROT_MASK            0x200
 164
 165 /* PCI Function States
 166  *
 167  * reserved: default; device has just been plugged or is in progress of being
 168  *           unplugged
 169  * standby: device is present but not configured; transition from any
 170  *          configured state/to this state via sclp configure/deconfigure
 171  *
 172  * The following states make up the "configured" meta-state:
 173  * disabled: device is configured but not enabled; transition between this
 174  *           state and enabled via clp enable/disable
 175  * enbaled: device is ready for use; transition to disabled via clp disable;
 176  *          may enter an error state
 177  * blocked: ignore all DMA and interrupts; transition back to enabled or from
 178  *          error state via mpcifc
 179  * error: an error occured; transition back to enabled via mpcifc
 180  * permanent error: an unrecoverable error occured; transition to standby via
 181  *                  sclp deconfigure
 182  */
 183 typedef enum {
 184     ZPCI_FS_RESERVED,
 185     ZPCI_FS_STANDBY,
 186     ZPCI_FS_DISABLED,
 187     ZPCI_FS_ENABLED,
 188     ZPCI_FS_BLOCKED,
 189     ZPCI_FS_ERROR,
 190     ZPCI_FS_PERMANENT_ERROR,
 191 } ZpciState;
 192
 193 typedef struct SeiContainer {
 194     QTAILQ_ENTRY(SeiContainer) link;
 195     uint32_t fid;
 196     uint32_t fh;
 197     uint8_t cc;
 198     uint16_t pec;
 199     uint64_t faddr;
 200     uint32_t e;
 201 } SeiContainer;
 202
 203 typedef struct PciCcdfErr {
 204     uint32_t reserved1;
 205     uint32_t fh;
 206     uint32_t fid;
 207     uint32_t e;
 208     uint64_t faddr;
 209     uint32_t reserved3;
 210     uint16_t reserved4;
 211     uint16_t pec;
 212 } QEMU_PACKED PciCcdfErr;
 213
 214 typedef struct PciCcdfAvail {
 215     uint32_t reserved1;
 216     uint32_t fh;
 217     uint32_t fid;
 218     uint32_t reserved2;
 219     uint32_t reserved3;
 220     uint32_t reserved4;
 221     uint32_t reserved5;
 222     uint16_t reserved6;
 223     uint16_t pec;
 224 } QEMU_PACKED PciCcdfAvail;
 225
 226 typedef struct ChscSeiNt2Res {
 227     uint16_t length;
 228     uint16_t code;
 229     uint16_t reserved1;
 230     uint8_t reserved2;
 231     uint8_t nt;
 232     uint8_t flags;
 233     uint8_t reserved3;
 234     uint8_t reserved4;
 235     uint8_t cc;
 236     uint32_t reserved5[13];
 237     uint8_t ccdf[4016];
 238 } QEMU_PACKED ChscSeiNt2Res;
 239
 240 typedef struct PciCfgSccb {
 241     SCCBHeader header;
 242     uint8_t atype;
 243     uint8_t reserved1;
 244     uint16_t reserved2;
 245     uint32_t aid;
 246 } QEMU_PACKED PciCfgSccb;
 247
 248 typedef struct S390MsixInfo {
 249     bool available;
 250     uint8_t table_bar;
 251     uint8_t pba_bar;
 252     uint16_t entries;
 253     uint32_t table_offset;
 254     uint32_t pba_offset;
 255 } S390MsixInfo;
 256
 257 typedef struct S390PCIIOMMU {
 258     AddressSpace as;
 259     MemoryRegion mr;
 260 } S390PCIIOMMU;
 261
 262 typedef struct S390PCIBusDevice {
 263     DeviceState qdev;
 264     PCIDevice *pdev;
 265     ZpciState state;
 266     bool iommu_enabled;
 267     char *target;
 268     uint16_t uid;
 269     uint32_t fh;
 270     uint32_t fid;
 271     bool fid_defined;
 272     uint64_t g_iota;
 273     uint64_t pba;
 274     uint64_t pal;
 275     uint64_t fmb_addr;
 276     uint8_t isc;
 277     uint16_t noi;
 278     uint8_t sum;
 279     S390MsixInfo msix;
 280     AdapterRoutes routes;
 281     S390PCIIOMMU *iommu;
 282     MemoryRegion iommu_mr;
 283     IndAddr *summary_ind;
 284     IndAddr *indicator;
 285 } S390PCIBusDevice;
 286
 287 typedef struct S390PCIBus {
 288     BusState qbus;
 289 } S390PCIBus;
 290
 291 typedef struct S390pciState {
 292     PCIHostState parent_obj;
 293     S390PCIBus *bus;
 294     S390PCIBusDevice *pbdev[PCI_SLOT_MAX];
 295     S390PCIIOMMU *iommu[PCI_SLOT_MAX];
 296     AddressSpace msix_notify_as;
 297     MemoryRegion msix_notify_mr;
 298     QTAILQ_HEAD(, SeiContainer) pending_sei;
 299 } S390pciState;
 300
 301 int chsc_sei_nt2_get_event(void *res);
 302 int chsc_sei_nt2_have_event(void);
 303 void s390_pci_sclp_configure(SCCB *sccb);
 304 void s390_pci_sclp_deconfigure(SCCB *sccb);
 305 void s390_pci_iommu_enable(S390PCIBusDevice *pbdev);
 306 void s390_pci_iommu_disable(S390PCIBusDevice *pbdev);
 307 void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
 308                                    uint64_t faddr, uint32_t e);
 309 S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx);
 310 S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh);
 311 S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid);
 312
 313 #endif