hw/s390x/s390-pci-inst.c

   1 /*
   2  * s390 PCI instructions
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu-common.h"
  16 #include "cpu.h"
  17 #include "s390-pci-inst.h"
  18 #include "s390-pci-bus.h"
  19 #include "exec/memory-internal.h"
  20 #include "qemu/error-report.h"
  21 #include "sysemu/hw_accel.h"
  22
  23 #ifndef DEBUG_S390PCI_INST
  24 #define DEBUG_S390PCI_INST  0
  25 #endif
  26
  27 #define DPRINTF(fmt, ...)                                          \
  28     do {                                                           \
  29         if (DEBUG_S390PCI_INST) {                                  \
  30             fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \
  31         }                                                          \
  32     } while (0)
  33
  34 static void s390_set_status_code(CPUS390XState *env,
  35                                  uint8_t r, uint64_t status_code)
  36 {
  37     env->regs[r] &= ~0xff000000ULL;
  38     env->regs[r] |= (status_code & 0xff) << 24;
  39 }
  40
  41 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)
  42 {
  43     S390PCIBusDevice *pbdev = NULL;
  44     S390pciState *s = s390_get_phb();
  45     uint32_t res_code, initial_l2, g_l2;
  46     int rc, i;
  47     uint64_t resume_token;
  48
  49     rc = 0;
  50     if (lduw_p(&rrb->request.hdr.len) != 32) {
  51         res_code = CLP_RC_LEN;
  52         rc = -EINVAL;
  53         goto out;
  54     }
  55
  56     if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) {
  57         res_code = CLP_RC_FMT;
  58         rc = -EINVAL;
  59         goto out;
  60     }
  61
  62     if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 ||
  63         ldq_p(&rrb->request.reserved1) != 0) {
  64         res_code = CLP_RC_RESNOT0;
  65         rc = -EINVAL;
  66         goto out;
  67     }
  68
  69     resume_token = ldq_p(&rrb->request.resume_token);
  70
  71     if (resume_token) {
  72         pbdev = s390_pci_find_dev_by_idx(s, resume_token);
  73         if (!pbdev) {
  74             res_code = CLP_RC_LISTPCI_BADRT;
  75             rc = -EINVAL;
  76             goto out;
  77         }
  78     } else {
  79         pbdev = s390_pci_find_next_avail_dev(s, NULL);
  80     }
  81
  82     if (lduw_p(&rrb->response.hdr.len) < 48) {
  83         res_code = CLP_RC_8K;
  84         rc = -EINVAL;
  85         goto out;
  86     }
  87
  88     initial_l2 = lduw_p(&rrb->response.hdr.len);
  89     if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry)
  90         != 0) {
  91         res_code = CLP_RC_LEN;
  92         rc = -EINVAL;
  93         *cc = 3;
  94         goto out;
  95     }
  96
  97     stl_p(&rrb->response.fmt, 0);
  98     stq_p(&rrb->response.reserved1, 0);
  99     stl_p(&rrb->response.mdd, FH_MASK_SHM);
 100     stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS);
 101     rrb->response.flags = UID_CHECKING_ENABLED;
 102     rrb->response.entry_size = sizeof(ClpFhListEntry);
 103
 104     i = 0;
 105     g_l2 = LIST_PCI_HDR_LEN;
 106     while (g_l2 < initial_l2 && pbdev) {
 107         stw_p(&rrb->response.fh_list[i].device_id,
 108             pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID));
 109         stw_p(&rrb->response.fh_list[i].vendor_id,
 110             pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID));
 111         /* Ignore RESERVED devices. */
 112         stl_p(&rrb->response.fh_list[i].config,
 113             pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31);
 114         stl_p(&rrb->response.fh_list[i].fid, pbdev->fid);
 115         stl_p(&rrb->response.fh_list[i].fh, pbdev->fh);
 116
 117         g_l2 += sizeof(ClpFhListEntry);
 118         /* Add endian check for DPRINTF? */
 119         DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
 120                 g_l2,
 121                 lduw_p(&rrb->response.fh_list[i].vendor_id),
 122                 lduw_p(&rrb->response.fh_list[i].device_id),
 123                 ldl_p(&rrb->response.fh_list[i].fid),
 124                 ldl_p(&rrb->response.fh_list[i].fh));
 125         pbdev = s390_pci_find_next_avail_dev(s, pbdev);
 126         i++;
 127     }
 128
 129     if (!pbdev) {
 130         resume_token = 0;
 131     } else {
 132         resume_token = pbdev->fh & FH_MASK_INDEX;
 133     }
 134     stq_p(&rrb->response.resume_token, resume_token);
 135     stw_p(&rrb->response.hdr.len, g_l2);
 136     stw_p(&rrb->response.hdr.rsp, CLP_RC_OK);
 137 out:
 138     if (rc) {
 139         DPRINTF("list pci failed rc 0x%x\n", rc);
 140         stw_p(&rrb->response.hdr.rsp, res_code);
 141     }
 142     return rc;
 143 }
 144
 145 int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)
 146 {
 147     ClpReqHdr *reqh;
 148     ClpRspHdr *resh;
 149     S390PCIBusDevice *pbdev;
 150     uint32_t req_len;
 151     uint32_t res_len;
 152     uint8_t buffer[4096 * 2];
 153     uint8_t cc = 0;
 154     CPUS390XState *env = &cpu->env;
 155     S390pciState *s = s390_get_phb();
 156     int i;
 157
 158     if (env->psw.mask & PSW_MASK_PSTATE) {
 159         s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
 160         return 0;
 161     }
 162
 163     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) {
 164         s390_cpu_virt_mem_handle_exc(cpu, ra);
 165         return 0;
 166     }
 167     reqh = (ClpReqHdr *)buffer;
 168     req_len = lduw_p(&reqh->len);
 169     if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) {
 170         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 171         return 0;
 172     }
 173
 174     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
 175                                req_len + sizeof(*resh))) {
 176         s390_cpu_virt_mem_handle_exc(cpu, ra);
 177         return 0;
 178     }
 179     resh = (ClpRspHdr *)(buffer + req_len);
 180     res_len = lduw_p(&resh->len);
 181     if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) {
 182         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 183         return 0;
 184     }
 185     if ((req_len + res_len) > 8192) {
 186         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 187         return 0;
 188     }
 189
 190     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
 191                                req_len + res_len)) {
 192         s390_cpu_virt_mem_handle_exc(cpu, ra);
 193         return 0;
 194     }
 195
 196     if (req_len != 32) {
 197         stw_p(&resh->rsp, CLP_RC_LEN);
 198         goto out;
 199     }
 200
 201     switch (lduw_p(&reqh->cmd)) {
 202     case CLP_LIST_PCI: {
 203         ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer;
 204         list_pci(rrb, &cc);
 205         break;
 206     }
 207     case CLP_SET_PCI_FN: {
 208         ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh;
 209         ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh;
 210
 211         pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh));
 212         if (!pbdev) {
 213                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);
 214                 goto out;
 215         }
 216
 217         switch (reqsetpci->oc) {
 218         case CLP_SET_ENABLE_PCI_FN:
 219             switch (reqsetpci->ndas) {
 220             case 0:
 221                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS);
 222                 goto out;
 223             case 1:
 224                 break;
 225             default:
 226                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES);
 227                 goto out;
 228             }
 229
 230             if (pbdev->fh & FH_MASK_ENABLE) {
 231                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
 232                 goto out;
 233             }
 234
 235             pbdev->fh |= FH_MASK_ENABLE;
 236             pbdev->state = ZPCI_FS_ENABLED;
 237             stl_p(&ressetpci->fh, pbdev->fh);
 238             stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
 239             break;
 240         case CLP_SET_DISABLE_PCI_FN:
 241             if (!(pbdev->fh & FH_MASK_ENABLE)) {
 242                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
 243                 goto out;
 244             }
 245             device_reset(DEVICE(pbdev));
 246             pbdev->fh &= ~FH_MASK_ENABLE;
 247             pbdev->state = ZPCI_FS_DISABLED;
 248             stl_p(&ressetpci->fh, pbdev->fh);
 249             stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
 250             break;
 251         default:
 252             DPRINTF("unknown set pci command\n");
 253             stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
 254             break;
 255         }
 256         break;
 257     }
 258     case CLP_QUERY_PCI_FN: {
 259         ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh;
 260         ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh;
 261
 262         pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh));
 263         if (!pbdev) {
 264             DPRINTF("query pci no pci dev\n");
 265             stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH);
 266             goto out;
 267         }
 268
 269         for (i = 0; i < PCI_BAR_COUNT; i++) {
 270             uint32_t data = pci_get_long(pbdev->pdev->config +
 271                 PCI_BASE_ADDRESS_0 + (i * 4));
 272
 273             stl_p(&resquery->bar[i], data);
 274             resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ?
 275                                     ctz64(pbdev->pdev->io_regions[i].size) : 0;
 276             DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i,
 277                     ldl_p(&resquery->bar[i]),
 278                     pbdev->pdev->io_regions[i].size,
 279                     resquery->bar_size[i]);
 280         }
 281
 282         stq_p(&resquery->sdma, ZPCI_SDMA_ADDR);
 283         stq_p(&resquery->edma, ZPCI_EDMA_ADDR);
 284         stl_p(&resquery->fid, pbdev->fid);
 285         stw_p(&resquery->pchid, 0);
 286         stw_p(&resquery->ug, 1);
 287         stl_p(&resquery->uid, pbdev->uid);
 288         stw_p(&resquery->hdr.rsp, CLP_RC_OK);
 289         break;
 290     }
 291     case CLP_QUERY_PCI_FNGRP: {
 292         ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh;
 293         resgrp->fr = 1;
 294         stq_p(&resgrp->dasm, 0);
 295         stq_p(&resgrp->msia, ZPCI_MSI_ADDR);
 296         stw_p(&resgrp->mui, 0);
 297         stw_p(&resgrp->i, 128);
 298         stw_p(&resgrp->maxstbl, 128);
 299         resgrp->version = 0;
 300
 301         stw_p(&resgrp->hdr.rsp, CLP_RC_OK);
 302         break;
 303     }
 304     default:
 305         DPRINTF("unknown clp command\n");
 306         stw_p(&resh->rsp, CLP_RC_CMD);
 307         break;
 308     }
 309
 310 out:
 311     if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer,
 312                                 req_len + res_len)) {
 313         s390_cpu_virt_mem_handle_exc(cpu, ra);
 314         return 0;
 315     }
 316     setcc(cpu, cc);
 317     return 0;
 318 }
 319
 320 /**
 321  * Swap data contained in s390x big endian registers to little endian
 322  * PCI bars.
 323  *
 324  * @ptr: a pointer to a uint64_t data field
 325  * @len: the length of the valid data, must be 1,2,4 or 8
 326  */
 327 static int zpci_endian_swap(uint64_t *ptr, uint8_t len)
 328 {
 329     uint64_t data = *ptr;
 330
 331     switch (len) {
 332     case 1:
 333         break;
 334     case 2:
 335         data = bswap16(data);
 336         break;
 337     case 4:
 338         data = bswap32(data);
 339         break;
 340     case 8:
 341         data = bswap64(data);
 342         break;
 343     default:
 344         return -EINVAL;
 345     }
 346     *ptr = data;
 347     return 0;
 348 }
 349
 350 static MemoryRegion *s390_get_subregion(MemoryRegion *mr, uint64_t offset,
 351                                         uint8_t len)
 352 {
 353     MemoryRegion *subregion;
 354     uint64_t subregion_size;
 355
 356     QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
 357         subregion_size = int128_get64(subregion->size);
 358         if ((offset >= subregion->addr) &&
 359             (offset + len) <= (subregion->addr + subregion_size)) {
 360             mr = subregion;
 361             break;
 362         }
 363     }
 364     return mr;
 365 }
 366
 367 static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
 368                                  uint64_t offset, uint64_t *data, uint8_t len)
 369 {
 370     MemoryRegion *mr;
 371
 372     mr = pbdev->pdev->io_regions[pcias].memory;
 373     mr = s390_get_subregion(mr, offset, len);
 374     offset -= mr->addr;
 375     return memory_region_dispatch_read(mr, offset, data, len,
 376                                        MEMTXATTRS_UNSPECIFIED);
 377 }
 378
 379 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
 380 {
 381     CPUS390XState *env = &cpu->env;
 382     S390PCIBusDevice *pbdev;
 383     uint64_t offset;
 384     uint64_t data;
 385     MemTxResult result;
 386     uint8_t len;
 387     uint32_t fh;
 388     uint8_t pcias;
 389
 390     if (env->psw.mask & PSW_MASK_PSTATE) {
 391         s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
 392         return 0;
 393     }
 394
 395     if (r2 & 0x1) {
 396         s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
 397         return 0;
 398     }
 399
 400     fh = env->regs[r2] >> 32;
 401     pcias = (env->regs[r2] >> 16) & 0xf;
 402     len = env->regs[r2] & 0xf;
 403     offset = env->regs[r2 + 1];
 404
 405     if (!(fh & FH_MASK_ENABLE)) {
 406         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 407         return 0;
 408     }
 409
 410     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 411     if (!pbdev) {
 412         DPRINTF("pcilg no pci dev\n");
 413         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 414         return 0;
 415     }
 416
 417     switch (pbdev->state) {
 418     case ZPCI_FS_PERMANENT_ERROR:
 419     case ZPCI_FS_ERROR:
 420         setcc(cpu, ZPCI_PCI_LS_ERR);
 421         s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
 422         return 0;
 423     default:
 424         break;
 425     }
 426
 427     switch (pcias) {
 428     case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX:
 429         if (!len || (len > (8 - (offset & 0x7)))) {
 430             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 431             return 0;
 432         }
 433         result = zpci_read_bar(pbdev, pcias, offset, &data, len);
 434         if (result != MEMTX_OK) {
 435             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 436             return 0;
 437         }
 438         break;
 439     case ZPCI_CONFIG_BAR:
 440         if (!len || (len > (4 - (offset & 0x3))) || len == 3) {
 441             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 442             return 0;
 443         }
 444         data =  pci_host_config_read_common(
 445                    pbdev->pdev, offset, pci_config_size(pbdev->pdev), len);
 446
 447         if (zpci_endian_swap(&data, len)) {
 448             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 449             return 0;
 450         }
 451         break;
 452     default:
 453         DPRINTF("pcilg invalid space\n");
 454         setcc(cpu, ZPCI_PCI_LS_ERR);
 455         s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
 456         return 0;
 457     }
 458
 459     env->regs[r1] = data;
 460     setcc(cpu, ZPCI_PCI_LS_OK);
 461     return 0;
 462 }
 463
 464 static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
 465                                   uint64_t offset, uint64_t data, uint8_t len)
 466 {
 467     MemoryRegion *mr;
 468
 469     mr = pbdev->pdev->io_regions[pcias].memory;
 470     mr = s390_get_subregion(mr, offset, len);
 471     offset -= mr->addr;
 472     return memory_region_dispatch_write(mr, offset, data, len,
 473                                         MEMTXATTRS_UNSPECIFIED);
 474 }
 475
 476 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
 477 {
 478     CPUS390XState *env = &cpu->env;
 479     uint64_t offset, data;
 480     S390PCIBusDevice *pbdev;
 481     MemTxResult result;
 482     uint8_t len;
 483     uint32_t fh;
 484     uint8_t pcias;
 485
 486     if (env->psw.mask & PSW_MASK_PSTATE) {
 487         s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
 488         return 0;
 489     }
 490
 491     if (r2 & 0x1) {
 492         s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
 493         return 0;
 494     }
 495
 496     fh = env->regs[r2] >> 32;
 497     pcias = (env->regs[r2] >> 16) & 0xf;
 498     len = env->regs[r2] & 0xf;
 499     offset = env->regs[r2 + 1];
 500     data = env->regs[r1];
 501
 502     if (!(fh & FH_MASK_ENABLE)) {
 503         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 504         return 0;
 505     }
 506
 507     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 508     if (!pbdev) {
 509         DPRINTF("pcistg no pci dev\n");
 510         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 511         return 0;
 512     }
 513
 514     switch (pbdev->state) {
 515     /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED
 516      * are already covered by the FH_MASK_ENABLE check above
 517      */
 518     case ZPCI_FS_PERMANENT_ERROR:
 519     case ZPCI_FS_ERROR:
 520         setcc(cpu, ZPCI_PCI_LS_ERR);
 521         s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
 522         return 0;
 523     default:
 524         break;
 525     }
 526
 527     switch (pcias) {
 528         /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */
 529     case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX:
 530         /* Check length:
 531          * A length of 0 is invalid and length should not cross a double word
 532          */
 533         if (!len || (len > (8 - (offset & 0x7)))) {
 534             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 535             return 0;
 536         }
 537
 538         result = zpci_write_bar(pbdev, pcias, offset, data, len);
 539         if (result != MEMTX_OK) {
 540             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 541             return 0;
 542         }
 543         break;
 544     case ZPCI_CONFIG_BAR:
 545         /* ZPCI uses the pseudo BAR number 15 as configuration space */
 546         /* possible access lengths are 1,2,4 and must not cross a word */
 547         if (!len || (len > (4 - (offset & 0x3))) || len == 3) {
 548             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 549             return 0;
 550         }
 551         /* len = 1,2,4 so we do not need to test */
 552         zpci_endian_swap(&data, len);
 553         pci_host_config_write_common(pbdev->pdev, offset,
 554                                      pci_config_size(pbdev->pdev),
 555                                      data, len);
 556         break;
 557     default:
 558         DPRINTF("pcistg invalid space\n");
 559         setcc(cpu, ZPCI_PCI_LS_ERR);
 560         s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
 561         return 0;
 562     }
 563
 564     setcc(cpu, ZPCI_PCI_LS_OK);
 565     return 0;
 566 }
 567
 568 static void s390_pci_update_iotlb(S390PCIIOMMU *iommu, S390IOTLBEntry *entry)
 569 {
 570     S390IOTLBEntry *cache = g_hash_table_lookup(iommu->iotlb, &entry->iova);
 571     IOMMUTLBEntry notify = {
 572         .target_as = &address_space_memory,
 573         .iova = entry->iova,
 574         .translated_addr = entry->translated_addr,
 575         .perm = entry->perm,
 576         .addr_mask = ~PAGE_MASK,
 577     };
 578
 579     if (entry->perm == IOMMU_NONE) {
 580         if (!cache) {
 581             return;
 582         }
 583         g_hash_table_remove(iommu->iotlb, &entry->iova);
 584     } else {
 585         if (cache) {
 586             if (cache->perm == entry->perm &&
 587                 cache->translated_addr == entry->translated_addr) {
 588                 return;
 589             }
 590
 591             notify.perm = IOMMU_NONE;
 592             memory_region_notify_iommu(&iommu->iommu_mr, 0, notify);
 593             notify.perm = entry->perm;
 594         }
 595
 596         cache = g_new(S390IOTLBEntry, 1);
 597         cache->iova = entry->iova;
 598         cache->translated_addr = entry->translated_addr;
 599         cache->len = PAGE_SIZE;
 600         cache->perm = entry->perm;
 601         g_hash_table_replace(iommu->iotlb, &cache->iova, cache);
 602     }
 603
 604     memory_region_notify_iommu(&iommu->iommu_mr, 0, notify);
 605 }
 606
 607 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
 608 {
 609     CPUS390XState *env = &cpu->env;
 610     uint32_t fh;
 611     uint16_t error = 0;
 612     S390PCIBusDevice *pbdev;
 613     S390PCIIOMMU *iommu;
 614     S390IOTLBEntry entry;
 615     hwaddr start, end;
 616
 617     if (env->psw.mask & PSW_MASK_PSTATE) {
 618         s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
 619         return 0;
 620     }
 621
 622     if (r2 & 0x1) {
 623         s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
 624         return 0;
 625     }
 626
 627     fh = env->regs[r1] >> 32;
 628     start = env->regs[r2];
 629     end = start + env->regs[r2 + 1];
 630
 631     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 632     if (!pbdev) {
 633         DPRINTF("rpcit no pci dev\n");
 634         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 635         return 0;
 636     }
 637
 638     switch (pbdev->state) {
 639     case ZPCI_FS_RESERVED:
 640     case ZPCI_FS_STANDBY:
 641     case ZPCI_FS_DISABLED:
 642     case ZPCI_FS_PERMANENT_ERROR:
 643         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 644         return 0;
 645     case ZPCI_FS_ERROR:
 646         setcc(cpu, ZPCI_PCI_LS_ERR);
 647         s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER);
 648         return 0;
 649     default:
 650         break;
 651     }
 652
 653     iommu = pbdev->iommu;
 654     if (!iommu->g_iota) {
 655         error = ERR_EVENT_INVALAS;
 656         goto err;
 657     }
 658
 659     if (end < iommu->pba || start > iommu->pal) {
 660         error = ERR_EVENT_OORANGE;
 661         goto err;
 662     }
 663
 664     while (start < end) {
 665         error = s390_guest_io_table_walk(iommu->g_iota, start, &entry);
 666         if (error) {
 667             break;
 668         }
 669
 670         start += entry.len;
 671         while (entry.iova < start && entry.iova < end) {
 672             s390_pci_update_iotlb(iommu, &entry);
 673             entry.iova += PAGE_SIZE;
 674             entry.translated_addr += PAGE_SIZE;
 675         }
 676     }
 677 err:
 678     if (error) {
 679         pbdev->state = ZPCI_FS_ERROR;
 680         setcc(cpu, ZPCI_PCI_LS_ERR);
 681         s390_set_status_code(env, r1, ZPCI_PCI_ST_FUNC_IN_ERR);
 682         s390_pci_generate_error_event(error, pbdev->fh, pbdev->fid, start, 0);
 683     } else {
 684         setcc(cpu, ZPCI_PCI_LS_OK);
 685     }
 686     return 0;
 687 }
 688
 689 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
 690                         uint8_t ar, uintptr_t ra)
 691 {
 692     CPUS390XState *env = &cpu->env;
 693     S390PCIBusDevice *pbdev;
 694     MemoryRegion *mr;
 695     MemTxResult result;
 696     uint64_t offset;
 697     int i;
 698     uint32_t fh;
 699     uint8_t pcias;
 700     uint8_t len;
 701     uint8_t buffer[128];
 702
 703     if (env->psw.mask & PSW_MASK_PSTATE) {
 704         s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra);
 705         return 0;
 706     }
 707
 708     fh = env->regs[r1] >> 32;
 709     pcias = (env->regs[r1] >> 16) & 0xf;
 710     len = env->regs[r1] & 0xff;
 711     offset = env->regs[r3];
 712
 713     if (!(fh & FH_MASK_ENABLE)) {
 714         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 715         return 0;
 716     }
 717
 718     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 719     if (!pbdev) {
 720         DPRINTF("pcistb no pci dev fh 0x%x\n", fh);
 721         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 722         return 0;
 723     }
 724
 725     switch (pbdev->state) {
 726     case ZPCI_FS_PERMANENT_ERROR:
 727     case ZPCI_FS_ERROR:
 728         setcc(cpu, ZPCI_PCI_LS_ERR);
 729         s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED);
 730         return 0;
 731     default:
 732         break;
 733     }
 734
 735     if (pcias > ZPCI_IO_BAR_MAX) {
 736         DPRINTF("pcistb invalid space\n");
 737         setcc(cpu, ZPCI_PCI_LS_ERR);
 738         s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS);
 739         return 0;
 740     }
 741
 742     /* Verify the address, offset and length */
 743     /* offset must be a multiple of 8 */
 744     if (offset % 8) {
 745         goto specification_error;
 746     }
 747     /* Length must be greater than 8, a multiple of 8 */
 748     /* and not greater than maxstbl */
 749     if ((len <= 8) || (len % 8) || (len > pbdev->maxstbl)) {
 750         goto specification_error;
 751     }
 752     /* Do not cross a 4K-byte boundary */
 753     if (((offset & 0xfff) + len) > 0x1000) {
 754         goto specification_error;
 755     }
 756     /* Guest address must be double word aligned */
 757     if (gaddr & 0x07UL) {
 758         goto specification_error;
 759     }
 760
 761     mr = pbdev->pdev->io_regions[pcias].memory;
 762     mr = s390_get_subregion(mr, offset, len);
 763     offset -= mr->addr;
 764
 765     if (!memory_region_access_valid(mr, offset, len, true,
 766                                     MEMTXATTRS_UNSPECIFIED)) {
 767         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
 768         return 0;
 769     }
 770
 771     if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) {
 772         s390_cpu_virt_mem_handle_exc(cpu, ra);
 773         return 0;
 774     }
 775
 776     for (i = 0; i < len / 8; i++) {
 777         result = memory_region_dispatch_write(mr, offset + i * 8,
 778                                               ldq_p(buffer + i * 8), 8,
 779                                               MEMTXATTRS_UNSPECIFIED);
 780         if (result != MEMTX_OK) {
 781             s390_program_interrupt(env, PGM_OPERAND, 6, ra);
 782             return 0;
 783         }
 784     }
 785
 786     setcc(cpu, ZPCI_PCI_LS_OK);
 787     return 0;
 788
 789 specification_error:
 790     s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra);
 791     return 0;
 792 }
 793
 794 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)
 795 {
 796     int ret, len;
 797     uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data));
 798
 799     pbdev->routes.adapter.adapter_id = css_get_adapter_id(
 800                                        CSS_IO_ADAPTER_PCI, isc);
 801     pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t));
 802     len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long);
 803     pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len);
 804
 805     ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
 806     if (ret) {
 807         goto out;
 808     }
 809
 810     ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator);
 811     if (ret) {
 812         goto out;
 813     }
 814
 815     pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb);
 816     pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data));
 817     pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv);
 818     pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data));
 819     pbdev->isc = isc;
 820     pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data));
 821     pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data));
 822
 823     DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
 824     return 0;
 825 out:
 826     release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
 827     release_indicator(&pbdev->routes.adapter, pbdev->indicator);
 828     pbdev->summary_ind = NULL;
 829     pbdev->indicator = NULL;
 830     return ret;
 831 }
 832
 833 int pci_dereg_irqs(S390PCIBusDevice *pbdev)
 834 {
 835     release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
 836     release_indicator(&pbdev->routes.adapter, pbdev->indicator);
 837
 838     pbdev->summary_ind = NULL;
 839     pbdev->indicator = NULL;
 840     pbdev->routes.adapter.summary_addr = 0;
 841     pbdev->routes.adapter.summary_offset = 0;
 842     pbdev->routes.adapter.ind_addr = 0;
 843     pbdev->routes.adapter.ind_offset = 0;
 844     pbdev->isc = 0;
 845     pbdev->noi = 0;
 846     pbdev->sum = 0;
 847
 848     DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
 849     return 0;
 850 }
 851
 852 static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib,
 853                     uintptr_t ra)
 854 {
 855     uint64_t pba = ldq_p(&fib.pba);
 856     uint64_t pal = ldq_p(&fib.pal);
 857     uint64_t g_iota = ldq_p(&fib.iota);
 858     uint8_t dt = (g_iota >> 2) & 0x7;
 859     uint8_t t = (g_iota >> 11) & 0x1;
 860
 861     pba &= ~0xfff;
 862     pal |= 0xfff;
 863     if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) {
 864         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
 865         return -EINVAL;
 866     }
 867
 868     /* currently we only support designation type 1 with translation */
 869     if (!(dt == ZPCI_IOTA_RTTO && t)) {
 870         error_report("unsupported ioat dt %d t %d", dt, t);
 871         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
 872         return -EINVAL;
 873     }
 874
 875     iommu->pba = pba;
 876     iommu->pal = pal;
 877     iommu->g_iota = g_iota;
 878
 879     s390_pci_iommu_enable(iommu);
 880
 881     return 0;
 882 }
 883
 884 void pci_dereg_ioat(S390PCIIOMMU *iommu)
 885 {
 886     s390_pci_iommu_disable(iommu);
 887     iommu->pba = 0;
 888     iommu->pal = 0;
 889     iommu->g_iota = 0;
 890 }
 891
 892 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
 893                         uintptr_t ra)
 894 {
 895     CPUS390XState *env = &cpu->env;
 896     uint8_t oc, dmaas;
 897     uint32_t fh;
 898     ZpciFib fib;
 899     S390PCIBusDevice *pbdev;
 900     uint64_t cc = ZPCI_PCI_LS_OK;
 901
 902     if (env->psw.mask & PSW_MASK_PSTATE) {
 903         s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra);
 904         return 0;
 905     }
 906
 907     oc = env->regs[r1] & 0xff;
 908     dmaas = (env->regs[r1] >> 16) & 0xff;
 909     fh = env->regs[r1] >> 32;
 910
 911     if (fiba & 0x7) {
 912         s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra);
 913         return 0;
 914     }
 915
 916     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 917     if (!pbdev) {
 918         DPRINTF("mpcifc no pci dev fh 0x%x\n", fh);
 919         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 920         return 0;
 921     }
 922
 923     switch (pbdev->state) {
 924     case ZPCI_FS_RESERVED:
 925     case ZPCI_FS_STANDBY:
 926     case ZPCI_FS_DISABLED:
 927     case ZPCI_FS_PERMANENT_ERROR:
 928         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 929         return 0;
 930     default:
 931         break;
 932     }
 933
 934     if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
 935         s390_cpu_virt_mem_handle_exc(cpu, ra);
 936         return 0;
 937     }
 938
 939     if (fib.fmt != 0) {
 940         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
 941         return 0;
 942     }
 943
 944     switch (oc) {
 945     case ZPCI_MOD_FC_REG_INT:
 946         if (pbdev->summary_ind) {
 947             cc = ZPCI_PCI_LS_ERR;
 948             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 949         } else if (reg_irqs(env, pbdev, fib)) {
 950             cc = ZPCI_PCI_LS_ERR;
 951             s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL);
 952         }
 953         break;
 954     case ZPCI_MOD_FC_DEREG_INT:
 955         if (!pbdev->summary_ind) {
 956             cc = ZPCI_PCI_LS_ERR;
 957             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 958         } else {
 959             pci_dereg_irqs(pbdev);
 960         }
 961         break;
 962     case ZPCI_MOD_FC_REG_IOAT:
 963         if (dmaas != 0) {
 964             cc = ZPCI_PCI_LS_ERR;
 965             s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
 966         } else if (pbdev->iommu->enabled) {
 967             cc = ZPCI_PCI_LS_ERR;
 968             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 969         } else if (reg_ioat(env, pbdev->iommu, fib, ra)) {
 970             cc = ZPCI_PCI_LS_ERR;
 971             s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
 972         }
 973         break;
 974     case ZPCI_MOD_FC_DEREG_IOAT:
 975         if (dmaas != 0) {
 976             cc = ZPCI_PCI_LS_ERR;
 977             s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
 978         } else if (!pbdev->iommu->enabled) {
 979             cc = ZPCI_PCI_LS_ERR;
 980             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 981         } else {
 982             pci_dereg_ioat(pbdev->iommu);
 983         }
 984         break;
 985     case ZPCI_MOD_FC_REREG_IOAT:
 986         if (dmaas != 0) {
 987             cc = ZPCI_PCI_LS_ERR;
 988             s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
 989         } else if (!pbdev->iommu->enabled) {
 990             cc = ZPCI_PCI_LS_ERR;
 991             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 992         } else {
 993             pci_dereg_ioat(pbdev->iommu);
 994             if (reg_ioat(env, pbdev->iommu, fib, ra)) {
 995                 cc = ZPCI_PCI_LS_ERR;
 996                 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
 997             }
 998         }
 999         break;
1000     case ZPCI_MOD_FC_RESET_ERROR:
1001         switch (pbdev->state) {
1002         case ZPCI_FS_BLOCKED:
1003         case ZPCI_FS_ERROR:
1004             pbdev->state = ZPCI_FS_ENABLED;
1005             break;
1006         default:
1007             cc = ZPCI_PCI_LS_ERR;
1008             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1009         }
1010         break;
1011     case ZPCI_MOD_FC_RESET_BLOCK:
1012         switch (pbdev->state) {
1013         case ZPCI_FS_ERROR:
1014             pbdev->state = ZPCI_FS_BLOCKED;
1015             break;
1016         default:
1017             cc = ZPCI_PCI_LS_ERR;
1018             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
1019         }
1020         break;
1021     case ZPCI_MOD_FC_SET_MEASURE:
1022         pbdev->fmb_addr = ldq_p(&fib.fmb_addr);
1023         break;
1024     default:
1025         s390_program_interrupt(&cpu->env, PGM_OPERAND, 6, ra);
1026         cc = ZPCI_PCI_LS_ERR;
1027     }
1028
1029     setcc(cpu, cc);
1030     return 0;
1031 }
1032
1033 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
1034                          uintptr_t ra)
1035 {
1036     CPUS390XState *env = &cpu->env;
1037     uint8_t dmaas;
1038     uint32_t fh;
1039     ZpciFib fib;
1040     S390PCIBusDevice *pbdev;
1041     uint32_t data;
1042     uint64_t cc = ZPCI_PCI_LS_OK;
1043
1044     if (env->psw.mask & PSW_MASK_PSTATE) {
1045         s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra);
1046         return 0;
1047     }
1048
1049     fh = env->regs[r1] >> 32;
1050     dmaas = (env->regs[r1] >> 16) & 0xff;
1051
1052     if (dmaas) {
1053         setcc(cpu, ZPCI_PCI_LS_ERR);
1054         s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS);
1055         return 0;
1056     }
1057
1058     if (fiba & 0x7) {
1059         s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra);
1060         return 0;
1061     }
1062
1063     pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX);
1064     if (!pbdev) {
1065         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1066         return 0;
1067     }
1068
1069     memset(&fib, 0, sizeof(fib));
1070
1071     switch (pbdev->state) {
1072     case ZPCI_FS_RESERVED:
1073     case ZPCI_FS_STANDBY:
1074         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1075         return 0;
1076     case ZPCI_FS_DISABLED:
1077         if (fh & FH_MASK_ENABLE) {
1078             setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1079             return 0;
1080         }
1081         goto out;
1082     /* BLOCKED bit is set to one coincident with the setting of ERROR bit.
1083      * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */
1084     case ZPCI_FS_ERROR:
1085         fib.fc |= 0x20;
1086     case ZPCI_FS_BLOCKED:
1087         fib.fc |= 0x40;
1088     case ZPCI_FS_ENABLED:
1089         fib.fc |= 0x80;
1090         if (pbdev->iommu->enabled) {
1091             fib.fc |= 0x10;
1092         }
1093         if (!(fh & FH_MASK_ENABLE)) {
1094             env->regs[r1] |= 1ULL << 63;
1095         }
1096         break;
1097     case ZPCI_FS_PERMANENT_ERROR:
1098         setcc(cpu, ZPCI_PCI_LS_ERR);
1099         s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR);
1100         return 0;
1101     }
1102
1103     stq_p(&fib.pba, pbdev->iommu->pba);
1104     stq_p(&fib.pal, pbdev->iommu->pal);
1105     stq_p(&fib.iota, pbdev->iommu->g_iota);
1106     stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);
1107     stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);
1108     stq_p(&fib.fmb_addr, pbdev->fmb_addr);
1109
1110     data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |
1111            ((uint32_t)pbdev->routes.adapter.ind_offset << 8) |
1112            ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;
1113     stl_p(&fib.data, data);
1114
1115 out:
1116     if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
1117         s390_cpu_virt_mem_handle_exc(cpu, ra);
1118         return 0;
1119     }
1120
1121     setcc(cpu, cc);
1122     return 0;
1123 }