hw/s390x/s390-pci-inst.c

   1 /*
   2  * s390 PCI instructions
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu-common.h"
  16 #include "cpu.h"
  17 #include "s390-pci-inst.h"
  18 #include "s390-pci-bus.h"
  19 #include "exec/memory-internal.h"
  20 #include "qemu/error-report.h"
  21 #include "sysemu/hw_accel.h"
  22
  23 #ifndef DEBUG_S390PCI_INST
  24 #define DEBUG_S390PCI_INST  0
  25 #endif
  26
  27 #define DPRINTF(fmt, ...)                                          \
  28     do {                                                           \
  29         if (DEBUG_S390PCI_INST) {                                  \
  30             fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \
  31         }                                                          \
  32     } while (0)
  33
  34 static void s390_set_status_code(CPUS390XState *env,
  35                                  uint8_t r, uint64_t status_code)
  36 {
  37     env->regs[r] &= ~0xff000000ULL;
  38     env->regs[r] |= (status_code & 0xff) << 24;
  39 }
  40
  41 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)
  42 {
  43     S390PCIBusDevice *pbdev = NULL;
  44     S390pciState *s = s390_get_phb();
  45     uint32_t res_code, initial_l2, g_l2;
  46     int rc, i;
  47     uint64_t resume_token;
  48
  49     rc = 0;
  50     if (lduw_p(&rrb->request.hdr.len) != 32) {
  51         res_code = CLP_RC_LEN;
  52         rc = -EINVAL;
  53         goto out;
  54     }
  55
  56     if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) {
  57         res_code = CLP_RC_FMT;
  58         rc = -EINVAL;
  59         goto out;
  60     }
  61
  62     if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 ||
  63         ldq_p(&rrb->request.reserved1) != 0) {
  64         res_code = CLP_RC_RESNOT0;
  65         rc = -EINVAL;
  66         goto out;
  67     }
  68
  69     resume_token = ldq_p(&rrb->request.resume_token);
  70
  71     if (resume_token) {
  72         pbdev = s390_pci_find_dev_by_idx(s, resume_token);
  73         if (!pbdev) {
  74             res_code = CLP_RC_LISTPCI_BADRT;
  75             rc = -EINVAL;
  76             goto out;
  77         }
  78     } else {
  79         pbdev = s390_pci_find_next_avail_dev(s, NULL);
  80     }
  81
  82     if (lduw_p(&rrb->response.hdr.len) < 48) {
  83         res_code = CLP_RC_8K;
  84         rc = -EINVAL;
  85         goto out;
  86     }
  87
  88     initial_l2 = lduw_p(&rrb->response.hdr.len);
  89     if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry)
  90         != 0) {
  91         res_code = CLP_RC_LEN;
  92         rc = -EINVAL;
  93         *cc = 3;
  94         goto out;
  95     }
  96
  97     stl_p(&rrb->response.fmt, 0);
  98     stq_p(&rrb->response.reserved1, 0);
  99     stl_p(&rrb->response.mdd, FH_MASK_SHM);
 100     stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS);
 101     rrb->response.flags = UID_CHECKING_ENABLED;
 102     rrb->response.entry_size = sizeof(ClpFhListEntry);
 103
 104     i = 0;
 105     g_l2 = LIST_PCI_HDR_LEN;
 106     while (g_l2 < initial_l2 && pbdev) {
 107         stw_p(&rrb->response.fh_list[i].device_id,
 108             pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID));
 109         stw_p(&rrb->response.fh_list[i].vendor_id,
 110             pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID));
 111         /* Ignore RESERVED devices. */
 112         stl_p(&rrb->response.fh_list[i].config,
 113             pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31);
 114         stl_p(&rrb->response.fh_list[i].fid, pbdev->fid);
 115         stl_p(&rrb->response.fh_list[i].fh, pbdev->fh);
 116
 117         g_l2 += sizeof(ClpFhListEntry);
 118         /* Add endian check for DPRINTF? */
 119         DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
 120                 g_l2,
 121                 lduw_p(&rrb->response.fh_list[i].vendor_id),
 122                 lduw_p(&rrb->response.fh_list[i].device_id),
 123                 ldl_p(&rrb->response.fh_list[i].fid),
 124                 ldl_p(&rrb->response.fh_list[i].fh));
 125         pbdev = s390_pci_find_next_avail_dev(s, pbdev);
 126         i++;
 127     }
 128
 129     if (!pbdev) {
 130         resume_token = 0;
 131     } else {
 132         resume_token = pbdev->fh & FH_MASK_INDEX;
 133     }
 134     stq_p(&rrb->response.resume_token, resume_token);
 135     stw_p(&rrb->response.hdr.len, g_l2);
 136     stw_p(&rrb->response.hdr.rsp, CLP_RC_OK);
 137 out:
 138     if (rc) {
 139         DPRINTF("list pci failed rc 0x%x\n", rc);
 140         stw_p(&rrb->response.hdr.rsp, res_code);
 141     }
 142     return rc;
 143 }
 144
 145 int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra)
 146 {
 147     ClpReqHdr *reqh;
 148     ClpRspHdr *resh;
 149     S390PCIBusDevice *pbdev;
 150     uint32_t req_len;
 151     uint32_t res_len;
 152     uint8_t buffer[4096 * 2];
 153     uint8_t cc = 0;
 154     CPUS390XState *env = &cpu->env;
 155     S390pciState *s = s390_get_phb();
 156     int i;
 157
 158     cpu_synchronize_state(CPU(cpu));
 159
 160     if (env->psw.mask & PSW_MASK_PSTATE) {
 161         s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
 162         return 0;
 163     }
 164
 165     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) {
 166         s390_cpu_virt_mem_handle_exc(cpu, ra);
 167         return 0;
 168     }
 169     reqh = (ClpReqHdr *)buffer;
 170     req_len = lduw_p(&reqh->len);
 171     if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) {
 172         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 173         return 0;
 174     }
 175
 176     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
 177                                req_len + sizeof(*resh))) {
 178         s390_cpu_virt_mem_handle_exc(cpu, ra);
 179         return 0;
 180     }
 181     resh = (ClpRspHdr *)(buffer + req_len);
 182     res_len = lduw_p(&resh->len);
 183     if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) {
 184         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 185         return 0;
 186     }
 187     if ((req_len + res_len) > 8192) {
 188         s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 189         return 0;
 190     }
 191
 192     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
 193                                req_len + res_len)) {
 194         s390_cpu_virt_mem_handle_exc(cpu, ra);
 195         return 0;
 196     }
 197
 198     if (req_len != 32) {
 199         stw_p(&resh->rsp, CLP_RC_LEN);
 200         goto out;
 201     }
 202
 203     switch (lduw_p(&reqh->cmd)) {
 204     case CLP_LIST_PCI: {
 205         ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer;
 206         list_pci(rrb, &cc);
 207         break;
 208     }
 209     case CLP_SET_PCI_FN: {
 210         ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh;
 211         ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh;
 212
 213         pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh));
 214         if (!pbdev) {
 215                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);
 216                 goto out;
 217         }
 218
 219         switch (reqsetpci->oc) {
 220         case CLP_SET_ENABLE_PCI_FN:
 221             switch (reqsetpci->ndas) {
 222             case 0:
 223                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS);
 224                 goto out;
 225             case 1:
 226                 break;
 227             default:
 228                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES);
 229                 goto out;
 230             }
 231
 232             if (pbdev->fh & FH_MASK_ENABLE) {
 233                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
 234                 goto out;
 235             }
 236
 237             pbdev->fh |= FH_MASK_ENABLE;
 238             pbdev->state = ZPCI_FS_ENABLED;
 239             stl_p(&ressetpci->fh, pbdev->fh);
 240             stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
 241             break;
 242         case CLP_SET_DISABLE_PCI_FN:
 243             if (!(pbdev->fh & FH_MASK_ENABLE)) {
 244                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
 245                 goto out;
 246             }
 247             device_reset(DEVICE(pbdev));
 248             pbdev->fh &= ~FH_MASK_ENABLE;
 249             pbdev->state = ZPCI_FS_DISABLED;
 250             stl_p(&ressetpci->fh, pbdev->fh);
 251             stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
 252             break;
 253         default:
 254             DPRINTF("unknown set pci command\n");
 255             stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
 256             break;
 257         }
 258         break;
 259     }
 260     case CLP_QUERY_PCI_FN: {
 261         ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh;
 262         ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh;
 263
 264         pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh));
 265         if (!pbdev) {
 266             DPRINTF("query pci no pci dev\n");
 267             stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH);
 268             goto out;
 269         }
 270
 271         for (i = 0; i < PCI_BAR_COUNT; i++) {
 272             uint32_t data = pci_get_long(pbdev->pdev->config +
 273                 PCI_BASE_ADDRESS_0 + (i * 4));
 274
 275             stl_p(&resquery->bar[i], data);
 276             resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ?
 277                                     ctz64(pbdev->pdev->io_regions[i].size) : 0;
 278             DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i,
 279                     ldl_p(&resquery->bar[i]),
 280                     pbdev->pdev->io_regions[i].size,
 281                     resquery->bar_size[i]);
 282         }
 283
 284         stq_p(&resquery->sdma, ZPCI_SDMA_ADDR);
 285         stq_p(&resquery->edma, ZPCI_EDMA_ADDR);
 286         stl_p(&resquery->fid, pbdev->fid);
 287         stw_p(&resquery->pchid, 0);
 288         stw_p(&resquery->ug, 1);
 289         stl_p(&resquery->uid, pbdev->uid);
 290         stw_p(&resquery->hdr.rsp, CLP_RC_OK);
 291         break;
 292     }
 293     case CLP_QUERY_PCI_FNGRP: {
 294         ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh;
 295         resgrp->fr = 1;
 296         stq_p(&resgrp->dasm, 0);
 297         stq_p(&resgrp->msia, ZPCI_MSI_ADDR);
 298         stw_p(&resgrp->mui, 0);
 299         stw_p(&resgrp->i, 128);
 300         stw_p(&resgrp->maxstbl, 128);
 301         resgrp->version = 0;
 302
 303         stw_p(&resgrp->hdr.rsp, CLP_RC_OK);
 304         break;
 305     }
 306     default:
 307         DPRINTF("unknown clp command\n");
 308         stw_p(&resh->rsp, CLP_RC_CMD);
 309         break;
 310     }
 311
 312 out:
 313     if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer,
 314                                 req_len + res_len)) {
 315         s390_cpu_virt_mem_handle_exc(cpu, ra);
 316         return 0;
 317     }
 318     setcc(cpu, cc);
 319     return 0;
 320 }
 321
 322 /**
 323  * Swap data contained in s390x big endian registers to little endian
 324  * PCI bars.
 325  *
 326  * @ptr: a pointer to a uint64_t data field
 327  * @len: the length of the valid data, must be 1,2,4 or 8
 328  */
 329 static int zpci_endian_swap(uint64_t *ptr, uint8_t len)
 330 {
 331     uint64_t data = *ptr;
 332
 333     switch (len) {
 334     case 1:
 335         break;
 336     case 2:
 337         data = bswap16(data);
 338         break;
 339     case 4:
 340         data = bswap32(data);
 341         break;
 342     case 8:
 343         data = bswap64(data);
 344         break;
 345     default:
 346         return -EINVAL;
 347     }
 348     *ptr = data;
 349     return 0;
 350 }
 351
 352 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
 353 {
 354     CPUS390XState *env = &cpu->env;
 355     S390PCIBusDevice *pbdev;
 356     uint64_t offset;
 357     uint64_t data;
 358     MemoryRegion *mr;
 359     MemTxResult result;
 360     uint8_t len;
 361     uint32_t fh;
 362     uint8_t pcias;
 363
 364     cpu_synchronize_state(CPU(cpu));
 365
 366     if (env->psw.mask & PSW_MASK_PSTATE) {
 367         s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
 368         return 0;
 369     }
 370
 371     if (r2 & 0x1) {
 372         s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
 373         return 0;
 374     }
 375
 376     fh = env->regs[r2] >> 32;
 377     pcias = (env->regs[r2] >> 16) & 0xf;
 378     len = env->regs[r2] & 0xf;
 379     offset = env->regs[r2 + 1];
 380
 381     if (!(fh & FH_MASK_ENABLE)) {
 382         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 383         return 0;
 384     }
 385
 386     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 387     if (!pbdev) {
 388         DPRINTF("pcilg no pci dev\n");
 389         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 390         return 0;
 391     }
 392
 393     switch (pbdev->state) {
 394     case ZPCI_FS_PERMANENT_ERROR:
 395     case ZPCI_FS_ERROR:
 396         setcc(cpu, ZPCI_PCI_LS_ERR);
 397         s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
 398         return 0;
 399     default:
 400         break;
 401     }
 402
 403     switch (pcias) {
 404     case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX:
 405         if (!len || (len > (8 - (offset & 0x7)))) {
 406             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 407             return 0;
 408         }
 409         mr = pbdev->pdev->io_regions[pcias].memory;
 410         result = memory_region_dispatch_read(mr, offset, &data, len,
 411                                              MEMTXATTRS_UNSPECIFIED);
 412         if (result != MEMTX_OK) {
 413             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 414             return 0;
 415         }
 416         break;
 417     case ZPCI_CONFIG_BAR:
 418         if (!len || (len > (4 - (offset & 0x3))) || len == 3) {
 419             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 420             return 0;
 421         }
 422         data =  pci_host_config_read_common(
 423                    pbdev->pdev, offset, pci_config_size(pbdev->pdev), len);
 424
 425         if (zpci_endian_swap(&data, len)) {
 426             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 427             return 0;
 428         }
 429         break;
 430     default:
 431         DPRINTF("pcilg invalid space\n");
 432         setcc(cpu, ZPCI_PCI_LS_ERR);
 433         s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
 434         return 0;
 435     }
 436
 437     env->regs[r1] = data;
 438     setcc(cpu, ZPCI_PCI_LS_OK);
 439     return 0;
 440 }
 441
 442 static int trap_msix(S390PCIBusDevice *pbdev, uint64_t offset, uint8_t pcias)
 443 {
 444     if (pbdev->msix.available && pbdev->msix.table_bar == pcias &&
 445         offset >= pbdev->msix.table_offset &&
 446         offset < (pbdev->msix.table_offset +
 447                   pbdev->msix.entries * PCI_MSIX_ENTRY_SIZE)) {
 448         return 1;
 449     } else {
 450         return 0;
 451     }
 452 }
 453
 454 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
 455 {
 456     CPUS390XState *env = &cpu->env;
 457     uint64_t offset, data;
 458     S390PCIBusDevice *pbdev;
 459     MemoryRegion *mr;
 460     MemTxResult result;
 461     uint8_t len;
 462     uint32_t fh;
 463     uint8_t pcias;
 464
 465     cpu_synchronize_state(CPU(cpu));
 466
 467     if (env->psw.mask & PSW_MASK_PSTATE) {
 468         s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
 469         return 0;
 470     }
 471
 472     if (r2 & 0x1) {
 473         s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
 474         return 0;
 475     }
 476
 477     fh = env->regs[r2] >> 32;
 478     pcias = (env->regs[r2] >> 16) & 0xf;
 479     len = env->regs[r2] & 0xf;
 480     offset = env->regs[r2 + 1];
 481     data = env->regs[r1];
 482
 483     if (!(fh & FH_MASK_ENABLE)) {
 484         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 485         return 0;
 486     }
 487
 488     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 489     if (!pbdev) {
 490         DPRINTF("pcistg no pci dev\n");
 491         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 492         return 0;
 493     }
 494
 495     switch (pbdev->state) {
 496     /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED
 497      * are already covered by the FH_MASK_ENABLE check above
 498      */
 499     case ZPCI_FS_PERMANENT_ERROR:
 500     case ZPCI_FS_ERROR:
 501         setcc(cpu, ZPCI_PCI_LS_ERR);
 502         s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
 503         return 0;
 504     default:
 505         break;
 506     }
 507
 508     switch (pcias) {
 509         /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */
 510     case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX:
 511         /* Check length:
 512          * A length of 0 is invalid and length should not cross a double word
 513          */
 514         if (!len || (len > (8 - (offset & 0x7)))) {
 515             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 516             return 0;
 517         }
 518
 519         if (trap_msix(pbdev, offset, pcias)) {
 520             offset = offset - pbdev->msix.table_offset;
 521             mr = &pbdev->pdev->msix_table_mmio;
 522         } else {
 523             mr = pbdev->pdev->io_regions[pcias].memory;
 524         }
 525
 526         result = memory_region_dispatch_write(mr, offset, data, len,
 527                                      MEMTXATTRS_UNSPECIFIED);
 528         if (result != MEMTX_OK) {
 529             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 530             return 0;
 531         }
 532         break;
 533     case ZPCI_CONFIG_BAR:
 534         /* ZPCI uses the pseudo BAR number 15 as configuration space */
 535         /* possible access lengths are 1,2,4 and must not cross a word */
 536         if (!len || (len > (4 - (offset & 0x3))) || len == 3) {
 537             s390_program_interrupt(env, PGM_OPERAND, 4, ra);
 538             return 0;
 539         }
 540         /* len = 1,2,4 so we do not need to test */
 541         zpci_endian_swap(&data, len);
 542         pci_host_config_write_common(pbdev->pdev, offset,
 543                                      pci_config_size(pbdev->pdev),
 544                                      data, len);
 545         break;
 546     default:
 547         DPRINTF("pcistg invalid space\n");
 548         setcc(cpu, ZPCI_PCI_LS_ERR);
 549         s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
 550         return 0;
 551     }
 552
 553     setcc(cpu, ZPCI_PCI_LS_OK);
 554     return 0;
 555 }
 556
 557 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra)
 558 {
 559     CPUS390XState *env = &cpu->env;
 560     uint32_t fh;
 561     S390PCIBusDevice *pbdev;
 562     S390PCIIOMMU *iommu;
 563     hwaddr start, end;
 564     IOMMUTLBEntry entry;
 565     IOMMUMemoryRegion *iommu_mr;
 566     IOMMUMemoryRegionClass *imrc;
 567
 568     cpu_synchronize_state(CPU(cpu));
 569
 570     if (env->psw.mask & PSW_MASK_PSTATE) {
 571         s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra);
 572         goto out;
 573     }
 574
 575     if (r2 & 0x1) {
 576         s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra);
 577         goto out;
 578     }
 579
 580     fh = env->regs[r1] >> 32;
 581     start = env->regs[r2];
 582     end = start + env->regs[r2 + 1];
 583
 584     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 585     if (!pbdev) {
 586         DPRINTF("rpcit no pci dev\n");
 587         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 588         goto out;
 589     }
 590
 591     switch (pbdev->state) {
 592     case ZPCI_FS_RESERVED:
 593     case ZPCI_FS_STANDBY:
 594     case ZPCI_FS_DISABLED:
 595     case ZPCI_FS_PERMANENT_ERROR:
 596         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 597         return 0;
 598     case ZPCI_FS_ERROR:
 599         setcc(cpu, ZPCI_PCI_LS_ERR);
 600         s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER);
 601         return 0;
 602     default:
 603         break;
 604     }
 605
 606     iommu = pbdev->iommu;
 607     if (!iommu->g_iota) {
 608         pbdev->state = ZPCI_FS_ERROR;
 609         setcc(cpu, ZPCI_PCI_LS_ERR);
 610         s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES);
 611         s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid,
 612                                       start, 0);
 613         goto out;
 614     }
 615
 616     if (end < iommu->pba || start > iommu->pal) {
 617         pbdev->state = ZPCI_FS_ERROR;
 618         setcc(cpu, ZPCI_PCI_LS_ERR);
 619         s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES);
 620         s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid,
 621                                       start, 0);
 622         goto out;
 623     }
 624
 625     iommu_mr = &iommu->iommu_mr;
 626     imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
 627
 628     while (start < end) {
 629         entry = imrc->translate(iommu_mr, start, IOMMU_NONE);
 630
 631         if (!entry.translated_addr) {
 632             pbdev->state = ZPCI_FS_ERROR;
 633             setcc(cpu, ZPCI_PCI_LS_ERR);
 634             s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES);
 635             s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid,
 636                                           start, ERR_EVENT_Q_BIT);
 637             goto out;
 638         }
 639
 640         memory_region_notify_iommu(iommu_mr, entry);
 641         start += entry.addr_mask + 1;
 642     }
 643
 644     setcc(cpu, ZPCI_PCI_LS_OK);
 645 out:
 646     return 0;
 647 }
 648
 649 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
 650                         uint8_t ar, uintptr_t ra)
 651 {
 652     CPUS390XState *env = &cpu->env;
 653     S390PCIBusDevice *pbdev;
 654     MemoryRegion *mr;
 655     MemTxResult result;
 656     uint64_t offset;
 657     int i;
 658     uint32_t fh;
 659     uint8_t pcias;
 660     uint8_t len;
 661     uint8_t buffer[128];
 662
 663     if (env->psw.mask & PSW_MASK_PSTATE) {
 664         s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra);
 665         return 0;
 666     }
 667
 668     fh = env->regs[r1] >> 32;
 669     pcias = (env->regs[r1] >> 16) & 0xf;
 670     len = env->regs[r1] & 0xff;
 671     offset = env->regs[r3];
 672
 673     if (!(fh & FH_MASK_ENABLE)) {
 674         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 675         return 0;
 676     }
 677
 678     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 679     if (!pbdev) {
 680         DPRINTF("pcistb no pci dev fh 0x%x\n", fh);
 681         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 682         return 0;
 683     }
 684
 685     switch (pbdev->state) {
 686     case ZPCI_FS_PERMANENT_ERROR:
 687     case ZPCI_FS_ERROR:
 688         setcc(cpu, ZPCI_PCI_LS_ERR);
 689         s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED);
 690         return 0;
 691     default:
 692         break;
 693     }
 694
 695     if (pcias > ZPCI_IO_BAR_MAX) {
 696         DPRINTF("pcistb invalid space\n");
 697         setcc(cpu, ZPCI_PCI_LS_ERR);
 698         s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS);
 699         return 0;
 700     }
 701
 702     /* Verify the address, offset and length */
 703     /* offset must be a multiple of 8 */
 704     if (offset % 8) {
 705         goto specification_error;
 706     }
 707     /* Length must be greater than 8, a multiple of 8 */
 708     /* and not greater than maxstbl */
 709     if ((len <= 8) || (len % 8) || (len > pbdev->maxstbl)) {
 710         goto specification_error;
 711     }
 712     /* Do not cross a 4K-byte boundary */
 713     if (((offset & 0xfff) + len) > 0x1000) {
 714         goto specification_error;
 715     }
 716     /* Guest address must be double word aligned */
 717     if (gaddr & 0x07UL) {
 718         goto specification_error;
 719     }
 720
 721     mr = pbdev->pdev->io_regions[pcias].memory;
 722     if (!memory_region_access_valid(mr, offset, len, true)) {
 723         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
 724         return 0;
 725     }
 726
 727     if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) {
 728         s390_cpu_virt_mem_handle_exc(cpu, ra);
 729         return 0;
 730     }
 731
 732     for (i = 0; i < len / 8; i++) {
 733         result = memory_region_dispatch_write(mr, offset + i * 8,
 734                                               ldq_p(buffer + i * 8), 8,
 735                                               MEMTXATTRS_UNSPECIFIED);
 736         if (result != MEMTX_OK) {
 737             s390_program_interrupt(env, PGM_OPERAND, 6, ra);
 738             return 0;
 739         }
 740     }
 741
 742     setcc(cpu, ZPCI_PCI_LS_OK);
 743     return 0;
 744
 745 specification_error:
 746     s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra);
 747     return 0;
 748 }
 749
 750 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)
 751 {
 752     int ret, len;
 753     uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data));
 754
 755     pbdev->routes.adapter.adapter_id = css_get_adapter_id(
 756                                        CSS_IO_ADAPTER_PCI, isc);
 757     pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t));
 758     len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long);
 759     pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len);
 760
 761     ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
 762     if (ret) {
 763         goto out;
 764     }
 765
 766     ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator);
 767     if (ret) {
 768         goto out;
 769     }
 770
 771     pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb);
 772     pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data));
 773     pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv);
 774     pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data));
 775     pbdev->isc = isc;
 776     pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data));
 777     pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data));
 778
 779     DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
 780     return 0;
 781 out:
 782     release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
 783     release_indicator(&pbdev->routes.adapter, pbdev->indicator);
 784     pbdev->summary_ind = NULL;
 785     pbdev->indicator = NULL;
 786     return ret;
 787 }
 788
 789 int pci_dereg_irqs(S390PCIBusDevice *pbdev)
 790 {
 791     release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
 792     release_indicator(&pbdev->routes.adapter, pbdev->indicator);
 793
 794     pbdev->summary_ind = NULL;
 795     pbdev->indicator = NULL;
 796     pbdev->routes.adapter.summary_addr = 0;
 797     pbdev->routes.adapter.summary_offset = 0;
 798     pbdev->routes.adapter.ind_addr = 0;
 799     pbdev->routes.adapter.ind_offset = 0;
 800     pbdev->isc = 0;
 801     pbdev->noi = 0;
 802     pbdev->sum = 0;
 803
 804     DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
 805     return 0;
 806 }
 807
 808 static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib,
 809                     uintptr_t ra)
 810 {
 811     uint64_t pba = ldq_p(&fib.pba);
 812     uint64_t pal = ldq_p(&fib.pal);
 813     uint64_t g_iota = ldq_p(&fib.iota);
 814     uint8_t dt = (g_iota >> 2) & 0x7;
 815     uint8_t t = (g_iota >> 11) & 0x1;
 816
 817     if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) {
 818         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
 819         return -EINVAL;
 820     }
 821
 822     /* currently we only support designation type 1 with translation */
 823     if (!(dt == ZPCI_IOTA_RTTO && t)) {
 824         error_report("unsupported ioat dt %d t %d", dt, t);
 825         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
 826         return -EINVAL;
 827     }
 828
 829     iommu->pba = pba;
 830     iommu->pal = pal;
 831     iommu->g_iota = g_iota;
 832
 833     s390_pci_iommu_enable(iommu);
 834
 835     return 0;
 836 }
 837
 838 void pci_dereg_ioat(S390PCIIOMMU *iommu)
 839 {
 840     s390_pci_iommu_disable(iommu);
 841     iommu->pba = 0;
 842     iommu->pal = 0;
 843     iommu->g_iota = 0;
 844 }
 845
 846 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
 847                         uintptr_t ra)
 848 {
 849     CPUS390XState *env = &cpu->env;
 850     uint8_t oc, dmaas;
 851     uint32_t fh;
 852     ZpciFib fib;
 853     S390PCIBusDevice *pbdev;
 854     uint64_t cc = ZPCI_PCI_LS_OK;
 855
 856     if (env->psw.mask & PSW_MASK_PSTATE) {
 857         s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra);
 858         return 0;
 859     }
 860
 861     oc = env->regs[r1] & 0xff;
 862     dmaas = (env->regs[r1] >> 16) & 0xff;
 863     fh = env->regs[r1] >> 32;
 864
 865     if (fiba & 0x7) {
 866         s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra);
 867         return 0;
 868     }
 869
 870     pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
 871     if (!pbdev) {
 872         DPRINTF("mpcifc no pci dev fh 0x%x\n", fh);
 873         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 874         return 0;
 875     }
 876
 877     switch (pbdev->state) {
 878     case ZPCI_FS_RESERVED:
 879     case ZPCI_FS_STANDBY:
 880     case ZPCI_FS_DISABLED:
 881     case ZPCI_FS_PERMANENT_ERROR:
 882         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 883         return 0;
 884     default:
 885         break;
 886     }
 887
 888     if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
 889         s390_cpu_virt_mem_handle_exc(cpu, ra);
 890         return 0;
 891     }
 892
 893     if (fib.fmt != 0) {
 894         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
 895         return 0;
 896     }
 897
 898     switch (oc) {
 899     case ZPCI_MOD_FC_REG_INT:
 900         if (pbdev->summary_ind) {
 901             cc = ZPCI_PCI_LS_ERR;
 902             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 903         } else if (reg_irqs(env, pbdev, fib)) {
 904             cc = ZPCI_PCI_LS_ERR;
 905             s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL);
 906         }
 907         break;
 908     case ZPCI_MOD_FC_DEREG_INT:
 909         if (!pbdev->summary_ind) {
 910             cc = ZPCI_PCI_LS_ERR;
 911             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 912         } else {
 913             pci_dereg_irqs(pbdev);
 914         }
 915         break;
 916     case ZPCI_MOD_FC_REG_IOAT:
 917         if (dmaas != 0) {
 918             cc = ZPCI_PCI_LS_ERR;
 919             s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
 920         } else if (pbdev->iommu->enabled) {
 921             cc = ZPCI_PCI_LS_ERR;
 922             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 923         } else if (reg_ioat(env, pbdev->iommu, fib, ra)) {
 924             cc = ZPCI_PCI_LS_ERR;
 925             s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
 926         }
 927         break;
 928     case ZPCI_MOD_FC_DEREG_IOAT:
 929         if (dmaas != 0) {
 930             cc = ZPCI_PCI_LS_ERR;
 931             s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
 932         } else if (!pbdev->iommu->enabled) {
 933             cc = ZPCI_PCI_LS_ERR;
 934             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 935         } else {
 936             pci_dereg_ioat(pbdev->iommu);
 937         }
 938         break;
 939     case ZPCI_MOD_FC_REREG_IOAT:
 940         if (dmaas != 0) {
 941             cc = ZPCI_PCI_LS_ERR;
 942             s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
 943         } else if (!pbdev->iommu->enabled) {
 944             cc = ZPCI_PCI_LS_ERR;
 945             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 946         } else {
 947             pci_dereg_ioat(pbdev->iommu);
 948             if (reg_ioat(env, pbdev->iommu, fib, ra)) {
 949                 cc = ZPCI_PCI_LS_ERR;
 950                 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
 951             }
 952         }
 953         break;
 954     case ZPCI_MOD_FC_RESET_ERROR:
 955         switch (pbdev->state) {
 956         case ZPCI_FS_BLOCKED:
 957         case ZPCI_FS_ERROR:
 958             pbdev->state = ZPCI_FS_ENABLED;
 959             break;
 960         default:
 961             cc = ZPCI_PCI_LS_ERR;
 962             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 963         }
 964         break;
 965     case ZPCI_MOD_FC_RESET_BLOCK:
 966         switch (pbdev->state) {
 967         case ZPCI_FS_ERROR:
 968             pbdev->state = ZPCI_FS_BLOCKED;
 969             break;
 970         default:
 971             cc = ZPCI_PCI_LS_ERR;
 972             s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
 973         }
 974         break;
 975     case ZPCI_MOD_FC_SET_MEASURE:
 976         pbdev->fmb_addr = ldq_p(&fib.fmb_addr);
 977         break;
 978     default:
 979         s390_program_interrupt(&cpu->env, PGM_OPERAND, 6, ra);
 980         cc = ZPCI_PCI_LS_ERR;
 981     }
 982
 983     setcc(cpu, cc);
 984     return 0;
 985 }
 986
 987 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar,
 988                          uintptr_t ra)
 989 {
 990     CPUS390XState *env = &cpu->env;
 991     uint8_t dmaas;
 992     uint32_t fh;
 993     ZpciFib fib;
 994     S390PCIBusDevice *pbdev;
 995     uint32_t data;
 996     uint64_t cc = ZPCI_PCI_LS_OK;
 997
 998     if (env->psw.mask & PSW_MASK_PSTATE) {
 999         s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra);
1000         return 0;
1001     }
1002
1003     fh = env->regs[r1] >> 32;
1004     dmaas = (env->regs[r1] >> 16) & 0xff;
1005
1006     if (dmaas) {
1007         setcc(cpu, ZPCI_PCI_LS_ERR);
1008         s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS);
1009         return 0;
1010     }
1011
1012     if (fiba & 0x7) {
1013         s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra);
1014         return 0;
1015     }
1016
1017     pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX);
1018     if (!pbdev) {
1019         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1020         return 0;
1021     }
1022
1023     memset(&fib, 0, sizeof(fib));
1024
1025     switch (pbdev->state) {
1026     case ZPCI_FS_RESERVED:
1027     case ZPCI_FS_STANDBY:
1028         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1029         return 0;
1030     case ZPCI_FS_DISABLED:
1031         if (fh & FH_MASK_ENABLE) {
1032             setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
1033             return 0;
1034         }
1035         goto out;
1036     /* BLOCKED bit is set to one coincident with the setting of ERROR bit.
1037      * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */
1038     case ZPCI_FS_ERROR:
1039         fib.fc |= 0x20;
1040     case ZPCI_FS_BLOCKED:
1041         fib.fc |= 0x40;
1042     case ZPCI_FS_ENABLED:
1043         fib.fc |= 0x80;
1044         if (pbdev->iommu->enabled) {
1045             fib.fc |= 0x10;
1046         }
1047         if (!(fh & FH_MASK_ENABLE)) {
1048             env->regs[r1] |= 1ULL << 63;
1049         }
1050         break;
1051     case ZPCI_FS_PERMANENT_ERROR:
1052         setcc(cpu, ZPCI_PCI_LS_ERR);
1053         s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR);
1054         return 0;
1055     }
1056
1057     stq_p(&fib.pba, pbdev->iommu->pba);
1058     stq_p(&fib.pal, pbdev->iommu->pal);
1059     stq_p(&fib.iota, pbdev->iommu->g_iota);
1060     stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);
1061     stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);
1062     stq_p(&fib.fmb_addr, pbdev->fmb_addr);
1063
1064     data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |
1065            ((uint32_t)pbdev->routes.adapter.ind_offset << 8) |
1066            ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;
1067     stl_p(&fib.data, data);
1068
1069 out:
1070     if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
1071         s390_cpu_virt_mem_handle_exc(cpu, ra);
1072         return 0;
1073     }
1074
1075     setcc(cpu, cc);
1076     return 0;
1077 }