hw/scsi/esp-pci.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  * Copyright (c) 2012 Herve Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/pci/pci_device.h"
  28 #include "hw/irq.h"
  29 #include "hw/nvram/eeprom93xx.h"
  30 #include "hw/scsi/esp.h"
  31 #include "migration/vmstate.h"
  32 #include "trace.h"
  33 #include "qapi/error.h"
  34 #include "qemu/log.h"
  35 #include "qemu/module.h"
  36 #include "qom/object.h"
  37
  38 #define TYPE_AM53C974_DEVICE "am53c974"
  39
  40 typedef struct PCIESPState PCIESPState;
  41 DECLARE_INSTANCE_CHECKER(PCIESPState, PCI_ESP,
  42                          TYPE_AM53C974_DEVICE)
  43
  44 #define DMA_CMD   0x0
  45 #define DMA_STC   0x1
  46 #define DMA_SPA   0x2
  47 #define DMA_WBC   0x3
  48 #define DMA_WAC   0x4
  49 #define DMA_STAT  0x5
  50 #define DMA_SMDLA 0x6
  51 #define DMA_WMAC  0x7
  52
  53 #define DMA_CMD_MASK   0x03
  54 #define DMA_CMD_DIAG   0x04
  55 #define DMA_CMD_MDL    0x10
  56 #define DMA_CMD_INTE_P 0x20
  57 #define DMA_CMD_INTE_D 0x40
  58 #define DMA_CMD_DIR    0x80
  59
  60 #define DMA_STAT_PWDN    0x01
  61 #define DMA_STAT_ERROR   0x02
  62 #define DMA_STAT_ABORT   0x04
  63 #define DMA_STAT_DONE    0x08
  64 #define DMA_STAT_SCSIINT 0x10
  65 #define DMA_STAT_BCMBLT  0x20
  66
  67 #define SBAC_STATUS (1 << 24)
  68
  69 struct PCIESPState {
  70     /*< private >*/
  71     PCIDevice parent_obj;
  72     /*< public >*/
  73
  74     MemoryRegion io;
  75     uint32_t dma_regs[8];
  76     uint32_t sbac;
  77     ESPState esp;
  78 };
  79
  80 static void esp_pci_update_irq(PCIESPState *pci)
  81 {
  82     int scsi_level = !!(pci->dma_regs[DMA_STAT] & DMA_STAT_SCSIINT);
  83     int dma_level = (pci->dma_regs[DMA_CMD] & DMA_CMD_INTE_D) ?
  84                     !!(pci->dma_regs[DMA_STAT] & DMA_STAT_DONE) : 0;
  85     int level = scsi_level || dma_level;
  86
  87     pci_set_irq(PCI_DEVICE(pci), level);
  88 }
  89
  90 static void esp_irq_handler(void *opaque, int irq_num, int level)
  91 {
  92     PCIESPState *pci = PCI_ESP(opaque);
  93
  94     if (level) {
  95         pci->dma_regs[DMA_STAT] |= DMA_STAT_SCSIINT;
  96
  97         /*
  98          * If raising the ESP IRQ to indicate end of DMA transfer, set
  99          * DMA_STAT_DONE at the same time. In theory this should be done in
 100          * esp_pci_dma_memory_rw(), however there is a delay between setting
 101          * DMA_STAT_DONE and the ESP IRQ arriving which is visible to the
 102          * guest that can cause confusion e.g. Linux
 103          */
 104         if ((pci->dma_regs[DMA_CMD] & DMA_CMD_MASK) == 0x3 &&
 105             pci->dma_regs[DMA_WBC] == 0) {
 106                 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
 107         }
 108     } else {
 109         pci->dma_regs[DMA_STAT] &= ~DMA_STAT_SCSIINT;
 110     }
 111
 112     esp_pci_update_irq(pci);
 113 }
 114
 115 static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
 116 {
 117     ESPState *s = &pci->esp;
 118
 119     trace_esp_pci_dma_idle(val);
 120     esp_dma_enable(s, 0, 0);
 121 }
 122
 123 static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
 124 {
 125     trace_esp_pci_dma_blast(val);
 126     qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
 127 }
 128
 129 static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
 130 {
 131     ESPState *s = &pci->esp;
 132
 133     trace_esp_pci_dma_abort(val);
 134     if (s->current_req) {
 135         scsi_req_cancel(s->current_req);
 136     }
 137 }
 138
 139 static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
 140 {
 141     ESPState *s = &pci->esp;
 142
 143     trace_esp_pci_dma_start(val);
 144
 145     pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
 146     pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
 147     pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
 148
 149     pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
 150                                | DMA_STAT_DONE | DMA_STAT_ABORT
 151                                | DMA_STAT_ERROR | DMA_STAT_PWDN);
 152
 153     esp_dma_enable(s, 0, 1);
 154 }
 155
 156 static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
 157 {
 158     trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
 159     switch (saddr) {
 160     case DMA_CMD:
 161         pci->dma_regs[saddr] = val;
 162         switch (val & DMA_CMD_MASK) {
 163         case 0x0: /* IDLE */
 164             esp_pci_handle_idle(pci, val);
 165             break;
 166         case 0x1: /* BLAST */
 167             esp_pci_handle_blast(pci, val);
 168             break;
 169         case 0x2: /* ABORT */
 170             esp_pci_handle_abort(pci, val);
 171             break;
 172         case 0x3: /* START */
 173             esp_pci_handle_start(pci, val);
 174             break;
 175         default: /* can't happen */
 176             abort();
 177         }
 178         break;
 179     case DMA_STC:
 180     case DMA_SPA:
 181     case DMA_SMDLA:
 182         pci->dma_regs[saddr] = val;
 183         break;
 184     case DMA_STAT:
 185         if (pci->sbac & SBAC_STATUS) {
 186             /* clear some bits on write */
 187             uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
 188             pci->dma_regs[DMA_STAT] &= ~(val & mask);
 189             esp_pci_update_irq(pci);
 190         }
 191         break;
 192     default:
 193         trace_esp_pci_error_invalid_write_dma(val, saddr);
 194         return;
 195     }
 196 }
 197
 198 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
 199 {
 200     uint32_t val;
 201
 202     val = pci->dma_regs[saddr];
 203     if (saddr == DMA_STAT) {
 204         if (!(pci->sbac & SBAC_STATUS)) {
 205             pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
 206                                          DMA_STAT_DONE);
 207             esp_pci_update_irq(pci);
 208         }
 209     }
 210
 211     trace_esp_pci_dma_read(saddr, val);
 212     return val;
 213 }
 214
 215 static void esp_pci_io_write(void *opaque, hwaddr addr,
 216                              uint64_t val, unsigned int size)
 217 {
 218     PCIESPState *pci = opaque;
 219     ESPState *s = &pci->esp;
 220
 221     if (size < 4 || addr & 3) {
 222         /* need to upgrade request: we only support 4-bytes accesses */
 223         uint32_t current = 0, mask;
 224         int shift;
 225
 226         if (addr < 0x40) {
 227             current = s->wregs[addr >> 2];
 228         } else if (addr < 0x60) {
 229             current = pci->dma_regs[(addr - 0x40) >> 2];
 230         } else if (addr < 0x74) {
 231             current = pci->sbac;
 232         }
 233
 234         shift = (4 - size) * 8;
 235         mask = (~(uint32_t)0 << shift) >> shift;
 236
 237         shift = ((4 - (addr & 3)) & 3) * 8;
 238         val <<= shift;
 239         val |= current & ~(mask << shift);
 240         addr &= ~3;
 241         size = 4;
 242     }
 243     g_assert(size >= 4);
 244
 245     if (addr < 0x40) {
 246         /* SCSI core reg */
 247         esp_reg_write(s, addr >> 2, val);
 248     } else if (addr < 0x60) {
 249         /* PCI DMA CCB */
 250         esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
 251     } else if (addr == 0x70) {
 252         /* DMA SCSI Bus and control */
 253         trace_esp_pci_sbac_write(pci->sbac, val);
 254         pci->sbac = val;
 255     } else {
 256         trace_esp_pci_error_invalid_write((int)addr);
 257     }
 258 }
 259
 260 static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
 261                                 unsigned int size)
 262 {
 263     PCIESPState *pci = opaque;
 264     ESPState *s = &pci->esp;
 265     uint32_t ret;
 266
 267     if (addr < 0x40) {
 268         /* SCSI core reg */
 269         ret = esp_reg_read(s, addr >> 2);
 270     } else if (addr < 0x60) {
 271         /* PCI DMA CCB */
 272         ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
 273     } else if (addr == 0x70) {
 274         /* DMA SCSI Bus and control */
 275         trace_esp_pci_sbac_read(pci->sbac);
 276         ret = pci->sbac;
 277     } else {
 278         /* Invalid region */
 279         trace_esp_pci_error_invalid_read((int)addr);
 280         ret = 0;
 281     }
 282
 283     /* give only requested data */
 284     ret >>= (addr & 3) * 8;
 285     ret &= ~(~(uint64_t)0 << (8 * size));
 286
 287     return ret;
 288 }
 289
 290 static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
 291                                   DMADirection dir)
 292 {
 293     dma_addr_t addr;
 294     DMADirection expected_dir;
 295
 296     if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
 297         expected_dir = DMA_DIRECTION_FROM_DEVICE;
 298     } else {
 299         expected_dir = DMA_DIRECTION_TO_DEVICE;
 300     }
 301
 302     if (dir != expected_dir) {
 303         trace_esp_pci_error_invalid_dma_direction();
 304         return;
 305     }
 306
 307     if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
 308         qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
 309     }
 310
 311     addr = pci->dma_regs[DMA_WAC];
 312     if (pci->dma_regs[DMA_WBC] < len) {
 313         len = pci->dma_regs[DMA_WBC];
 314     }
 315
 316     pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir, MEMTXATTRS_UNSPECIFIED);
 317
 318     /* update status registers */
 319     pci->dma_regs[DMA_WBC] -= len;
 320     pci->dma_regs[DMA_WAC] += len;
 321 }
 322
 323 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
 324 {
 325     PCIESPState *pci = opaque;
 326     esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
 327 }
 328
 329 static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len)
 330 {
 331     PCIESPState *pci = opaque;
 332     esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
 333 }
 334
 335 static const MemoryRegionOps esp_pci_io_ops = {
 336     .read = esp_pci_io_read,
 337     .write = esp_pci_io_write,
 338     .endianness = DEVICE_LITTLE_ENDIAN,
 339     .impl = {
 340         .min_access_size = 1,
 341         .max_access_size = 4,
 342     },
 343 };
 344
 345 static void esp_pci_hard_reset(DeviceState *dev)
 346 {
 347     PCIESPState *pci = PCI_ESP(dev);
 348     ESPState *s = &pci->esp;
 349
 350     esp_hard_reset(s);
 351     pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
 352                               | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
 353     pci->dma_regs[DMA_WBC] &= ~0xffff;
 354     pci->dma_regs[DMA_WAC] = 0xffffffff;
 355     pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
 356                                | DMA_STAT_DONE | DMA_STAT_ABORT
 357                                | DMA_STAT_ERROR);
 358     pci->dma_regs[DMA_WMAC] = 0xfffffffd;
 359 }
 360
 361 static const VMStateDescription vmstate_esp_pci_scsi = {
 362     .name = "pciespscsi",
 363     .version_id = 2,
 364     .minimum_version_id = 1,
 365     .pre_save = esp_pre_save,
 366     .fields = (const VMStateField[]) {
 367         VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
 368         VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
 369         VMSTATE_UINT8_V(esp.mig_version_id, PCIESPState, 2),
 370         VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
 371         VMSTATE_END_OF_LIST()
 372     }
 373 };
 374
 375 static const struct SCSIBusInfo esp_pci_scsi_info = {
 376     .tcq = false,
 377     .max_target = ESP_MAX_DEVS,
 378     .max_lun = 7,
 379
 380     .transfer_data = esp_transfer_data,
 381     .complete = esp_command_complete,
 382     .cancel = esp_request_cancelled,
 383 };
 384
 385 static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp)
 386 {
 387     PCIESPState *pci = PCI_ESP(dev);
 388     DeviceState *d = DEVICE(dev);
 389     ESPState *s = &pci->esp;
 390     uint8_t *pci_conf;
 391
 392     if (!qdev_realize(DEVICE(s), NULL, errp)) {
 393         return;
 394     }
 395
 396     pci_conf = dev->config;
 397
 398     /* Interrupt pin A */
 399     pci_conf[PCI_INTERRUPT_PIN] = 0x01;
 400
 401     s->dma_memory_read = esp_pci_dma_memory_read;
 402     s->dma_memory_write = esp_pci_dma_memory_write;
 403     s->dma_opaque = pci;
 404     s->chip_id = TCHI_AM53C974;
 405     memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
 406                           "esp-io", 0x80);
 407
 408     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
 409     s->irq = qemu_allocate_irq(esp_irq_handler, pci, 0);
 410
 411     scsi_bus_init(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info);
 412 }
 413
 414 static void esp_pci_scsi_exit(PCIDevice *d)
 415 {
 416     PCIESPState *pci = PCI_ESP(d);
 417     ESPState *s = &pci->esp;
 418
 419     qemu_free_irq(s->irq);
 420 }
 421
 422 static void esp_pci_init(Object *obj)
 423 {
 424     PCIESPState *pci = PCI_ESP(obj);
 425
 426     object_initialize_child(obj, "esp", &pci->esp, TYPE_ESP);
 427 }
 428
 429 static void esp_pci_class_init(ObjectClass *klass, void *data)
 430 {
 431     DeviceClass *dc = DEVICE_CLASS(klass);
 432     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 433
 434     k->realize = esp_pci_scsi_realize;
 435     k->exit = esp_pci_scsi_exit;
 436     k->vendor_id = PCI_VENDOR_ID_AMD;
 437     k->device_id = PCI_DEVICE_ID_AMD_SCSI;
 438     k->revision = 0x10;
 439     k->class_id = PCI_CLASS_STORAGE_SCSI;
 440     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 441     dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
 442     dc->reset = esp_pci_hard_reset;
 443     dc->vmsd = &vmstate_esp_pci_scsi;
 444 }
 445
 446 static const TypeInfo esp_pci_info = {
 447     .name = TYPE_AM53C974_DEVICE,
 448     .parent = TYPE_PCI_DEVICE,
 449     .instance_init = esp_pci_init,
 450     .instance_size = sizeof(PCIESPState),
 451     .class_init = esp_pci_class_init,
 452     .interfaces = (InterfaceInfo[]) {
 453         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 454         { },
 455     },
 456 };
 457
 458 struct DC390State {
 459     PCIESPState pci;
 460     eeprom_t *eeprom;
 461 };
 462 typedef struct DC390State DC390State;
 463
 464 #define TYPE_DC390_DEVICE "dc390"
 465 DECLARE_INSTANCE_CHECKER(DC390State, DC390,
 466                          TYPE_DC390_DEVICE)
 467
 468 #define EE_ADAPT_SCSI_ID 64
 469 #define EE_MODE2         65
 470 #define EE_DELAY         66
 471 #define EE_TAG_CMD_NUM   67
 472 #define EE_ADAPT_OPTIONS 68
 473 #define EE_BOOT_SCSI_ID  69
 474 #define EE_BOOT_SCSI_LUN 70
 475 #define EE_CHKSUM1       126
 476 #define EE_CHKSUM2       127
 477
 478 #define EE_ADAPT_OPTION_F6_F8_AT_BOOT   0x01
 479 #define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
 480 #define EE_ADAPT_OPTION_INT13           0x04
 481 #define EE_ADAPT_OPTION_SCAM_SUPPORT    0x08
 482
 483
 484 static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
 485 {
 486     DC390State *pci = DC390(dev);
 487     uint32_t val;
 488
 489     val = pci_default_read_config(dev, addr, l);
 490
 491     if (addr == 0x00 && l == 1) {
 492         /* First byte of address space is AND-ed with EEPROM DO line */
 493         if (!eeprom93xx_read(pci->eeprom)) {
 494             val &= ~0xff;
 495         }
 496     }
 497
 498     return val;
 499 }
 500
 501 static void dc390_write_config(PCIDevice *dev,
 502                                uint32_t addr, uint32_t val, int l)
 503 {
 504     DC390State *pci = DC390(dev);
 505     if (addr == 0x80) {
 506         /* EEPROM write */
 507         int eesk = val & 0x80 ? 1 : 0;
 508         int eedi = val & 0x40 ? 1 : 0;
 509         eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
 510     } else if (addr == 0xc0) {
 511         /* EEPROM CS low */
 512         eeprom93xx_write(pci->eeprom, 0, 0, 0);
 513     } else {
 514         pci_default_write_config(dev, addr, val, l);
 515     }
 516 }
 517
 518 static void dc390_scsi_realize(PCIDevice *dev, Error **errp)
 519 {
 520     DC390State *pci = DC390(dev);
 521     Error *err = NULL;
 522     uint8_t *contents;
 523     uint16_t chksum = 0;
 524     int i;
 525
 526     /* init base class */
 527     esp_pci_scsi_realize(dev, &err);
 528     if (err) {
 529         error_propagate(errp, err);
 530         return;
 531     }
 532
 533     /* EEPROM */
 534     pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);
 535
 536     /* set default eeprom values */
 537     contents = (uint8_t *)eeprom93xx_data(pci->eeprom);
 538
 539     for (i = 0; i < 16; i++) {
 540         contents[i * 2] = 0x57;
 541         contents[i * 2 + 1] = 0x00;
 542     }
 543     contents[EE_ADAPT_SCSI_ID] = 7;
 544     contents[EE_MODE2] = 0x0f;
 545     contents[EE_TAG_CMD_NUM] = 0x04;
 546     contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
 547                                | EE_ADAPT_OPTION_BOOT_FROM_CDROM
 548                                | EE_ADAPT_OPTION_INT13;
 549
 550     /* update eeprom checksum */
 551     for (i = 0; i < EE_CHKSUM1; i += 2) {
 552         chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
 553     }
 554     chksum = 0x1234 - chksum;
 555     contents[EE_CHKSUM1] = chksum & 0xff;
 556     contents[EE_CHKSUM2] = chksum >> 8;
 557 }
 558
 559 static void dc390_class_init(ObjectClass *klass, void *data)
 560 {
 561     DeviceClass *dc = DEVICE_CLASS(klass);
 562     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 563
 564     k->realize = dc390_scsi_realize;
 565     k->config_read = dc390_read_config;
 566     k->config_write = dc390_write_config;
 567     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 568     dc->desc = "Tekram DC-390 SCSI adapter";
 569 }
 570
 571 static const TypeInfo dc390_info = {
 572     .name = TYPE_DC390_DEVICE,
 573     .parent = TYPE_AM53C974_DEVICE,
 574     .instance_size = sizeof(DC390State),
 575     .class_init = dc390_class_init,
 576 };
 577
 578 static void esp_pci_register_types(void)
 579 {
 580     type_register_static(&esp_pci_info);
 581     type_register_static(&dc390_info);
 582 }
 583
 584 type_init(esp_pci_register_types)