hw/scsi/esp.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  * Copyright (c) 2012 Herve Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/sysbus.h"
  28 #include "hw/scsi/esp.h"
  29 #include "trace.h"
  30 #include "qapi/error.h"
  31 #include "qemu/log.h"
  32
  33 /*
  34  * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
  35  * also produced as NCR89C100. See
  36  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  37  * and
  38  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  39  */
  40
  41 static void esp_raise_irq(ESPState *s)
  42 {
  43     if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
  44         s->rregs[ESP_RSTAT] |= STAT_INT;
  45         qemu_irq_raise(s->irq);
  46         trace_esp_raise_irq();
  47     }
  48 }
  49
  50 static void esp_lower_irq(ESPState *s)
  51 {
  52     if (s->rregs[ESP_RSTAT] & STAT_INT) {
  53         s->rregs[ESP_RSTAT] &= ~STAT_INT;
  54         qemu_irq_lower(s->irq);
  55         trace_esp_lower_irq();
  56     }
  57 }
  58
  59 void esp_dma_enable(ESPState *s, int irq, int level)
  60 {
  61     if (level) {
  62         s->dma_enabled = 1;
  63         trace_esp_dma_enable();
  64         if (s->dma_cb) {
  65             s->dma_cb(s);
  66             s->dma_cb = NULL;
  67         }
  68     } else {
  69         trace_esp_dma_disable();
  70         s->dma_enabled = 0;
  71     }
  72 }
  73
  74 void esp_request_cancelled(SCSIRequest *req)
  75 {
  76     ESPState *s = req->hba_private;
  77
  78     if (req == s->current_req) {
  79         scsi_req_unref(s->current_req);
  80         s->current_req = NULL;
  81         s->current_dev = NULL;
  82     }
  83 }
  84
  85 static uint32_t get_cmd(ESPState *s, uint8_t *buf)
  86 {
  87     uint32_t dmalen;
  88     int target;
  89
  90     target = s->wregs[ESP_WBUSID] & BUSID_DID;
  91     if (s->dma) {
  92         dmalen = s->rregs[ESP_TCLO];
  93         dmalen |= s->rregs[ESP_TCMID] << 8;
  94         dmalen |= s->rregs[ESP_TCHI] << 16;
  95         s->dma_memory_read(s->dma_opaque, buf, dmalen);
  96     } else {
  97         dmalen = s->ti_size;
  98         memcpy(buf, s->ti_buf, dmalen);
  99         buf[0] = buf[2] >> 5;
 100     }
 101     trace_esp_get_cmd(dmalen, target);
 102
 103     s->ti_size = 0;
 104     s->ti_rptr = 0;
 105     s->ti_wptr = 0;
 106
 107     if (s->current_req) {
 108         /* Started a new command before the old one finished.  Cancel it.  */
 109         scsi_req_cancel(s->current_req);
 110         s->async_len = 0;
 111     }
 112
 113     s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
 114     if (!s->current_dev) {
 115         // No such drive
 116         s->rregs[ESP_RSTAT] = 0;
 117         s->rregs[ESP_RINTR] = INTR_DC;
 118         s->rregs[ESP_RSEQ] = SEQ_0;
 119         esp_raise_irq(s);
 120         return 0;
 121     }
 122     return dmalen;
 123 }
 124
 125 static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
 126 {
 127     int32_t datalen;
 128     int lun;
 129     SCSIDevice *current_lun;
 130
 131     trace_esp_do_busid_cmd(busid);
 132     lun = busid & 7;
 133     current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
 134     s->current_req = scsi_req_new(current_lun, 0, lun, buf, s);
 135     datalen = scsi_req_enqueue(s->current_req);
 136     s->ti_size = datalen;
 137     if (datalen != 0) {
 138         s->rregs[ESP_RSTAT] = STAT_TC;
 139         s->dma_left = 0;
 140         s->dma_counter = 0;
 141         if (datalen > 0) {
 142             s->rregs[ESP_RSTAT] |= STAT_DI;
 143         } else {
 144             s->rregs[ESP_RSTAT] |= STAT_DO;
 145         }
 146         scsi_req_continue(s->current_req);
 147     }
 148     s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 149     s->rregs[ESP_RSEQ] = SEQ_CD;
 150     esp_raise_irq(s);
 151 }
 152
 153 static void do_cmd(ESPState *s, uint8_t *buf)
 154 {
 155     uint8_t busid = buf[0];
 156
 157     do_busid_cmd(s, &buf[1], busid);
 158 }
 159
 160 static void handle_satn(ESPState *s)
 161 {
 162     uint8_t buf[32];
 163     int len;
 164
 165     if (s->dma && !s->dma_enabled) {
 166         s->dma_cb = handle_satn;
 167         return;
 168     }
 169     len = get_cmd(s, buf);
 170     if (len)
 171         do_cmd(s, buf);
 172 }
 173
 174 static void handle_s_without_atn(ESPState *s)
 175 {
 176     uint8_t buf[32];
 177     int len;
 178
 179     if (s->dma && !s->dma_enabled) {
 180         s->dma_cb = handle_s_without_atn;
 181         return;
 182     }
 183     len = get_cmd(s, buf);
 184     if (len) {
 185         do_busid_cmd(s, buf, 0);
 186     }
 187 }
 188
 189 static void handle_satn_stop(ESPState *s)
 190 {
 191     if (s->dma && !s->dma_enabled) {
 192         s->dma_cb = handle_satn_stop;
 193         return;
 194     }
 195     s->cmdlen = get_cmd(s, s->cmdbuf);
 196     if (s->cmdlen) {
 197         trace_esp_handle_satn_stop(s->cmdlen);
 198         s->do_cmd = 1;
 199         s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 200         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 201         s->rregs[ESP_RSEQ] = SEQ_CD;
 202         esp_raise_irq(s);
 203     }
 204 }
 205
 206 static void write_response(ESPState *s)
 207 {
 208     trace_esp_write_response(s->status);
 209     s->ti_buf[0] = s->status;
 210     s->ti_buf[1] = 0;
 211     if (s->dma) {
 212         s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
 213         s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
 214         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 215         s->rregs[ESP_RSEQ] = SEQ_CD;
 216     } else {
 217         s->ti_size = 2;
 218         s->ti_rptr = 0;
 219         s->ti_wptr = 0;
 220         s->rregs[ESP_RFLAGS] = 2;
 221     }
 222     esp_raise_irq(s);
 223 }
 224
 225 static void esp_dma_done(ESPState *s)
 226 {
 227     s->rregs[ESP_RSTAT] |= STAT_TC;
 228     s->rregs[ESP_RINTR] = INTR_BS;
 229     s->rregs[ESP_RSEQ] = 0;
 230     s->rregs[ESP_RFLAGS] = 0;
 231     s->rregs[ESP_TCLO] = 0;
 232     s->rregs[ESP_TCMID] = 0;
 233     s->rregs[ESP_TCHI] = 0;
 234     esp_raise_irq(s);
 235 }
 236
 237 static void esp_do_dma(ESPState *s)
 238 {
 239     uint32_t len;
 240     int to_device;
 241
 242     to_device = (s->ti_size < 0);
 243     len = s->dma_left;
 244     if (s->do_cmd) {
 245         trace_esp_do_dma(s->cmdlen, len);
 246         s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
 247         s->ti_size = 0;
 248         s->cmdlen = 0;
 249         s->do_cmd = 0;
 250         do_cmd(s, s->cmdbuf);
 251         return;
 252     }
 253     if (s->async_len == 0) {
 254         /* Defer until data is available.  */
 255         return;
 256     }
 257     if (len > s->async_len) {
 258         len = s->async_len;
 259     }
 260     if (to_device) {
 261         s->dma_memory_read(s->dma_opaque, s->async_buf, len);
 262     } else {
 263         s->dma_memory_write(s->dma_opaque, s->async_buf, len);
 264     }
 265     s->dma_left -= len;
 266     s->async_buf += len;
 267     s->async_len -= len;
 268     if (to_device)
 269         s->ti_size += len;
 270     else
 271         s->ti_size -= len;
 272     if (s->async_len == 0) {
 273         scsi_req_continue(s->current_req);
 274         /* If there is still data to be read from the device then
 275            complete the DMA operation immediately.  Otherwise defer
 276            until the scsi layer has completed.  */
 277         if (to_device || s->dma_left != 0 || s->ti_size == 0) {
 278             return;
 279         }
 280     }
 281
 282     /* Partially filled a scsi buffer. Complete immediately.  */
 283     esp_dma_done(s);
 284 }
 285
 286 void esp_command_complete(SCSIRequest *req, uint32_t status,
 287                                  size_t resid)
 288 {
 289     ESPState *s = req->hba_private;
 290
 291     trace_esp_command_complete();
 292     if (s->ti_size != 0) {
 293         trace_esp_command_complete_unexpected();
 294     }
 295     s->ti_size = 0;
 296     s->dma_left = 0;
 297     s->async_len = 0;
 298     if (status) {
 299         trace_esp_command_complete_fail();
 300     }
 301     s->status = status;
 302     s->rregs[ESP_RSTAT] = STAT_ST;
 303     esp_dma_done(s);
 304     if (s->current_req) {
 305         scsi_req_unref(s->current_req);
 306         s->current_req = NULL;
 307         s->current_dev = NULL;
 308     }
 309 }
 310
 311 void esp_transfer_data(SCSIRequest *req, uint32_t len)
 312 {
 313     ESPState *s = req->hba_private;
 314
 315     trace_esp_transfer_data(s->dma_left, s->ti_size);
 316     s->async_len = len;
 317     s->async_buf = scsi_req_get_buf(req);
 318     if (s->dma_left) {
 319         esp_do_dma(s);
 320     } else if (s->dma_counter != 0 && s->ti_size <= 0) {
 321         /* If this was the last part of a DMA transfer then the
 322            completion interrupt is deferred to here.  */
 323         esp_dma_done(s);
 324     }
 325 }
 326
 327 static void handle_ti(ESPState *s)
 328 {
 329     uint32_t dmalen, minlen;
 330
 331     if (s->dma && !s->dma_enabled) {
 332         s->dma_cb = handle_ti;
 333         return;
 334     }
 335
 336     dmalen = s->rregs[ESP_TCLO];
 337     dmalen |= s->rregs[ESP_TCMID] << 8;
 338     dmalen |= s->rregs[ESP_TCHI] << 16;
 339     if (dmalen==0) {
 340       dmalen=0x10000;
 341     }
 342     s->dma_counter = dmalen;
 343
 344     if (s->do_cmd)
 345         minlen = (dmalen < 32) ? dmalen : 32;
 346     else if (s->ti_size < 0)
 347         minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
 348     else
 349         minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
 350     trace_esp_handle_ti(minlen);
 351     if (s->dma) {
 352         s->dma_left = minlen;
 353         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 354         esp_do_dma(s);
 355     } else if (s->do_cmd) {
 356         trace_esp_handle_ti_cmd(s->cmdlen);
 357         s->ti_size = 0;
 358         s->cmdlen = 0;
 359         s->do_cmd = 0;
 360         do_cmd(s, s->cmdbuf);
 361         return;
 362     }
 363 }
 364
 365 void esp_hard_reset(ESPState *s)
 366 {
 367     memset(s->rregs, 0, ESP_REGS);
 368     memset(s->wregs, 0, ESP_REGS);
 369     s->tchi_written = 0;
 370     s->ti_size = 0;
 371     s->ti_rptr = 0;
 372     s->ti_wptr = 0;
 373     s->dma = 0;
 374     s->do_cmd = 0;
 375     s->dma_cb = NULL;
 376
 377     s->rregs[ESP_CFG1] = 7;
 378 }
 379
 380 static void esp_soft_reset(ESPState *s)
 381 {
 382     qemu_irq_lower(s->irq);
 383     esp_hard_reset(s);
 384 }
 385
 386 static void parent_esp_reset(ESPState *s, int irq, int level)
 387 {
 388     if (level) {
 389         esp_soft_reset(s);
 390     }
 391 }
 392
 393 uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
 394 {
 395     uint32_t old_val;
 396
 397     trace_esp_mem_readb(saddr, s->rregs[saddr]);
 398     switch (saddr) {
 399     case ESP_FIFO:
 400         if (s->ti_size > 0) {
 401             s->ti_size--;
 402             if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
 403                 /* Data out.  */
 404                 qemu_log_mask(LOG_UNIMP,
 405                               "esp: PIO data read not implemented\n");
 406                 s->rregs[ESP_FIFO] = 0;
 407             } else {
 408                 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
 409             }
 410             esp_raise_irq(s);
 411         }
 412         if (s->ti_size == 0) {
 413             s->ti_rptr = 0;
 414             s->ti_wptr = 0;
 415         }
 416         break;
 417     case ESP_RINTR:
 418         /* Clear sequence step, interrupt register and all status bits
 419            except TC */
 420         old_val = s->rregs[ESP_RINTR];
 421         s->rregs[ESP_RINTR] = 0;
 422         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 423         s->rregs[ESP_RSEQ] = SEQ_CD;
 424         esp_lower_irq(s);
 425
 426         return old_val;
 427     case ESP_TCHI:
 428         /* Return the unique id if the value has never been written */
 429         if (!s->tchi_written) {
 430             return s->chip_id;
 431         }
 432     default:
 433         break;
 434     }
 435     return s->rregs[saddr];
 436 }
 437
 438 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
 439 {
 440     trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
 441     switch (saddr) {
 442     case ESP_TCHI:
 443         s->tchi_written = true;
 444         /* fall through */
 445     case ESP_TCLO:
 446     case ESP_TCMID:
 447         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 448         break;
 449     case ESP_FIFO:
 450         if (s->do_cmd) {
 451             s->cmdbuf[s->cmdlen++] = val & 0xff;
 452         } else if (s->ti_size == TI_BUFSZ - 1) {
 453             trace_esp_error_fifo_overrun();
 454         } else {
 455             s->ti_size++;
 456             s->ti_buf[s->ti_wptr++] = val & 0xff;
 457         }
 458         break;
 459     case ESP_CMD:
 460         s->rregs[saddr] = val;
 461         if (val & CMD_DMA) {
 462             s->dma = 1;
 463             /* Reload DMA counter.  */
 464             s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
 465             s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
 466             s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI];
 467         } else {
 468             s->dma = 0;
 469         }
 470         switch(val & CMD_CMD) {
 471         case CMD_NOP:
 472             trace_esp_mem_writeb_cmd_nop(val);
 473             break;
 474         case CMD_FLUSH:
 475             trace_esp_mem_writeb_cmd_flush(val);
 476             //s->ti_size = 0;
 477             s->rregs[ESP_RINTR] = INTR_FC;
 478             s->rregs[ESP_RSEQ] = 0;
 479             s->rregs[ESP_RFLAGS] = 0;
 480             break;
 481         case CMD_RESET:
 482             trace_esp_mem_writeb_cmd_reset(val);
 483             esp_soft_reset(s);
 484             break;
 485         case CMD_BUSRESET:
 486             trace_esp_mem_writeb_cmd_bus_reset(val);
 487             s->rregs[ESP_RINTR] = INTR_RST;
 488             if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
 489                 esp_raise_irq(s);
 490             }
 491             break;
 492         case CMD_TI:
 493             handle_ti(s);
 494             break;
 495         case CMD_ICCS:
 496             trace_esp_mem_writeb_cmd_iccs(val);
 497             write_response(s);
 498             s->rregs[ESP_RINTR] = INTR_FC;
 499             s->rregs[ESP_RSTAT] |= STAT_MI;
 500             break;
 501         case CMD_MSGACC:
 502             trace_esp_mem_writeb_cmd_msgacc(val);
 503             s->rregs[ESP_RINTR] = INTR_DC;
 504             s->rregs[ESP_RSEQ] = 0;
 505             s->rregs[ESP_RFLAGS] = 0;
 506             esp_raise_irq(s);
 507             break;
 508         case CMD_PAD:
 509             trace_esp_mem_writeb_cmd_pad(val);
 510             s->rregs[ESP_RSTAT] = STAT_TC;
 511             s->rregs[ESP_RINTR] = INTR_FC;
 512             s->rregs[ESP_RSEQ] = 0;
 513             break;
 514         case CMD_SATN:
 515             trace_esp_mem_writeb_cmd_satn(val);
 516             break;
 517         case CMD_RSTATN:
 518             trace_esp_mem_writeb_cmd_rstatn(val);
 519             break;
 520         case CMD_SEL:
 521             trace_esp_mem_writeb_cmd_sel(val);
 522             handle_s_without_atn(s);
 523             break;
 524         case CMD_SELATN:
 525             trace_esp_mem_writeb_cmd_selatn(val);
 526             handle_satn(s);
 527             break;
 528         case CMD_SELATNS:
 529             trace_esp_mem_writeb_cmd_selatns(val);
 530             handle_satn_stop(s);
 531             break;
 532         case CMD_ENSEL:
 533             trace_esp_mem_writeb_cmd_ensel(val);
 534             s->rregs[ESP_RINTR] = 0;
 535             break;
 536         case CMD_DISSEL:
 537             trace_esp_mem_writeb_cmd_dissel(val);
 538             s->rregs[ESP_RINTR] = 0;
 539             esp_raise_irq(s);
 540             break;
 541         default:
 542             trace_esp_error_unhandled_command(val);
 543             break;
 544         }
 545         break;
 546     case ESP_WBUSID ... ESP_WSYNO:
 547         break;
 548     case ESP_CFG1:
 549     case ESP_CFG2: case ESP_CFG3:
 550     case ESP_RES3: case ESP_RES4:
 551         s->rregs[saddr] = val;
 552         break;
 553     case ESP_WCCF ... ESP_WTEST:
 554         break;
 555     default:
 556         trace_esp_error_invalid_write(val, saddr);
 557         return;
 558     }
 559     s->wregs[saddr] = val;
 560 }
 561
 562 static bool esp_mem_accepts(void *opaque, hwaddr addr,
 563                             unsigned size, bool is_write)
 564 {
 565     return (size == 1) || (is_write && size == 4);
 566 }
 567
 568 const VMStateDescription vmstate_esp = {
 569     .name ="esp",
 570     .version_id = 3,
 571     .minimum_version_id = 3,
 572     .fields = (VMStateField[]) {
 573         VMSTATE_BUFFER(rregs, ESPState),
 574         VMSTATE_BUFFER(wregs, ESPState),
 575         VMSTATE_INT32(ti_size, ESPState),
 576         VMSTATE_UINT32(ti_rptr, ESPState),
 577         VMSTATE_UINT32(ti_wptr, ESPState),
 578         VMSTATE_BUFFER(ti_buf, ESPState),
 579         VMSTATE_UINT32(status, ESPState),
 580         VMSTATE_UINT32(dma, ESPState),
 581         VMSTATE_BUFFER(cmdbuf, ESPState),
 582         VMSTATE_UINT32(cmdlen, ESPState),
 583         VMSTATE_UINT32(do_cmd, ESPState),
 584         VMSTATE_UINT32(dma_left, ESPState),
 585         VMSTATE_END_OF_LIST()
 586     }
 587 };
 588
 589 #define TYPE_ESP "esp"
 590 #define ESP(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP)
 591
 592 typedef struct {
 593     /*< private >*/
 594     SysBusDevice parent_obj;
 595     /*< public >*/
 596
 597     MemoryRegion iomem;
 598     uint32_t it_shift;
 599     ESPState esp;
 600 } SysBusESPState;
 601
 602 static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
 603                                  uint64_t val, unsigned int size)
 604 {
 605     SysBusESPState *sysbus = opaque;
 606     uint32_t saddr;
 607
 608     saddr = addr >> sysbus->it_shift;
 609     esp_reg_write(&sysbus->esp, saddr, val);
 610 }
 611
 612 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
 613                                     unsigned int size)
 614 {
 615     SysBusESPState *sysbus = opaque;
 616     uint32_t saddr;
 617
 618     saddr = addr >> sysbus->it_shift;
 619     return esp_reg_read(&sysbus->esp, saddr);
 620 }
 621
 622 static const MemoryRegionOps sysbus_esp_mem_ops = {
 623     .read = sysbus_esp_mem_read,
 624     .write = sysbus_esp_mem_write,
 625     .endianness = DEVICE_NATIVE_ENDIAN,
 626     .valid.accepts = esp_mem_accepts,
 627 };
 628
 629 void esp_init(hwaddr espaddr, int it_shift,
 630               ESPDMAMemoryReadWriteFunc dma_memory_read,
 631               ESPDMAMemoryReadWriteFunc dma_memory_write,
 632               void *dma_opaque, qemu_irq irq, qemu_irq *reset,
 633               qemu_irq *dma_enable)
 634 {
 635     DeviceState *dev;
 636     SysBusDevice *s;
 637     SysBusESPState *sysbus;
 638     ESPState *esp;
 639
 640     dev = qdev_create(NULL, TYPE_ESP);
 641     sysbus = ESP(dev);
 642     esp = &sysbus->esp;
 643     esp->dma_memory_read = dma_memory_read;
 644     esp->dma_memory_write = dma_memory_write;
 645     esp->dma_opaque = dma_opaque;
 646     sysbus->it_shift = it_shift;
 647     /* XXX for now until rc4030 has been changed to use DMA enable signal */
 648     esp->dma_enabled = 1;
 649     qdev_init_nofail(dev);
 650     s = SYS_BUS_DEVICE(dev);
 651     sysbus_connect_irq(s, 0, irq);
 652     sysbus_mmio_map(s, 0, espaddr);
 653     *reset = qdev_get_gpio_in(dev, 0);
 654     *dma_enable = qdev_get_gpio_in(dev, 1);
 655 }
 656
 657 static const struct SCSIBusInfo esp_scsi_info = {
 658     .tcq = false,
 659     .max_target = ESP_MAX_DEVS,
 660     .max_lun = 7,
 661
 662     .transfer_data = esp_transfer_data,
 663     .complete = esp_command_complete,
 664     .cancel = esp_request_cancelled
 665 };
 666
 667 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
 668 {
 669     SysBusESPState *sysbus = ESP(opaque);
 670     ESPState *s = &sysbus->esp;
 671
 672     switch (irq) {
 673     case 0:
 674         parent_esp_reset(s, irq, level);
 675         break;
 676     case 1:
 677         esp_dma_enable(opaque, irq, level);
 678         break;
 679     }
 680 }
 681
 682 static void sysbus_esp_realize(DeviceState *dev, Error **errp)
 683 {
 684     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 685     SysBusESPState *sysbus = ESP(dev);
 686     ESPState *s = &sysbus->esp;
 687     Error *err = NULL;
 688
 689     sysbus_init_irq(sbd, &s->irq);
 690     assert(sysbus->it_shift != -1);
 691
 692     s->chip_id = TCHI_FAS100A;
 693     memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
 694                           sysbus, "esp", ESP_REGS << sysbus->it_shift);
 695     sysbus_init_mmio(sbd, &sysbus->iomem);
 696
 697     qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
 698
 699     scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
 700     scsi_bus_legacy_handle_cmdline(&s->bus, &err);
 701     if (err != NULL) {
 702         error_propagate(errp, err);
 703         return;
 704     }
 705 }
 706
 707 static void sysbus_esp_hard_reset(DeviceState *dev)
 708 {
 709     SysBusESPState *sysbus = ESP(dev);
 710     esp_hard_reset(&sysbus->esp);
 711 }
 712
 713 static const VMStateDescription vmstate_sysbus_esp_scsi = {
 714     .name = "sysbusespscsi",
 715     .version_id = 0,
 716     .minimum_version_id = 0,
 717     .fields = (VMStateField[]) {
 718         VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState),
 719         VMSTATE_END_OF_LIST()
 720     }
 721 };
 722
 723 static void sysbus_esp_class_init(ObjectClass *klass, void *data)
 724 {
 725     DeviceClass *dc = DEVICE_CLASS(klass);
 726
 727     dc->realize = sysbus_esp_realize;
 728     dc->reset = sysbus_esp_hard_reset;
 729     dc->vmsd = &vmstate_sysbus_esp_scsi;
 730     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 731 }
 732
 733 static const TypeInfo sysbus_esp_info = {
 734     .name          = TYPE_ESP,
 735     .parent        = TYPE_SYS_BUS_DEVICE,
 736     .instance_size = sizeof(SysBusESPState),
 737     .class_init    = sysbus_esp_class_init,
 738 };
 739
 740 static void esp_register_types(void)
 741 {
 742     type_register_static(&sysbus_esp_info);
 743 }
 744
 745 type_init(esp_register_types)