hw/scsi/esp.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  * Copyright (c) 2012 Herve Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/sysbus.h"
  28 #include "migration/vmstate.h"
  29 #include "hw/irq.h"
  30 #include "hw/scsi/esp.h"
  31 #include "trace.h"
  32 #include "qemu/log.h"
  33 #include "qemu/module.h"
  34
  35 /*
  36  * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
  37  * also produced as NCR89C100. See
  38  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  39  * and
  40  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  41  *
  42  * On Macintosh Quadra it is a NCR53C96.
  43  */
  44
  45 static void esp_raise_irq(ESPState *s)
  46 {
  47     if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
  48         s->rregs[ESP_RSTAT] |= STAT_INT;
  49         qemu_irq_raise(s->irq);
  50         trace_esp_raise_irq();
  51     }
  52 }
  53
  54 static void esp_lower_irq(ESPState *s)
  55 {
  56     if (s->rregs[ESP_RSTAT] & STAT_INT) {
  57         s->rregs[ESP_RSTAT] &= ~STAT_INT;
  58         qemu_irq_lower(s->irq);
  59         trace_esp_lower_irq();
  60     }
  61 }
  62
  63 static void esp_raise_drq(ESPState *s)
  64 {
  65     qemu_irq_raise(s->irq_data);
  66     trace_esp_raise_drq();
  67 }
  68
  69 static void esp_lower_drq(ESPState *s)
  70 {
  71     qemu_irq_lower(s->irq_data);
  72     trace_esp_lower_drq();
  73 }
  74
  75 void esp_dma_enable(ESPState *s, int irq, int level)
  76 {
  77     if (level) {
  78         s->dma_enabled = 1;
  79         trace_esp_dma_enable();
  80         if (s->dma_cb) {
  81             s->dma_cb(s);
  82             s->dma_cb = NULL;
  83         }
  84     } else {
  85         trace_esp_dma_disable();
  86         s->dma_enabled = 0;
  87     }
  88 }
  89
  90 void esp_request_cancelled(SCSIRequest *req)
  91 {
  92     ESPState *s = req->hba_private;
  93
  94     if (req == s->current_req) {
  95         scsi_req_unref(s->current_req);
  96         s->current_req = NULL;
  97         s->current_dev = NULL;
  98     }
  99 }
 100
 101 static void esp_fifo_push(Fifo8 *fifo, uint8_t val)
 102 {
 103     if (fifo8_num_used(fifo) == fifo->capacity) {
 104         trace_esp_error_fifo_overrun();
 105         return;
 106     }
 107
 108     fifo8_push(fifo, val);
 109 }
 110
 111 static uint8_t esp_fifo_pop(Fifo8 *fifo)
 112 {
 113     if (fifo8_is_empty(fifo)) {
 114         return 0;
 115     }
 116
 117     return fifo8_pop(fifo);
 118 }
 119
 120 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen)
 121 {
 122     const uint8_t *buf;
 123     uint32_t n;
 124
 125     if (maxlen == 0) {
 126         return 0;
 127     }
 128
 129     buf = fifo8_pop_buf(fifo, maxlen, &n);
 130     if (dest) {
 131         memcpy(dest, buf, n);
 132     }
 133
 134     return n;
 135 }
 136
 137 static uint32_t esp_get_tc(ESPState *s)
 138 {
 139     uint32_t dmalen;
 140
 141     dmalen = s->rregs[ESP_TCLO];
 142     dmalen |= s->rregs[ESP_TCMID] << 8;
 143     dmalen |= s->rregs[ESP_TCHI] << 16;
 144
 145     return dmalen;
 146 }
 147
 148 static void esp_set_tc(ESPState *s, uint32_t dmalen)
 149 {
 150     s->rregs[ESP_TCLO] = dmalen;
 151     s->rregs[ESP_TCMID] = dmalen >> 8;
 152     s->rregs[ESP_TCHI] = dmalen >> 16;
 153 }
 154
 155 static uint32_t esp_get_stc(ESPState *s)
 156 {
 157     uint32_t dmalen;
 158
 159     dmalen = s->wregs[ESP_TCLO];
 160     dmalen |= s->wregs[ESP_TCMID] << 8;
 161     dmalen |= s->wregs[ESP_TCHI] << 16;
 162
 163     return dmalen;
 164 }
 165
 166 static uint8_t esp_pdma_read(ESPState *s)
 167 {
 168     uint8_t val;
 169
 170     if (s->do_cmd) {
 171         val = esp_fifo_pop(&s->cmdfifo);
 172     } else {
 173         val = esp_fifo_pop(&s->fifo);
 174     }
 175
 176     return val;
 177 }
 178
 179 static void esp_pdma_write(ESPState *s, uint8_t val)
 180 {
 181     uint32_t dmalen = esp_get_tc(s);
 182
 183     if (dmalen == 0) {
 184         return;
 185     }
 186
 187     if (s->do_cmd) {
 188         esp_fifo_push(&s->cmdfifo, val);
 189     } else {
 190         esp_fifo_push(&s->fifo, val);
 191     }
 192
 193     dmalen--;
 194     esp_set_tc(s, dmalen);
 195 }
 196
 197 static int esp_select(ESPState *s)
 198 {
 199     int target;
 200
 201     target = s->wregs[ESP_WBUSID] & BUSID_DID;
 202
 203     s->ti_size = 0;
 204     fifo8_reset(&s->fifo);
 205
 206     if (s->current_req) {
 207         /* Started a new command before the old one finished.  Cancel it.  */
 208         scsi_req_cancel(s->current_req);
 209         s->async_len = 0;
 210     }
 211
 212     s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
 213     if (!s->current_dev) {
 214         /* No such drive */
 215         s->rregs[ESP_RSTAT] = 0;
 216         s->rregs[ESP_RINTR] |= INTR_DC;
 217         s->rregs[ESP_RSEQ] = SEQ_0;
 218         esp_raise_irq(s);
 219         return -1;
 220     }
 221
 222     /*
 223      * Note that we deliberately don't raise the IRQ here: this will be done
 224      * either in do_busid_cmd() for DATA OUT transfers or by the deferred
 225      * IRQ mechanism in esp_transfer_data() for DATA IN transfers
 226      */
 227     s->rregs[ESP_RINTR] |= INTR_FC;
 228     s->rregs[ESP_RSEQ] = SEQ_CD;
 229     return 0;
 230 }
 231
 232 static uint32_t get_cmd(ESPState *s, uint32_t maxlen)
 233 {
 234     uint8_t buf[ESP_CMDFIFO_SZ];
 235     uint32_t dmalen, n;
 236     int target;
 237
 238     target = s->wregs[ESP_WBUSID] & BUSID_DID;
 239     if (s->dma) {
 240         dmalen = MIN(esp_get_tc(s), maxlen);
 241         if (dmalen == 0) {
 242             return 0;
 243         }
 244         if (s->dma_memory_read) {
 245             s->dma_memory_read(s->dma_opaque, buf, dmalen);
 246             dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen);
 247             fifo8_push_all(&s->cmdfifo, buf, dmalen);
 248         } else {
 249             if (esp_select(s) < 0) {
 250                 fifo8_reset(&s->cmdfifo);
 251                 return -1;
 252             }
 253             esp_raise_drq(s);
 254             fifo8_reset(&s->cmdfifo);
 255             return 0;
 256         }
 257     } else {
 258         dmalen = MIN(fifo8_num_used(&s->fifo), maxlen);
 259         if (dmalen == 0) {
 260             return 0;
 261         }
 262         n = esp_fifo_pop_buf(&s->fifo, buf, dmalen);
 263         if (n >= 3) {
 264             buf[0] = buf[2] >> 5;
 265         }
 266         n = MIN(fifo8_num_free(&s->cmdfifo), n);
 267         fifo8_push_all(&s->cmdfifo, buf, n);
 268     }
 269     trace_esp_get_cmd(dmalen, target);
 270
 271     if (esp_select(s) < 0) {
 272         fifo8_reset(&s->cmdfifo);
 273         return -1;
 274     }
 275     return dmalen;
 276 }
 277
 278 static void do_busid_cmd(ESPState *s, uint8_t busid)
 279 {
 280     uint32_t cmdlen;
 281     int32_t datalen;
 282     int lun;
 283     SCSIDevice *current_lun;
 284     uint8_t buf[ESP_CMDFIFO_SZ];
 285
 286     trace_esp_do_busid_cmd(busid);
 287     lun = busid & 7;
 288     cmdlen = fifo8_num_used(&s->cmdfifo);
 289     if (!cmdlen || !s->current_dev) {
 290         return;
 291     }
 292     esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen);
 293
 294     current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
 295     s->current_req = scsi_req_new(current_lun, 0, lun, buf, s);
 296     datalen = scsi_req_enqueue(s->current_req);
 297     s->ti_size = datalen;
 298     fifo8_reset(&s->cmdfifo);
 299     if (datalen != 0) {
 300         s->rregs[ESP_RSTAT] = STAT_TC;
 301         s->rregs[ESP_RSEQ] = SEQ_CD;
 302         s->ti_cmd = 0;
 303         esp_set_tc(s, 0);
 304         if (datalen > 0) {
 305             /*
 306              * Switch to DATA IN phase but wait until initial data xfer is
 307              * complete before raising the command completion interrupt
 308              */
 309             s->data_in_ready = false;
 310             s->rregs[ESP_RSTAT] |= STAT_DI;
 311         } else {
 312             s->rregs[ESP_RSTAT] |= STAT_DO;
 313             s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
 314             esp_raise_irq(s);
 315             esp_lower_drq(s);
 316         }
 317         scsi_req_continue(s->current_req);
 318         return;
 319     }
 320 }
 321
 322 static void do_cmd(ESPState *s)
 323 {
 324     uint8_t busid = esp_fifo_pop(&s->cmdfifo);
 325     int len;
 326
 327     s->cmdfifo_cdb_offset--;
 328
 329     /* Ignore extended messages for now */
 330     if (s->cmdfifo_cdb_offset) {
 331         len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo));
 332         esp_fifo_pop_buf(&s->cmdfifo, NULL, len);
 333         s->cmdfifo_cdb_offset = 0;
 334     }
 335
 336     do_busid_cmd(s, busid);
 337 }
 338
 339 static void satn_pdma_cb(ESPState *s)
 340 {
 341     s->do_cmd = 0;
 342     if (!fifo8_is_empty(&s->cmdfifo)) {
 343         s->cmdfifo_cdb_offset = 1;
 344         do_cmd(s);
 345     }
 346 }
 347
 348 static void handle_satn(ESPState *s)
 349 {
 350     int32_t cmdlen;
 351
 352     if (s->dma && !s->dma_enabled) {
 353         s->dma_cb = handle_satn;
 354         return;
 355     }
 356     s->pdma_cb = satn_pdma_cb;
 357     cmdlen = get_cmd(s, ESP_CMDFIFO_SZ);
 358     if (cmdlen > 0) {
 359         s->cmdfifo_cdb_offset = 1;
 360         do_cmd(s);
 361     } else if (cmdlen == 0) {
 362         s->do_cmd = 1;
 363         /* Target present, but no cmd yet - switch to command phase */
 364         s->rregs[ESP_RSEQ] = SEQ_CD;
 365         s->rregs[ESP_RSTAT] = STAT_CD;
 366     }
 367 }
 368
 369 static void s_without_satn_pdma_cb(ESPState *s)
 370 {
 371     uint32_t len;
 372
 373     s->do_cmd = 0;
 374     len = fifo8_num_used(&s->cmdfifo);
 375     if (len) {
 376         s->cmdfifo_cdb_offset = 0;
 377         do_busid_cmd(s, 0);
 378     }
 379 }
 380
 381 static void handle_s_without_atn(ESPState *s)
 382 {
 383     int32_t cmdlen;
 384
 385     if (s->dma && !s->dma_enabled) {
 386         s->dma_cb = handle_s_without_atn;
 387         return;
 388     }
 389     s->pdma_cb = s_without_satn_pdma_cb;
 390     cmdlen = get_cmd(s, ESP_CMDFIFO_SZ);
 391     if (cmdlen > 0) {
 392         s->cmdfifo_cdb_offset = 0;
 393         do_busid_cmd(s, 0);
 394     } else if (cmdlen == 0) {
 395         s->do_cmd = 1;
 396         /* Target present, but no cmd yet - switch to command phase */
 397         s->rregs[ESP_RSEQ] = SEQ_CD;
 398         s->rregs[ESP_RSTAT] = STAT_CD;
 399     }
 400 }
 401
 402 static void satn_stop_pdma_cb(ESPState *s)
 403 {
 404     s->do_cmd = 0;
 405     if (!fifo8_is_empty(&s->cmdfifo)) {
 406         trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo));
 407         s->do_cmd = 1;
 408         s->cmdfifo_cdb_offset = 1;
 409         s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 410         s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
 411         s->rregs[ESP_RSEQ] = SEQ_CD;
 412         esp_raise_irq(s);
 413     }
 414 }
 415
 416 static void handle_satn_stop(ESPState *s)
 417 {
 418     int32_t cmdlen;
 419
 420     if (s->dma && !s->dma_enabled) {
 421         s->dma_cb = handle_satn_stop;
 422         return;
 423     }
 424     s->pdma_cb = satn_stop_pdma_cb;
 425     cmdlen = get_cmd(s, 1);
 426     if (cmdlen > 0) {
 427         trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo));
 428         s->do_cmd = 1;
 429         s->cmdfifo_cdb_offset = 1;
 430         s->rregs[ESP_RSTAT] = STAT_MO;
 431         s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
 432         s->rregs[ESP_RSEQ] = SEQ_MO;
 433         esp_raise_irq(s);
 434     } else if (cmdlen == 0) {
 435         s->do_cmd = 1;
 436         /* Target present, switch to message out phase */
 437         s->rregs[ESP_RSEQ] = SEQ_MO;
 438         s->rregs[ESP_RSTAT] = STAT_MO;
 439     }
 440 }
 441
 442 static void write_response_pdma_cb(ESPState *s)
 443 {
 444     s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
 445     s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
 446     s->rregs[ESP_RSEQ] = SEQ_CD;
 447     esp_raise_irq(s);
 448 }
 449
 450 static void write_response(ESPState *s)
 451 {
 452     uint8_t buf[2];
 453
 454     trace_esp_write_response(s->status);
 455
 456     buf[0] = s->status;
 457     buf[1] = 0;
 458
 459     if (s->dma) {
 460         if (s->dma_memory_write) {
 461             s->dma_memory_write(s->dma_opaque, buf, 2);
 462             s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
 463             s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC;
 464             s->rregs[ESP_RSEQ] = SEQ_CD;
 465         } else {
 466             s->pdma_cb = write_response_pdma_cb;
 467             esp_raise_drq(s);
 468             return;
 469         }
 470     } else {
 471         fifo8_reset(&s->fifo);
 472         fifo8_push_all(&s->fifo, buf, 2);
 473         s->rregs[ESP_RFLAGS] = 2;
 474     }
 475     esp_raise_irq(s);
 476 }
 477
 478 static void esp_dma_done(ESPState *s)
 479 {
 480     s->rregs[ESP_RSTAT] |= STAT_TC;
 481     s->rregs[ESP_RINTR] |= INTR_BS;
 482     s->rregs[ESP_RSEQ] = 0;
 483     s->rregs[ESP_RFLAGS] = 0;
 484     esp_set_tc(s, 0);
 485     esp_raise_irq(s);
 486 }
 487
 488 static void do_dma_pdma_cb(ESPState *s)
 489 {
 490     int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO);
 491     int len;
 492     uint32_t n;
 493
 494     if (s->do_cmd) {
 495         s->ti_size = 0;
 496         s->do_cmd = 0;
 497         do_cmd(s);
 498         esp_lower_drq(s);
 499         return;
 500     }
 501
 502     if (!s->current_req) {
 503         return;
 504     }
 505
 506     if (to_device) {
 507         /* Copy FIFO data to device */
 508         len = MIN(s->async_len, ESP_FIFO_SZ);
 509         len = MIN(len, fifo8_num_used(&s->fifo));
 510         n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len);
 511         s->async_buf += n;
 512         s->async_len -= n;
 513         s->ti_size += n;
 514
 515         if (n < len) {
 516             /* Unaligned accesses can cause FIFO wraparound */
 517             len = len - n;
 518             n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len);
 519             s->async_buf += n;
 520             s->async_len -= n;
 521             s->ti_size += n;
 522         }
 523
 524         if (s->async_len == 0) {
 525             scsi_req_continue(s->current_req);
 526             return;
 527         }
 528
 529         if (esp_get_tc(s) == 0) {
 530             esp_lower_drq(s);
 531             esp_dma_done(s);
 532         }
 533
 534         return;
 535     } else {
 536         if (s->async_len == 0) {
 537             /* Defer until the scsi layer has completed */
 538             scsi_req_continue(s->current_req);
 539             s->data_in_ready = false;
 540             return;
 541         }
 542
 543         if (esp_get_tc(s) != 0) {
 544             /* Copy device data to FIFO */
 545             len = MIN(s->async_len, esp_get_tc(s));
 546             len = MIN(len, fifo8_num_free(&s->fifo));
 547             fifo8_push_all(&s->fifo, s->async_buf, len);
 548             s->async_buf += len;
 549             s->async_len -= len;
 550             s->ti_size -= len;
 551             esp_set_tc(s, esp_get_tc(s) - len);
 552
 553             if (esp_get_tc(s) == 0) {
 554                 /* Indicate transfer to FIFO is complete */
 555                  s->rregs[ESP_RSTAT] |= STAT_TC;
 556             }
 557             return;
 558         }
 559
 560         /* Partially filled a scsi buffer. Complete immediately.  */
 561         esp_lower_drq(s);
 562         esp_dma_done(s);
 563     }
 564 }
 565
 566 static void esp_do_dma(ESPState *s)
 567 {
 568     uint32_t len, cmdlen;
 569     int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO);
 570     uint8_t buf[ESP_CMDFIFO_SZ];
 571
 572     len = esp_get_tc(s);
 573     if (s->do_cmd) {
 574         /*
 575          * handle_ti_cmd() case: esp_do_dma() is called only from
 576          * handle_ti_cmd() with do_cmd != NULL (see the assert())
 577          */
 578         cmdlen = fifo8_num_used(&s->cmdfifo);
 579         trace_esp_do_dma(cmdlen, len);
 580         if (s->dma_memory_read) {
 581             len = MIN(len, fifo8_num_free(&s->cmdfifo));
 582             s->dma_memory_read(s->dma_opaque, buf, len);
 583             fifo8_push_all(&s->cmdfifo, buf, len);
 584         } else {
 585             s->pdma_cb = do_dma_pdma_cb;
 586             esp_raise_drq(s);
 587             return;
 588         }
 589         trace_esp_handle_ti_cmd(cmdlen);
 590         s->ti_size = 0;
 591         if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) {
 592             /* No command received */
 593             if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) {
 594                 return;
 595             }
 596
 597             /* Command has been received */
 598             s->do_cmd = 0;
 599             do_cmd(s);
 600         } else {
 601             /*
 602              * Extra message out bytes received: update cmdfifo_cdb_offset
 603              * and then switch to commmand phase
 604              */
 605             s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo);
 606             s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 607             s->rregs[ESP_RSEQ] = SEQ_CD;
 608             s->rregs[ESP_RINTR] |= INTR_BS;
 609             esp_raise_irq(s);
 610         }
 611         return;
 612     }
 613     if (!s->current_req) {
 614         return;
 615     }
 616     if (s->async_len == 0) {
 617         /* Defer until data is available.  */
 618         return;
 619     }
 620     if (len > s->async_len) {
 621         len = s->async_len;
 622     }
 623     if (to_device) {
 624         if (s->dma_memory_read) {
 625             s->dma_memory_read(s->dma_opaque, s->async_buf, len);
 626         } else {
 627             s->pdma_cb = do_dma_pdma_cb;
 628             esp_raise_drq(s);
 629             return;
 630         }
 631     } else {
 632         if (s->dma_memory_write) {
 633             s->dma_memory_write(s->dma_opaque, s->async_buf, len);
 634         } else {
 635             /* Adjust TC for any leftover data in the FIFO */
 636             if (!fifo8_is_empty(&s->fifo)) {
 637                 esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo));
 638             }
 639
 640             /* Copy device data to FIFO */
 641             len = MIN(len, fifo8_num_free(&s->fifo));
 642             fifo8_push_all(&s->fifo, s->async_buf, len);
 643             s->async_buf += len;
 644             s->async_len -= len;
 645             s->ti_size -= len;
 646
 647             /*
 648              * MacOS toolbox uses a TI length of 16 bytes for all commands, so
 649              * commands shorter than this must be padded accordingly
 650              */
 651             if (len < esp_get_tc(s) && esp_get_tc(s) <= ESP_FIFO_SZ) {
 652                 while (fifo8_num_used(&s->fifo) < ESP_FIFO_SZ) {
 653                     esp_fifo_push(&s->fifo, 0);
 654                     len++;
 655                 }
 656             }
 657
 658             esp_set_tc(s, esp_get_tc(s) - len);
 659             s->pdma_cb = do_dma_pdma_cb;
 660             esp_raise_drq(s);
 661
 662             /* Indicate transfer to FIFO is complete */
 663             s->rregs[ESP_RSTAT] |= STAT_TC;
 664             return;
 665         }
 666     }
 667     esp_set_tc(s, esp_get_tc(s) - len);
 668     s->async_buf += len;
 669     s->async_len -= len;
 670     if (to_device) {
 671         s->ti_size += len;
 672     } else {
 673         s->ti_size -= len;
 674     }
 675     if (s->async_len == 0) {
 676         scsi_req_continue(s->current_req);
 677         /*
 678          * If there is still data to be read from the device then
 679          * complete the DMA operation immediately.  Otherwise defer
 680          * until the scsi layer has completed.
 681          */
 682         if (to_device || esp_get_tc(s) != 0 || s->ti_size == 0) {
 683             return;
 684         }
 685     }
 686
 687     /* Partially filled a scsi buffer. Complete immediately.  */
 688     esp_dma_done(s);
 689     esp_lower_drq(s);
 690 }
 691
 692 static void esp_do_nodma(ESPState *s)
 693 {
 694     int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO);
 695     uint32_t cmdlen;
 696     int len;
 697
 698     if (s->do_cmd) {
 699         cmdlen = fifo8_num_used(&s->cmdfifo);
 700         trace_esp_handle_ti_cmd(cmdlen);
 701         s->ti_size = 0;
 702         if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) {
 703             /* No command received */
 704             if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) {
 705                 return;
 706             }
 707
 708             /* Command has been received */
 709             s->do_cmd = 0;
 710             do_cmd(s);
 711         } else {
 712             /*
 713              * Extra message out bytes received: update cmdfifo_cdb_offset
 714              * and then switch to commmand phase
 715              */
 716             s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo);
 717             s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 718             s->rregs[ESP_RSEQ] = SEQ_CD;
 719             s->rregs[ESP_RINTR] |= INTR_BS;
 720             esp_raise_irq(s);
 721         }
 722         return;
 723     }
 724
 725     if (!s->current_req) {
 726         return;
 727     }
 728
 729     if (s->async_len == 0) {
 730         /* Defer until data is available.  */
 731         return;
 732     }
 733
 734     if (to_device) {
 735         len = MIN(fifo8_num_used(&s->fifo), ESP_FIFO_SZ);
 736         esp_fifo_pop_buf(&s->fifo, s->async_buf, len);
 737         s->async_buf += len;
 738         s->async_len -= len;
 739         s->ti_size += len;
 740     } else {
 741         len = MIN(s->ti_size, s->async_len);
 742         len = MIN(len, fifo8_num_free(&s->fifo));
 743         fifo8_push_all(&s->fifo, s->async_buf, len);
 744         s->async_buf += len;
 745         s->async_len -= len;
 746         s->ti_size -= len;
 747     }
 748
 749     if (s->async_len == 0) {
 750         scsi_req_continue(s->current_req);
 751
 752         if (to_device || s->ti_size == 0) {
 753             return;
 754         }
 755     }
 756
 757     s->rregs[ESP_RINTR] |= INTR_BS;
 758     esp_raise_irq(s);
 759 }
 760
 761 void esp_command_complete(SCSIRequest *req, size_t resid)
 762 {
 763     ESPState *s = req->hba_private;
 764
 765     trace_esp_command_complete();
 766     if (s->ti_size != 0) {
 767         trace_esp_command_complete_unexpected();
 768     }
 769     s->ti_size = 0;
 770     s->async_len = 0;
 771     if (req->status) {
 772         trace_esp_command_complete_fail();
 773     }
 774     s->status = req->status;
 775     s->rregs[ESP_RSTAT] = STAT_ST;
 776     esp_dma_done(s);
 777     esp_lower_drq(s);
 778     if (s->current_req) {
 779         scsi_req_unref(s->current_req);
 780         s->current_req = NULL;
 781         s->current_dev = NULL;
 782     }
 783 }
 784
 785 void esp_transfer_data(SCSIRequest *req, uint32_t len)
 786 {
 787     ESPState *s = req->hba_private;
 788     int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO);
 789     uint32_t dmalen = esp_get_tc(s);
 790
 791     assert(!s->do_cmd);
 792     trace_esp_transfer_data(dmalen, s->ti_size);
 793     s->async_len = len;
 794     s->async_buf = scsi_req_get_buf(req);
 795
 796     if (!to_device && !s->data_in_ready) {
 797         /*
 798          * Initial incoming data xfer is complete so raise command
 799          * completion interrupt
 800          */
 801         s->data_in_ready = true;
 802         s->rregs[ESP_RSTAT] |= STAT_TC;
 803         s->rregs[ESP_RINTR] |= INTR_BS;
 804         esp_raise_irq(s);
 805
 806         /*
 807          * If data is ready to transfer and the TI command has already
 808          * been executed, start DMA immediately. Otherwise DMA will start
 809          * when host sends the TI command
 810          */
 811         if (s->ti_size && (s->rregs[ESP_CMD] == (CMD_TI | CMD_DMA))) {
 812             esp_do_dma(s);
 813         }
 814         return;
 815     }
 816
 817     if (s->ti_cmd == 0) {
 818         /*
 819          * Always perform the initial transfer upon reception of the next TI
 820          * command to ensure the DMA/non-DMA status of the command is correct.
 821          * It is not possible to use s->dma directly in the section below as
 822          * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the
 823          * async data transfer is delayed then s->dma is set incorrectly.
 824          */
 825         return;
 826     }
 827
 828     if (s->ti_cmd & CMD_DMA) {
 829         if (dmalen) {
 830             esp_do_dma(s);
 831         } else if (s->ti_size <= 0) {
 832             /*
 833              * If this was the last part of a DMA transfer then the
 834              * completion interrupt is deferred to here.
 835              */
 836             esp_dma_done(s);
 837             esp_lower_drq(s);
 838         }
 839     } else {
 840         esp_do_nodma(s);
 841     }
 842 }
 843
 844 static void handle_ti(ESPState *s)
 845 {
 846     uint32_t dmalen;
 847
 848     if (s->dma && !s->dma_enabled) {
 849         s->dma_cb = handle_ti;
 850         return;
 851     }
 852
 853     s->ti_cmd = s->rregs[ESP_CMD];
 854     if (s->dma) {
 855         dmalen = esp_get_tc(s);
 856         trace_esp_handle_ti(dmalen);
 857         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 858         esp_do_dma(s);
 859     } else {
 860         trace_esp_handle_ti(s->ti_size);
 861         esp_do_nodma(s);
 862     }
 863 }
 864
 865 void esp_hard_reset(ESPState *s)
 866 {
 867     memset(s->rregs, 0, ESP_REGS);
 868     memset(s->wregs, 0, ESP_REGS);
 869     s->tchi_written = 0;
 870     s->ti_size = 0;
 871     fifo8_reset(&s->fifo);
 872     fifo8_reset(&s->cmdfifo);
 873     s->dma = 0;
 874     s->do_cmd = 0;
 875     s->dma_cb = NULL;
 876
 877     s->rregs[ESP_CFG1] = 7;
 878 }
 879
 880 static void esp_soft_reset(ESPState *s)
 881 {
 882     qemu_irq_lower(s->irq);
 883     qemu_irq_lower(s->irq_data);
 884     esp_hard_reset(s);
 885 }
 886
 887 static void parent_esp_reset(ESPState *s, int irq, int level)
 888 {
 889     if (level) {
 890         esp_soft_reset(s);
 891     }
 892 }
 893
 894 uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
 895 {
 896     uint32_t val;
 897
 898     switch (saddr) {
 899     case ESP_FIFO:
 900         if (s->dma_memory_read && s->dma_memory_write &&
 901                 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
 902             /* Data out.  */
 903             qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n");
 904             s->rregs[ESP_FIFO] = 0;
 905         } else {
 906             s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo);
 907         }
 908         val = s->rregs[ESP_FIFO];
 909         break;
 910     case ESP_RINTR:
 911         /*
 912          * Clear sequence step, interrupt register and all status bits
 913          * except TC
 914          */
 915         val = s->rregs[ESP_RINTR];
 916         s->rregs[ESP_RINTR] = 0;
 917         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 918         s->rregs[ESP_RSEQ] = SEQ_0;
 919         esp_lower_irq(s);
 920         break;
 921     case ESP_TCHI:
 922         /* Return the unique id if the value has never been written */
 923         if (!s->tchi_written) {
 924             val = s->chip_id;
 925         } else {
 926             val = s->rregs[saddr];
 927         }
 928         break;
 929      case ESP_RFLAGS:
 930         /* Bottom 5 bits indicate number of bytes in FIFO */
 931         val = fifo8_num_used(&s->fifo);
 932         break;
 933     default:
 934         val = s->rregs[saddr];
 935         break;
 936     }
 937
 938     trace_esp_mem_readb(saddr, val);
 939     return val;
 940 }
 941
 942 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
 943 {
 944     trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
 945     switch (saddr) {
 946     case ESP_TCHI:
 947         s->tchi_written = true;
 948         /* fall through */
 949     case ESP_TCLO:
 950     case ESP_TCMID:
 951         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 952         break;
 953     case ESP_FIFO:
 954         if (s->do_cmd) {
 955             esp_fifo_push(&s->cmdfifo, val);
 956         } else {
 957             esp_fifo_push(&s->fifo, val);
 958         }
 959
 960         /* Non-DMA transfers raise an interrupt after every byte */
 961         if (s->rregs[ESP_CMD] == CMD_TI) {
 962             s->rregs[ESP_RINTR] |= INTR_FC | INTR_BS;
 963             esp_raise_irq(s);
 964         }
 965         break;
 966     case ESP_CMD:
 967         s->rregs[saddr] = val;
 968         if (val & CMD_DMA) {
 969             s->dma = 1;
 970             /* Reload DMA counter.  */
 971             if (esp_get_stc(s) == 0) {
 972                 esp_set_tc(s, 0x10000);
 973             } else {
 974                 esp_set_tc(s, esp_get_stc(s));
 975             }
 976         } else {
 977             s->dma = 0;
 978         }
 979         switch (val & CMD_CMD) {
 980         case CMD_NOP:
 981             trace_esp_mem_writeb_cmd_nop(val);
 982             break;
 983         case CMD_FLUSH:
 984             trace_esp_mem_writeb_cmd_flush(val);
 985             fifo8_reset(&s->fifo);
 986             break;
 987         case CMD_RESET:
 988             trace_esp_mem_writeb_cmd_reset(val);
 989             esp_soft_reset(s);
 990             break;
 991         case CMD_BUSRESET:
 992             trace_esp_mem_writeb_cmd_bus_reset(val);
 993             if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
 994                 s->rregs[ESP_RINTR] |= INTR_RST;
 995                 esp_raise_irq(s);
 996             }
 997             break;
 998         case CMD_TI:
 999             trace_esp_mem_writeb_cmd_ti(val);
1000             handle_ti(s);
1001             break;
1002         case CMD_ICCS:
1003             trace_esp_mem_writeb_cmd_iccs(val);
1004             write_response(s);
1005             s->rregs[ESP_RINTR] |= INTR_FC;
1006             s->rregs[ESP_RSTAT] |= STAT_MI;
1007             break;
1008         case CMD_MSGACC:
1009             trace_esp_mem_writeb_cmd_msgacc(val);
1010             s->rregs[ESP_RINTR] |= INTR_DC;
1011             s->rregs[ESP_RSEQ] = 0;
1012             s->rregs[ESP_RFLAGS] = 0;
1013             esp_raise_irq(s);
1014             break;
1015         case CMD_PAD:
1016             trace_esp_mem_writeb_cmd_pad(val);
1017             s->rregs[ESP_RSTAT] = STAT_TC;
1018             s->rregs[ESP_RINTR] |= INTR_FC;
1019             s->rregs[ESP_RSEQ] = 0;
1020             break;
1021         case CMD_SATN:
1022             trace_esp_mem_writeb_cmd_satn(val);
1023             break;
1024         case CMD_RSTATN:
1025             trace_esp_mem_writeb_cmd_rstatn(val);
1026             break;
1027         case CMD_SEL:
1028             trace_esp_mem_writeb_cmd_sel(val);
1029             handle_s_without_atn(s);
1030             break;
1031         case CMD_SELATN:
1032             trace_esp_mem_writeb_cmd_selatn(val);
1033             handle_satn(s);
1034             break;
1035         case CMD_SELATNS:
1036             trace_esp_mem_writeb_cmd_selatns(val);
1037             handle_satn_stop(s);
1038             break;
1039         case CMD_ENSEL:
1040             trace_esp_mem_writeb_cmd_ensel(val);
1041             s->rregs[ESP_RINTR] = 0;
1042             break;
1043         case CMD_DISSEL:
1044             trace_esp_mem_writeb_cmd_dissel(val);
1045             s->rregs[ESP_RINTR] = 0;
1046             esp_raise_irq(s);
1047             break;
1048         default:
1049             trace_esp_error_unhandled_command(val);
1050             break;
1051         }
1052         break;
1053     case ESP_WBUSID ... ESP_WSYNO:
1054         break;
1055     case ESP_CFG1:
1056     case ESP_CFG2: case ESP_CFG3:
1057     case ESP_RES3: case ESP_RES4:
1058         s->rregs[saddr] = val;
1059         break;
1060     case ESP_WCCF ... ESP_WTEST:
1061         break;
1062     default:
1063         trace_esp_error_invalid_write(val, saddr);
1064         return;
1065     }
1066     s->wregs[saddr] = val;
1067 }
1068
1069 static bool esp_mem_accepts(void *opaque, hwaddr addr,
1070                             unsigned size, bool is_write,
1071                             MemTxAttrs attrs)
1072 {
1073     return (size == 1) || (is_write && size == 4);
1074 }
1075
1076 static bool esp_is_before_version_5(void *opaque, int version_id)
1077 {
1078     ESPState *s = ESP(opaque);
1079
1080     version_id = MIN(version_id, s->mig_version_id);
1081     return version_id < 5;
1082 }
1083
1084 static bool esp_is_version_5(void *opaque, int version_id)
1085 {
1086     ESPState *s = ESP(opaque);
1087
1088     version_id = MIN(version_id, s->mig_version_id);
1089     return version_id == 5;
1090 }
1091
1092 int esp_pre_save(void *opaque)
1093 {
1094     ESPState *s = ESP(object_resolve_path_component(
1095                       OBJECT(opaque), "esp"));
1096
1097     s->mig_version_id = vmstate_esp.version_id;
1098     return 0;
1099 }
1100
1101 static int esp_post_load(void *opaque, int version_id)
1102 {
1103     ESPState *s = ESP(opaque);
1104     int len, i;
1105
1106     version_id = MIN(version_id, s->mig_version_id);
1107
1108     if (version_id < 5) {
1109         esp_set_tc(s, s->mig_dma_left);
1110
1111         /* Migrate ti_buf to fifo */
1112         len = s->mig_ti_wptr - s->mig_ti_rptr;
1113         for (i = 0; i < len; i++) {
1114             fifo8_push(&s->fifo, s->mig_ti_buf[i]);
1115         }
1116
1117         /* Migrate cmdbuf to cmdfifo */
1118         for (i = 0; i < s->mig_cmdlen; i++) {
1119             fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]);
1120         }
1121     }
1122
1123     s->mig_version_id = vmstate_esp.version_id;
1124     return 0;
1125 }
1126
1127 const VMStateDescription vmstate_esp = {
1128     .name = "esp",
1129     .version_id = 5,
1130     .minimum_version_id = 3,
1131     .post_load = esp_post_load,
1132     .fields = (VMStateField[]) {
1133         VMSTATE_BUFFER(rregs, ESPState),
1134         VMSTATE_BUFFER(wregs, ESPState),
1135         VMSTATE_INT32(ti_size, ESPState),
1136         VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5),
1137         VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5),
1138         VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5),
1139         VMSTATE_UINT32(status, ESPState),
1140         VMSTATE_UINT32_TEST(mig_deferred_status, ESPState,
1141                             esp_is_before_version_5),
1142         VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState,
1143                           esp_is_before_version_5),
1144         VMSTATE_UINT32(dma, ESPState),
1145         VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0,
1146                               esp_is_before_version_5, 0, 16),
1147         VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4,
1148                               esp_is_before_version_5, 16,
1149                               sizeof(typeof_field(ESPState, mig_cmdbuf))),
1150         VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5),
1151         VMSTATE_UINT32(do_cmd, ESPState),
1152         VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5),
1153         VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5),
1154         VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5),
1155         VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5),
1156         VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5),
1157         VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5),
1158         VMSTATE_END_OF_LIST()
1159     },
1160 };
1161
1162 static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
1163                                  uint64_t val, unsigned int size)
1164 {
1165     SysBusESPState *sysbus = opaque;
1166     ESPState *s = ESP(&sysbus->esp);
1167     uint32_t saddr;
1168
1169     saddr = addr >> sysbus->it_shift;
1170     esp_reg_write(s, saddr, val);
1171 }
1172
1173 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
1174                                     unsigned int size)
1175 {
1176     SysBusESPState *sysbus = opaque;
1177     ESPState *s = ESP(&sysbus->esp);
1178     uint32_t saddr;
1179
1180     saddr = addr >> sysbus->it_shift;
1181     return esp_reg_read(s, saddr);
1182 }
1183
1184 static const MemoryRegionOps sysbus_esp_mem_ops = {
1185     .read = sysbus_esp_mem_read,
1186     .write = sysbus_esp_mem_write,
1187     .endianness = DEVICE_NATIVE_ENDIAN,
1188     .valid.accepts = esp_mem_accepts,
1189 };
1190
1191 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr,
1192                                   uint64_t val, unsigned int size)
1193 {
1194     SysBusESPState *sysbus = opaque;
1195     ESPState *s = ESP(&sysbus->esp);
1196     uint32_t dmalen;
1197
1198     trace_esp_pdma_write(size);
1199
1200     switch (size) {
1201     case 1:
1202         esp_pdma_write(s, val);
1203         break;
1204     case 2:
1205         esp_pdma_write(s, val >> 8);
1206         esp_pdma_write(s, val);
1207         break;
1208     }
1209     dmalen = esp_get_tc(s);
1210     if (dmalen == 0 || fifo8_num_free(&s->fifo) < 2) {
1211         s->pdma_cb(s);
1212     }
1213 }
1214
1215 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr,
1216                                      unsigned int size)
1217 {
1218     SysBusESPState *sysbus = opaque;
1219     ESPState *s = ESP(&sysbus->esp);
1220     uint64_t val = 0;
1221
1222     trace_esp_pdma_read(size);
1223
1224     switch (size) {
1225     case 1:
1226         val = esp_pdma_read(s);
1227         break;
1228     case 2:
1229         val = esp_pdma_read(s);
1230         val = (val << 8) | esp_pdma_read(s);
1231         break;
1232     }
1233     if (fifo8_num_used(&s->fifo) < 2) {
1234         s->pdma_cb(s);
1235     }
1236     return val;
1237 }
1238
1239 static const MemoryRegionOps sysbus_esp_pdma_ops = {
1240     .read = sysbus_esp_pdma_read,
1241     .write = sysbus_esp_pdma_write,
1242     .endianness = DEVICE_NATIVE_ENDIAN,
1243     .valid.min_access_size = 1,
1244     .valid.max_access_size = 4,
1245     .impl.min_access_size = 1,
1246     .impl.max_access_size = 2,
1247 };
1248
1249 static const struct SCSIBusInfo esp_scsi_info = {
1250     .tcq = false,
1251     .max_target = ESP_MAX_DEVS,
1252     .max_lun = 7,
1253
1254     .transfer_data = esp_transfer_data,
1255     .complete = esp_command_complete,
1256     .cancel = esp_request_cancelled
1257 };
1258
1259 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
1260 {
1261     SysBusESPState *sysbus = SYSBUS_ESP(opaque);
1262     ESPState *s = ESP(&sysbus->esp);
1263
1264     switch (irq) {
1265     case 0:
1266         parent_esp_reset(s, irq, level);
1267         break;
1268     case 1:
1269         esp_dma_enable(opaque, irq, level);
1270         break;
1271     }
1272 }
1273
1274 static void sysbus_esp_realize(DeviceState *dev, Error **errp)
1275 {
1276     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1277     SysBusESPState *sysbus = SYSBUS_ESP(dev);
1278     ESPState *s = ESP(&sysbus->esp);
1279
1280     if (!qdev_realize(DEVICE(s), NULL, errp)) {
1281         return;
1282     }
1283
1284     sysbus_init_irq(sbd, &s->irq);
1285     sysbus_init_irq(sbd, &s->irq_data);
1286     assert(sysbus->it_shift != -1);
1287
1288     s->chip_id = TCHI_FAS100A;
1289     memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
1290                           sysbus, "esp-regs", ESP_REGS << sysbus->it_shift);
1291     sysbus_init_mmio(sbd, &sysbus->iomem);
1292     memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops,
1293                           sysbus, "esp-pdma", 4);
1294     sysbus_init_mmio(sbd, &sysbus->pdma);
1295
1296     qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
1297
1298     scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
1299 }
1300
1301 static void sysbus_esp_hard_reset(DeviceState *dev)
1302 {
1303     SysBusESPState *sysbus = SYSBUS_ESP(dev);
1304     ESPState *s = ESP(&sysbus->esp);
1305
1306     esp_hard_reset(s);
1307 }
1308
1309 static void sysbus_esp_init(Object *obj)
1310 {
1311     SysBusESPState *sysbus = SYSBUS_ESP(obj);
1312
1313     object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP);
1314 }
1315
1316 static const VMStateDescription vmstate_sysbus_esp_scsi = {
1317     .name = "sysbusespscsi",
1318     .version_id = 2,
1319     .minimum_version_id = 1,
1320     .pre_save = esp_pre_save,
1321     .fields = (VMStateField[]) {
1322         VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2),
1323         VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState),
1324         VMSTATE_END_OF_LIST()
1325     }
1326 };
1327
1328 static void sysbus_esp_class_init(ObjectClass *klass, void *data)
1329 {
1330     DeviceClass *dc = DEVICE_CLASS(klass);
1331
1332     dc->realize = sysbus_esp_realize;
1333     dc->reset = sysbus_esp_hard_reset;
1334     dc->vmsd = &vmstate_sysbus_esp_scsi;
1335     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1336 }
1337
1338 static const TypeInfo sysbus_esp_info = {
1339     .name          = TYPE_SYSBUS_ESP,
1340     .parent        = TYPE_SYS_BUS_DEVICE,
1341     .instance_init = sysbus_esp_init,
1342     .instance_size = sizeof(SysBusESPState),
1343     .class_init    = sysbus_esp_class_init,
1344 };
1345
1346 static void esp_finalize(Object *obj)
1347 {
1348     ESPState *s = ESP(obj);
1349
1350     fifo8_destroy(&s->fifo);
1351     fifo8_destroy(&s->cmdfifo);
1352 }
1353
1354 static void esp_init(Object *obj)
1355 {
1356     ESPState *s = ESP(obj);
1357
1358     fifo8_create(&s->fifo, ESP_FIFO_SZ);
1359     fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ);
1360 }
1361
1362 static void esp_class_init(ObjectClass *klass, void *data)
1363 {
1364     DeviceClass *dc = DEVICE_CLASS(klass);
1365
1366     /* internal device for sysbusesp/pciespscsi, not user-creatable */
1367     dc->user_creatable = false;
1368     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1369 }
1370
1371 static const TypeInfo esp_info = {
1372     .name = TYPE_ESP,
1373     .parent = TYPE_DEVICE,
1374     .instance_init = esp_init,
1375     .instance_finalize = esp_finalize,
1376     .instance_size = sizeof(ESPState),
1377     .class_init = esp_class_init,
1378 };
1379
1380 static void esp_register_types(void)
1381 {
1382     type_register_static(&sysbus_esp_info);
1383     type_register_static(&esp_info);
1384 }
1385
1386 type_init(esp_register_types)