2 * QEMU LSI53C895A SCSI Host Bus Adapter emulation
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the LGPL.
10 /* ??? Need to check if the {read,write}[wl] routines work properly on
11 big-endian targets. */
16 #include "hw/pci/pci.h"
17 #include "hw/scsi/scsi.h"
18 #include "sysemu/dma.h"
21 //#define DEBUG_LSI_REG
24 #define DPRINTF(fmt, ...) \
25 do { printf("lsi_scsi: " fmt , ## __VA_ARGS__); } while (0)
26 #define BADF(fmt, ...) \
27 do { fprintf(stderr, "lsi_scsi: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
29 #define DPRINTF(fmt, ...) do {} while(0)
30 #define BADF(fmt, ...) \
31 do { fprintf(stderr, "lsi_scsi: error: " fmt , ## __VA_ARGS__);} while (0)
34 #define LSI_MAX_DEVS 7
36 #define LSI_SCNTL0_TRG 0x01
37 #define LSI_SCNTL0_AAP 0x02
38 #define LSI_SCNTL0_EPC 0x08
39 #define LSI_SCNTL0_WATN 0x10
40 #define LSI_SCNTL0_START 0x20
42 #define LSI_SCNTL1_SST 0x01
43 #define LSI_SCNTL1_IARB 0x02
44 #define LSI_SCNTL1_AESP 0x04
45 #define LSI_SCNTL1_RST 0x08
46 #define LSI_SCNTL1_CON 0x10
47 #define LSI_SCNTL1_DHP 0x20
48 #define LSI_SCNTL1_ADB 0x40
49 #define LSI_SCNTL1_EXC 0x80
51 #define LSI_SCNTL2_WSR 0x01
52 #define LSI_SCNTL2_VUE0 0x02
53 #define LSI_SCNTL2_VUE1 0x04
54 #define LSI_SCNTL2_WSS 0x08
55 #define LSI_SCNTL2_SLPHBEN 0x10
56 #define LSI_SCNTL2_SLPMD 0x20
57 #define LSI_SCNTL2_CHM 0x40
58 #define LSI_SCNTL2_SDU 0x80
60 #define LSI_ISTAT0_DIP 0x01
61 #define LSI_ISTAT0_SIP 0x02
62 #define LSI_ISTAT0_INTF 0x04
63 #define LSI_ISTAT0_CON 0x08
64 #define LSI_ISTAT0_SEM 0x10
65 #define LSI_ISTAT0_SIGP 0x20
66 #define LSI_ISTAT0_SRST 0x40
67 #define LSI_ISTAT0_ABRT 0x80
69 #define LSI_ISTAT1_SI 0x01
70 #define LSI_ISTAT1_SRUN 0x02
71 #define LSI_ISTAT1_FLSH 0x04
73 #define LSI_SSTAT0_SDP0 0x01
74 #define LSI_SSTAT0_RST 0x02
75 #define LSI_SSTAT0_WOA 0x04
76 #define LSI_SSTAT0_LOA 0x08
77 #define LSI_SSTAT0_AIP 0x10
78 #define LSI_SSTAT0_OLF 0x20
79 #define LSI_SSTAT0_ORF 0x40
80 #define LSI_SSTAT0_ILF 0x80
82 #define LSI_SIST0_PAR 0x01
83 #define LSI_SIST0_RST 0x02
84 #define LSI_SIST0_UDC 0x04
85 #define LSI_SIST0_SGE 0x08
86 #define LSI_SIST0_RSL 0x10
87 #define LSI_SIST0_SEL 0x20
88 #define LSI_SIST0_CMP 0x40
89 #define LSI_SIST0_MA 0x80
91 #define LSI_SIST1_HTH 0x01
92 #define LSI_SIST1_GEN 0x02
93 #define LSI_SIST1_STO 0x04
94 #define LSI_SIST1_SBMC 0x10
96 #define LSI_SOCL_IO 0x01
97 #define LSI_SOCL_CD 0x02
98 #define LSI_SOCL_MSG 0x04
99 #define LSI_SOCL_ATN 0x08
100 #define LSI_SOCL_SEL 0x10
101 #define LSI_SOCL_BSY 0x20
102 #define LSI_SOCL_ACK 0x40
103 #define LSI_SOCL_REQ 0x80
105 #define LSI_DSTAT_IID 0x01
106 #define LSI_DSTAT_SIR 0x04
107 #define LSI_DSTAT_SSI 0x08
108 #define LSI_DSTAT_ABRT 0x10
109 #define LSI_DSTAT_BF 0x20
110 #define LSI_DSTAT_MDPE 0x40
111 #define LSI_DSTAT_DFE 0x80
113 #define LSI_DCNTL_COM 0x01
114 #define LSI_DCNTL_IRQD 0x02
115 #define LSI_DCNTL_STD 0x04
116 #define LSI_DCNTL_IRQM 0x08
117 #define LSI_DCNTL_SSM 0x10
118 #define LSI_DCNTL_PFEN 0x20
119 #define LSI_DCNTL_PFF 0x40
120 #define LSI_DCNTL_CLSE 0x80
122 #define LSI_DMODE_MAN 0x01
123 #define LSI_DMODE_BOF 0x02
124 #define LSI_DMODE_ERMP 0x04
125 #define LSI_DMODE_ERL 0x08
126 #define LSI_DMODE_DIOM 0x10
127 #define LSI_DMODE_SIOM 0x20
129 #define LSI_CTEST2_DACK 0x01
130 #define LSI_CTEST2_DREQ 0x02
131 #define LSI_CTEST2_TEOP 0x04
132 #define LSI_CTEST2_PCICIE 0x08
133 #define LSI_CTEST2_CM 0x10
134 #define LSI_CTEST2_CIO 0x20
135 #define LSI_CTEST2_SIGP 0x40
136 #define LSI_CTEST2_DDIR 0x80
138 #define LSI_CTEST5_BL2 0x04
139 #define LSI_CTEST5_DDIR 0x08
140 #define LSI_CTEST5_MASR 0x10
141 #define LSI_CTEST5_DFSN 0x20
142 #define LSI_CTEST5_BBCK 0x40
143 #define LSI_CTEST5_ADCK 0x80
145 #define LSI_CCNTL0_DILS 0x01
146 #define LSI_CCNTL0_DISFC 0x10
147 #define LSI_CCNTL0_ENNDJ 0x20
148 #define LSI_CCNTL0_PMJCTL 0x40
149 #define LSI_CCNTL0_ENPMJ 0x80
151 #define LSI_CCNTL1_EN64DBMV 0x01
152 #define LSI_CCNTL1_EN64TIBMV 0x02
153 #define LSI_CCNTL1_64TIMOD 0x04
154 #define LSI_CCNTL1_DDAC 0x08
155 #define LSI_CCNTL1_ZMOD 0x80
157 /* Enable Response to Reselection */
158 #define LSI_SCID_RRE 0x60
160 #define LSI_CCNTL1_40BIT (LSI_CCNTL1_EN64TIBMV|LSI_CCNTL1_64TIMOD)
170 /* Maximum length of MSG IN data. */
171 #define LSI_MAX_MSGIN_LEN 8
173 /* Flag set if this is a tagged command. */
174 #define LSI_TAG_VALID (1 << 16)
176 typedef struct lsi_request
{
183 QTAILQ_ENTRY(lsi_request
) next
;
188 PCIDevice parent_obj
;
191 MemoryRegion mmio_io
;
195 int carry
; /* ??? Should this be an a visible register somewhere? */
197 /* Action to take at the end of a MSG IN phase.
198 0 = COMMAND, 1 = disconnect, 2 = DATA OUT, 3 = DATA IN. */
201 uint8_t msg
[LSI_MAX_MSGIN_LEN
];
202 /* 0 if SCRIPTS are running or stopped.
203 * 1 if a Wait Reselect instruction has been issued.
204 * 2 if processing DMA from lsi_execute_script.
205 * 3 if a DMA operation is in progress. */
209 /* The tag is a combination of the device ID and the SCSI tag. */
211 int command_complete
;
212 QTAILQ_HEAD(, lsi_request
) queue
;
213 lsi_request
*current
;
274 uint32_t scratch
[18]; /* SCRATCHA-SCRATCHR */
277 /* Script ram is stored as 32-bit words in host byteorder. */
278 uint32_t script_ram
[2048];
281 #define TYPE_LSI53C895A "lsi53c895a"
283 #define LSI53C895A(obj) \
284 OBJECT_CHECK(LSIState, (obj), TYPE_LSI53C895A)
286 static inline int lsi_irq_on_rsl(LSIState
*s
)
288 return (s
->sien0
& LSI_SIST0_RSL
) && (s
->scid
& LSI_SCID_RRE
);
291 static void lsi_soft_reset(LSIState
*s
)
303 memset(s
->scratch
, 0, sizeof(s
->scratch
));
307 s
->dstat
= LSI_DSTAT_DFE
;
316 s
->ctest2
= LSI_CTEST2_DACK
;
359 assert(QTAILQ_EMPTY(&s
->queue
));
363 static int lsi_dma_40bit(LSIState
*s
)
365 if ((s
->ccntl1
& LSI_CCNTL1_40BIT
) == LSI_CCNTL1_40BIT
)
370 static int lsi_dma_ti64bit(LSIState
*s
)
372 if ((s
->ccntl1
& LSI_CCNTL1_EN64TIBMV
) == LSI_CCNTL1_EN64TIBMV
)
377 static int lsi_dma_64bit(LSIState
*s
)
379 if ((s
->ccntl1
& LSI_CCNTL1_EN64DBMV
) == LSI_CCNTL1_EN64DBMV
)
384 static uint8_t lsi_reg_readb(LSIState
*s
, int offset
);
385 static void lsi_reg_writeb(LSIState
*s
, int offset
, uint8_t val
);
386 static void lsi_execute_script(LSIState
*s
);
387 static void lsi_reselect(LSIState
*s
, lsi_request
*p
);
389 static inline uint32_t read_dword(LSIState
*s
, uint32_t addr
)
393 pci_dma_read(PCI_DEVICE(s
), addr
, &buf
, 4);
394 return cpu_to_le32(buf
);
397 static void lsi_stop_script(LSIState
*s
)
399 s
->istat1
&= ~LSI_ISTAT1_SRUN
;
402 static void lsi_update_irq(LSIState
*s
)
404 PCIDevice
*d
= PCI_DEVICE(s
);
406 static int last_level
;
409 /* It's unclear whether the DIP/SIP bits should be cleared when the
410 Interrupt Status Registers are cleared or when istat0 is read.
411 We currently do the formwer, which seems to work. */
414 if (s
->dstat
& s
->dien
)
416 s
->istat0
|= LSI_ISTAT0_DIP
;
418 s
->istat0
&= ~LSI_ISTAT0_DIP
;
421 if (s
->sist0
|| s
->sist1
) {
422 if ((s
->sist0
& s
->sien0
) || (s
->sist1
& s
->sien1
))
424 s
->istat0
|= LSI_ISTAT0_SIP
;
426 s
->istat0
&= ~LSI_ISTAT0_SIP
;
428 if (s
->istat0
& LSI_ISTAT0_INTF
)
431 if (level
!= last_level
) {
432 DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
433 level
, s
->dstat
, s
->sist1
, s
->sist0
);
436 qemu_set_irq(d
->irq
[0], level
);
438 if (!level
&& lsi_irq_on_rsl(s
) && !(s
->scntl1
& LSI_SCNTL1_CON
)) {
439 DPRINTF("Handled IRQs & disconnected, looking for pending "
441 QTAILQ_FOREACH(p
, &s
->queue
, next
) {
450 /* Stop SCRIPTS execution and raise a SCSI interrupt. */
451 static void lsi_script_scsi_interrupt(LSIState
*s
, int stat0
, int stat1
)
456 DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
457 stat1
, stat0
, s
->sist1
, s
->sist0
);
460 /* Stop processor on fatal or unmasked interrupt. As a special hack
461 we don't stop processing when raising STO. Instead continue
462 execution and stop at the next insn that accesses the SCSI bus. */
463 mask0
= s
->sien0
| ~(LSI_SIST0_CMP
| LSI_SIST0_SEL
| LSI_SIST0_RSL
);
464 mask1
= s
->sien1
| ~(LSI_SIST1_GEN
| LSI_SIST1_HTH
);
465 mask1
&= ~LSI_SIST1_STO
;
466 if (s
->sist0
& mask0
|| s
->sist1
& mask1
) {
472 /* Stop SCRIPTS execution and raise a DMA interrupt. */
473 static void lsi_script_dma_interrupt(LSIState
*s
, int stat
)
475 DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat
, s
->dstat
);
481 static inline void lsi_set_phase(LSIState
*s
, int phase
)
483 s
->sstat1
= (s
->sstat1
& ~PHASE_MASK
) | phase
;
486 static void lsi_bad_phase(LSIState
*s
, int out
, int new_phase
)
488 /* Trigger a phase mismatch. */
489 if (s
->ccntl0
& LSI_CCNTL0_ENPMJ
) {
490 if ((s
->ccntl0
& LSI_CCNTL0_PMJCTL
)) {
491 s
->dsp
= out
? s
->pmjad1
: s
->pmjad2
;
493 s
->dsp
= (s
->scntl2
& LSI_SCNTL2_WSR
? s
->pmjad2
: s
->pmjad1
);
495 DPRINTF("Data phase mismatch jump to %08x\n", s
->dsp
);
497 DPRINTF("Phase mismatch interrupt\n");
498 lsi_script_scsi_interrupt(s
, LSI_SIST0_MA
, 0);
501 lsi_set_phase(s
, new_phase
);
505 /* Resume SCRIPTS execution after a DMA operation. */
506 static void lsi_resume_script(LSIState
*s
)
508 if (s
->waiting
!= 2) {
510 lsi_execute_script(s
);
516 static void lsi_disconnect(LSIState
*s
)
518 s
->scntl1
&= ~LSI_SCNTL1_CON
;
519 s
->sstat1
&= ~PHASE_MASK
;
522 static void lsi_bad_selection(LSIState
*s
, uint32_t id
)
524 DPRINTF("Selected absent target %d\n", id
);
525 lsi_script_scsi_interrupt(s
, 0, LSI_SIST1_STO
);
529 /* Initiate a SCSI layer data transfer. */
530 static void lsi_do_dma(LSIState
*s
, int out
)
538 if (!s
->current
->dma_len
) {
539 /* Wait until data is available. */
540 DPRINTF("DMA no data available\n");
544 pci_dev
= PCI_DEVICE(s
);
545 dev
= s
->current
->req
->dev
;
549 if (count
> s
->current
->dma_len
)
550 count
= s
->current
->dma_len
;
553 /* both 40 and Table Indirect 64-bit DMAs store upper bits in dnad64 */
554 if (lsi_dma_40bit(s
) || lsi_dma_ti64bit(s
))
555 addr
|= ((uint64_t)s
->dnad64
<< 32);
557 addr
|= ((uint64_t)s
->dbms
<< 32);
559 addr
|= ((uint64_t)s
->sbms
<< 32);
561 DPRINTF("DMA addr=0x" DMA_ADDR_FMT
" len=%d\n", addr
, count
);
565 if (s
->current
->dma_buf
== NULL
) {
566 s
->current
->dma_buf
= scsi_req_get_buf(s
->current
->req
);
568 /* ??? Set SFBR to first data byte. */
570 pci_dma_read(pci_dev
, addr
, s
->current
->dma_buf
, count
);
572 pci_dma_write(pci_dev
, addr
, s
->current
->dma_buf
, count
);
574 s
->current
->dma_len
-= count
;
575 if (s
->current
->dma_len
== 0) {
576 s
->current
->dma_buf
= NULL
;
577 scsi_req_continue(s
->current
->req
);
579 s
->current
->dma_buf
+= count
;
580 lsi_resume_script(s
);
585 /* Add a command to the queue. */
586 static void lsi_queue_command(LSIState
*s
)
588 lsi_request
*p
= s
->current
;
590 DPRINTF("Queueing tag=0x%x\n", p
->tag
);
591 assert(s
->current
!= NULL
);
592 assert(s
->current
->dma_len
== 0);
593 QTAILQ_INSERT_TAIL(&s
->queue
, s
->current
, next
);
597 p
->out
= (s
->sstat1
& PHASE_MASK
) == PHASE_DO
;
600 /* Queue a byte for a MSG IN phase. */
601 static void lsi_add_msg_byte(LSIState
*s
, uint8_t data
)
603 if (s
->msg_len
>= LSI_MAX_MSGIN_LEN
) {
604 BADF("MSG IN data too long\n");
606 DPRINTF("MSG IN 0x%02x\n", data
);
607 s
->msg
[s
->msg_len
++] = data
;
611 /* Perform reselection to continue a command. */
612 static void lsi_reselect(LSIState
*s
, lsi_request
*p
)
616 assert(s
->current
== NULL
);
617 QTAILQ_REMOVE(&s
->queue
, p
, next
);
620 id
= (p
->tag
>> 8) & 0xf;
622 /* LSI53C700 Family Compatibility, see LSI53C895A 4-73 */
623 if (!(s
->dcntl
& LSI_DCNTL_COM
)) {
624 s
->sfbr
= 1 << (id
& 0x7);
626 DPRINTF("Reselected target %d\n", id
);
627 s
->scntl1
|= LSI_SCNTL1_CON
;
628 lsi_set_phase(s
, PHASE_MI
);
629 s
->msg_action
= p
->out
? 2 : 3;
630 s
->current
->dma_len
= p
->pending
;
631 lsi_add_msg_byte(s
, 0x80);
632 if (s
->current
->tag
& LSI_TAG_VALID
) {
633 lsi_add_msg_byte(s
, 0x20);
634 lsi_add_msg_byte(s
, p
->tag
& 0xff);
637 if (lsi_irq_on_rsl(s
)) {
638 lsi_script_scsi_interrupt(s
, LSI_SIST0_RSL
, 0);
642 static lsi_request
*lsi_find_by_tag(LSIState
*s
, uint32_t tag
)
646 QTAILQ_FOREACH(p
, &s
->queue
, next
) {
655 static void lsi_request_free(LSIState
*s
, lsi_request
*p
)
657 if (p
== s
->current
) {
660 QTAILQ_REMOVE(&s
->queue
, p
, next
);
665 static void lsi_request_cancelled(SCSIRequest
*req
)
667 LSIState
*s
= LSI53C895A(req
->bus
->qbus
.parent
);
668 lsi_request
*p
= req
->hba_private
;
670 req
->hba_private
= NULL
;
671 lsi_request_free(s
, p
);
675 /* Record that data is available for a queued command. Returns zero if
676 the device was reselected, nonzero if the IO is deferred. */
677 static int lsi_queue_req(LSIState
*s
, SCSIRequest
*req
, uint32_t len
)
679 lsi_request
*p
= req
->hba_private
;
682 BADF("Multiple IO pending for request %p\n", p
);
685 /* Reselect if waiting for it, or if reselection triggers an IRQ
687 Since no interrupt stacking is implemented in the emulation, it
688 is also required that there are no pending interrupts waiting
689 for service from the device driver. */
690 if (s
->waiting
== 1 ||
691 (lsi_irq_on_rsl(s
) && !(s
->scntl1
& LSI_SCNTL1_CON
) &&
692 !(s
->istat0
& (LSI_ISTAT0_SIP
| LSI_ISTAT0_DIP
)))) {
693 /* Reselect device. */
697 DPRINTF("Queueing IO tag=0x%x\n", p
->tag
);
703 /* Callback to indicate that the SCSI layer has completed a command. */
704 static void lsi_command_complete(SCSIRequest
*req
, uint32_t status
, size_t resid
)
706 LSIState
*s
= LSI53C895A(req
->bus
->qbus
.parent
);
709 out
= (s
->sstat1
& PHASE_MASK
) == PHASE_DO
;
710 DPRINTF("Command complete status=%d\n", (int)status
);
712 s
->command_complete
= 2;
713 if (s
->waiting
&& s
->dbc
!= 0) {
714 /* Raise phase mismatch for short transfers. */
715 lsi_bad_phase(s
, out
, PHASE_ST
);
717 lsi_set_phase(s
, PHASE_ST
);
720 if (req
->hba_private
== s
->current
) {
721 req
->hba_private
= NULL
;
722 lsi_request_free(s
, s
->current
);
725 lsi_resume_script(s
);
728 /* Callback to indicate that the SCSI layer has completed a transfer. */
729 static void lsi_transfer_data(SCSIRequest
*req
, uint32_t len
)
731 LSIState
*s
= LSI53C895A(req
->bus
->qbus
.parent
);
734 assert(req
->hba_private
);
735 if (s
->waiting
== 1 || req
->hba_private
!= s
->current
||
736 (lsi_irq_on_rsl(s
) && !(s
->scntl1
& LSI_SCNTL1_CON
))) {
737 if (lsi_queue_req(s
, req
, len
)) {
742 out
= (s
->sstat1
& PHASE_MASK
) == PHASE_DO
;
744 /* host adapter (re)connected */
745 DPRINTF("Data ready tag=0x%x len=%d\n", req
->tag
, len
);
746 s
->current
->dma_len
= len
;
747 s
->command_complete
= 1;
749 if (s
->waiting
== 1 || s
->dbc
== 0) {
750 lsi_resume_script(s
);
757 static void lsi_do_command(LSIState
*s
)
764 DPRINTF("Send command len=%d\n", s
->dbc
);
767 pci_dma_read(PCI_DEVICE(s
), s
->dnad
, buf
, s
->dbc
);
769 s
->command_complete
= 0;
771 id
= (s
->select_tag
>> 8) & 0xf;
772 dev
= scsi_device_find(&s
->bus
, 0, id
, s
->current_lun
);
774 lsi_bad_selection(s
, id
);
778 assert(s
->current
== NULL
);
779 s
->current
= g_malloc0(sizeof(lsi_request
));
780 s
->current
->tag
= s
->select_tag
;
781 s
->current
->req
= scsi_req_new(dev
, s
->current
->tag
, s
->current_lun
, buf
,
784 n
= scsi_req_enqueue(s
->current
->req
);
787 lsi_set_phase(s
, PHASE_DI
);
789 lsi_set_phase(s
, PHASE_DO
);
791 scsi_req_continue(s
->current
->req
);
793 if (!s
->command_complete
) {
795 /* Command did not complete immediately so disconnect. */
796 lsi_add_msg_byte(s
, 2); /* SAVE DATA POINTER */
797 lsi_add_msg_byte(s
, 4); /* DISCONNECT */
799 lsi_set_phase(s
, PHASE_MI
);
801 lsi_queue_command(s
);
803 /* wait command complete */
804 lsi_set_phase(s
, PHASE_DI
);
809 static void lsi_do_status(LSIState
*s
)
812 DPRINTF("Get status len=%d status=%d\n", s
->dbc
, s
->status
);
814 BADF("Bad Status move\n");
818 pci_dma_write(PCI_DEVICE(s
), s
->dnad
, &status
, 1);
819 lsi_set_phase(s
, PHASE_MI
);
821 lsi_add_msg_byte(s
, 0); /* COMMAND COMPLETE */
824 static void lsi_do_msgin(LSIState
*s
)
827 DPRINTF("Message in len=%d/%d\n", s
->dbc
, s
->msg_len
);
832 pci_dma_write(PCI_DEVICE(s
), s
->dnad
, s
->msg
, len
);
833 /* Linux drivers rely on the last byte being in the SIDL. */
834 s
->sidl
= s
->msg
[len
- 1];
837 memmove(s
->msg
, s
->msg
+ len
, s
->msg_len
);
839 /* ??? Check if ATN (not yet implemented) is asserted and maybe
840 switch to PHASE_MO. */
841 switch (s
->msg_action
) {
843 lsi_set_phase(s
, PHASE_CMD
);
849 lsi_set_phase(s
, PHASE_DO
);
852 lsi_set_phase(s
, PHASE_DI
);
860 /* Read the next byte during a MSGOUT phase. */
861 static uint8_t lsi_get_msgbyte(LSIState
*s
)
864 pci_dma_read(PCI_DEVICE(s
), s
->dnad
, &data
, 1);
870 /* Skip the next n bytes during a MSGOUT phase. */
871 static void lsi_skip_msgbytes(LSIState
*s
, unsigned int n
)
877 static void lsi_do_msgout(LSIState
*s
)
881 uint32_t current_tag
;
882 lsi_request
*current_req
, *p
, *p_next
;
885 current_tag
= s
->current
->tag
;
886 current_req
= s
->current
;
888 current_tag
= s
->select_tag
;
889 current_req
= lsi_find_by_tag(s
, current_tag
);
892 DPRINTF("MSG out len=%d\n", s
->dbc
);
894 msg
= lsi_get_msgbyte(s
);
899 DPRINTF("MSG: Disconnect\n");
903 DPRINTF("MSG: No Operation\n");
904 lsi_set_phase(s
, PHASE_CMD
);
907 len
= lsi_get_msgbyte(s
);
908 msg
= lsi_get_msgbyte(s
);
909 (void)len
; /* avoid a warning about unused variable*/
910 DPRINTF("Extended message 0x%x (len %d)\n", msg
, len
);
913 DPRINTF("SDTR (ignored)\n");
914 lsi_skip_msgbytes(s
, 2);
917 DPRINTF("WDTR (ignored)\n");
918 lsi_skip_msgbytes(s
, 1);
924 case 0x20: /* SIMPLE queue */
925 s
->select_tag
|= lsi_get_msgbyte(s
) | LSI_TAG_VALID
;
926 DPRINTF("SIMPLE queue tag=0x%x\n", s
->select_tag
& 0xff);
928 case 0x21: /* HEAD of queue */
929 BADF("HEAD queue not implemented\n");
930 s
->select_tag
|= lsi_get_msgbyte(s
) | LSI_TAG_VALID
;
932 case 0x22: /* ORDERED queue */
933 BADF("ORDERED queue not implemented\n");
934 s
->select_tag
|= lsi_get_msgbyte(s
) | LSI_TAG_VALID
;
937 /* The ABORT TAG message clears the current I/O process only. */
938 DPRINTF("MSG: ABORT TAG tag=0x%x\n", current_tag
);
940 scsi_req_cancel(current_req
->req
);
947 /* The ABORT message clears all I/O processes for the selecting
948 initiator on the specified logical unit of the target. */
950 DPRINTF("MSG: ABORT tag=0x%x\n", current_tag
);
952 /* The CLEAR QUEUE message clears all I/O processes for all
953 initiators on the specified logical unit of the target. */
955 DPRINTF("MSG: CLEAR QUEUE tag=0x%x\n", current_tag
);
957 /* The BUS DEVICE RESET message clears all I/O processes for all
958 initiators on all logical units of the target. */
960 DPRINTF("MSG: BUS DEVICE RESET tag=0x%x\n", current_tag
);
963 /* clear the current I/O process */
965 scsi_req_cancel(s
->current
->req
);
968 /* As the current implemented devices scsi_disk and scsi_generic
969 only support one LUN, we don't need to keep track of LUNs.
970 Clearing I/O processes for other initiators could be possible
971 for scsi_generic by sending a SG_SCSI_RESET to the /dev/sgX
972 device, but this is currently not implemented (and seems not
973 to be really necessary). So let's simply clear all queued
974 commands for the current device: */
975 QTAILQ_FOREACH_SAFE(p
, &s
->queue
, next
, p_next
) {
976 if ((p
->tag
& 0x0000ff00) == (current_tag
& 0x0000ff00)) {
977 scsi_req_cancel(p
->req
);
984 if ((msg
& 0x80) == 0) {
987 s
->current_lun
= msg
& 7;
988 DPRINTF("Select LUN %d\n", s
->current_lun
);
989 lsi_set_phase(s
, PHASE_CMD
);
995 BADF("Unimplemented message 0x%02x\n", msg
);
996 lsi_set_phase(s
, PHASE_MI
);
997 lsi_add_msg_byte(s
, 7); /* MESSAGE REJECT */
1001 #define LSI_BUF_SIZE 4096
1002 static void lsi_memcpy(LSIState
*s
, uint32_t dest
, uint32_t src
, int count
)
1004 PCIDevice
*d
= PCI_DEVICE(s
);
1006 uint8_t buf
[LSI_BUF_SIZE
];
1008 DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest
, src
, count
);
1010 n
= (count
> LSI_BUF_SIZE
) ? LSI_BUF_SIZE
: count
;
1011 pci_dma_read(d
, src
, buf
, n
);
1012 pci_dma_write(d
, dest
, buf
, n
);
1019 static void lsi_wait_reselect(LSIState
*s
)
1023 DPRINTF("Wait Reselect\n");
1025 QTAILQ_FOREACH(p
, &s
->queue
, next
) {
1031 if (s
->current
== NULL
) {
1036 static void lsi_execute_script(LSIState
*s
)
1038 PCIDevice
*pci_dev
= PCI_DEVICE(s
);
1040 uint32_t addr
, addr_high
;
1042 int insn_processed
= 0;
1044 s
->istat1
|= LSI_ISTAT1_SRUN
;
1047 insn
= read_dword(s
, s
->dsp
);
1049 /* If we receive an empty opcode increment the DSP by 4 bytes
1050 instead of 8 and execute the next opcode at that location */
1054 addr
= read_dword(s
, s
->dsp
+ 4);
1056 DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s
->dsp
, insn
, addr
);
1058 s
->dcmd
= insn
>> 24;
1060 switch (insn
>> 30) {
1061 case 0: /* Block move. */
1062 if (s
->sist1
& LSI_SIST1_STO
) {
1063 DPRINTF("Delayed select timeout\n");
1067 s
->dbc
= insn
& 0xffffff;
1071 if (insn
& (1 << 29)) {
1072 /* Indirect addressing. */
1073 addr
= read_dword(s
, addr
);
1074 } else if (insn
& (1 << 28)) {
1077 /* Table indirect addressing. */
1079 /* 32-bit Table indirect */
1080 offset
= sextract32(addr
, 0, 24);
1081 pci_dma_read(pci_dev
, s
->dsa
+ offset
, buf
, 8);
1082 /* byte count is stored in bits 0:23 only */
1083 s
->dbc
= cpu_to_le32(buf
[0]) & 0xffffff;
1085 addr
= cpu_to_le32(buf
[1]);
1087 /* 40-bit DMA, upper addr bits [39:32] stored in first DWORD of
1088 * table, bits [31:24] */
1089 if (lsi_dma_40bit(s
))
1090 addr_high
= cpu_to_le32(buf
[0]) >> 24;
1091 else if (lsi_dma_ti64bit(s
)) {
1092 int selector
= (cpu_to_le32(buf
[0]) >> 24) & 0x1f;
1095 /* offset index into scratch registers since
1096 * TI64 mode can use registers C to R */
1097 addr_high
= s
->scratch
[2 + selector
];
1100 addr_high
= s
->mmrs
;
1103 addr_high
= s
->mmws
;
1112 addr_high
= s
->sbms
;
1115 addr_high
= s
->dbms
;
1118 BADF("Illegal selector specified (0x%x > 0x15)"
1119 " for 64-bit DMA block move", selector
);
1123 } else if (lsi_dma_64bit(s
)) {
1124 /* fetch a 3rd dword if 64-bit direct move is enabled and
1125 only if we're not doing table indirect or indirect addressing */
1126 s
->dbms
= read_dword(s
, s
->dsp
);
1128 s
->ia
= s
->dsp
- 12;
1130 if ((s
->sstat1
& PHASE_MASK
) != ((insn
>> 24) & 7)) {
1131 DPRINTF("Wrong phase got %d expected %d\n",
1132 s
->sstat1
& PHASE_MASK
, (insn
>> 24) & 7);
1133 lsi_script_scsi_interrupt(s
, LSI_SIST0_MA
, 0);
1137 s
->dnad64
= addr_high
;
1138 switch (s
->sstat1
& 0x7) {
1164 BADF("Unimplemented phase %d\n", s
->sstat1
& PHASE_MASK
);
1167 s
->dfifo
= s
->dbc
& 0xff;
1168 s
->ctest5
= (s
->ctest5
& 0xfc) | ((s
->dbc
>> 8) & 3);
1171 s
->ua
= addr
+ s
->dbc
;
1174 case 1: /* IO or Read/Write instruction. */
1175 opcode
= (insn
>> 27) & 7;
1179 if (insn
& (1 << 25)) {
1180 id
= read_dword(s
, s
->dsa
+ sextract32(insn
, 0, 24));
1184 id
= (id
>> 16) & 0xf;
1185 if (insn
& (1 << 26)) {
1186 addr
= s
->dsp
+ sextract32(addr
, 0, 24);
1190 case 0: /* Select */
1192 if (s
->scntl1
& LSI_SCNTL1_CON
) {
1193 DPRINTF("Already reselected, jumping to alternative address\n");
1197 s
->sstat0
|= LSI_SSTAT0_WOA
;
1198 s
->scntl1
&= ~LSI_SCNTL1_IARB
;
1199 if (!scsi_device_find(&s
->bus
, 0, id
, 0)) {
1200 lsi_bad_selection(s
, id
);
1203 DPRINTF("Selected target %d%s\n",
1204 id
, insn
& (1 << 3) ? " ATN" : "");
1205 /* ??? Linux drivers compain when this is set. Maybe
1206 it only applies in low-level mode (unimplemented).
1207 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
1208 s
->select_tag
= id
<< 8;
1209 s
->scntl1
|= LSI_SCNTL1_CON
;
1210 if (insn
& (1 << 3)) {
1211 s
->socl
|= LSI_SOCL_ATN
;
1213 lsi_set_phase(s
, PHASE_MO
);
1215 case 1: /* Disconnect */
1216 DPRINTF("Wait Disconnect\n");
1217 s
->scntl1
&= ~LSI_SCNTL1_CON
;
1219 case 2: /* Wait Reselect */
1220 if (!lsi_irq_on_rsl(s
)) {
1221 lsi_wait_reselect(s
);
1225 DPRINTF("Set%s%s%s%s\n",
1226 insn
& (1 << 3) ? " ATN" : "",
1227 insn
& (1 << 6) ? " ACK" : "",
1228 insn
& (1 << 9) ? " TM" : "",
1229 insn
& (1 << 10) ? " CC" : "");
1230 if (insn
& (1 << 3)) {
1231 s
->socl
|= LSI_SOCL_ATN
;
1232 lsi_set_phase(s
, PHASE_MO
);
1234 if (insn
& (1 << 9)) {
1235 BADF("Target mode not implemented\n");
1238 if (insn
& (1 << 10))
1242 DPRINTF("Clear%s%s%s%s\n",
1243 insn
& (1 << 3) ? " ATN" : "",
1244 insn
& (1 << 6) ? " ACK" : "",
1245 insn
& (1 << 9) ? " TM" : "",
1246 insn
& (1 << 10) ? " CC" : "");
1247 if (insn
& (1 << 3)) {
1248 s
->socl
&= ~LSI_SOCL_ATN
;
1250 if (insn
& (1 << 10))
1261 static const char *opcode_names
[3] =
1262 {"Write", "Read", "Read-Modify-Write"};
1263 static const char *operator_names
[8] =
1264 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1267 reg
= ((insn
>> 16) & 0x7f) | (insn
& 0x80);
1268 data8
= (insn
>> 8) & 0xff;
1269 opcode
= (insn
>> 27) & 7;
1270 operator = (insn
>> 24) & 7;
1271 DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1272 opcode_names
[opcode
- 5], reg
,
1273 operator_names
[operator], data8
, s
->sfbr
,
1274 (insn
& (1 << 23)) ? " SFBR" : "");
1277 case 5: /* From SFBR */
1281 case 6: /* To SFBR */
1283 op0
= lsi_reg_readb(s
, reg
);
1286 case 7: /* Read-modify-write */
1288 op0
= lsi_reg_readb(s
, reg
);
1289 if (insn
& (1 << 23)) {
1301 case 1: /* Shift left */
1303 op0
= (op0
<< 1) | s
->carry
;
1317 op0
= (op0
>> 1) | (s
->carry
<< 7);
1322 s
->carry
= op0
< op1
;
1325 op0
+= op1
+ s
->carry
;
1327 s
->carry
= op0
<= op1
;
1329 s
->carry
= op0
< op1
;
1334 case 5: /* From SFBR */
1335 case 7: /* Read-modify-write */
1336 lsi_reg_writeb(s
, reg
, op0
);
1338 case 6: /* To SFBR */
1345 case 2: /* Transfer Control. */
1350 if ((insn
& 0x002e0000) == 0) {
1354 if (s
->sist1
& LSI_SIST1_STO
) {
1355 DPRINTF("Delayed select timeout\n");
1359 cond
= jmp
= (insn
& (1 << 19)) != 0;
1360 if (cond
== jmp
&& (insn
& (1 << 21))) {
1361 DPRINTF("Compare carry %d\n", s
->carry
== jmp
);
1362 cond
= s
->carry
!= 0;
1364 if (cond
== jmp
&& (insn
& (1 << 17))) {
1365 DPRINTF("Compare phase %d %c= %d\n",
1366 (s
->sstat1
& PHASE_MASK
),
1368 ((insn
>> 24) & 7));
1369 cond
= (s
->sstat1
& PHASE_MASK
) == ((insn
>> 24) & 7);
1371 if (cond
== jmp
&& (insn
& (1 << 18))) {
1374 mask
= (~insn
>> 8) & 0xff;
1375 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1376 s
->sfbr
, mask
, jmp
? '=' : '!', insn
& mask
);
1377 cond
= (s
->sfbr
& mask
) == (insn
& mask
);
1380 if (insn
& (1 << 23)) {
1381 /* Relative address. */
1382 addr
= s
->dsp
+ sextract32(addr
, 0, 24);
1384 switch ((insn
>> 27) & 7) {
1386 DPRINTF("Jump to 0x%08x\n", addr
);
1390 DPRINTF("Call 0x%08x\n", addr
);
1394 case 2: /* Return */
1395 DPRINTF("Return to 0x%08x\n", s
->temp
);
1398 case 3: /* Interrupt */
1399 DPRINTF("Interrupt 0x%08x\n", s
->dsps
);
1400 if ((insn
& (1 << 20)) != 0) {
1401 s
->istat0
|= LSI_ISTAT0_INTF
;
1404 lsi_script_dma_interrupt(s
, LSI_DSTAT_SIR
);
1408 DPRINTF("Illegal transfer control\n");
1409 lsi_script_dma_interrupt(s
, LSI_DSTAT_IID
);
1413 DPRINTF("Control condition failed\n");
1419 if ((insn
& (1 << 29)) == 0) {
1422 /* ??? The docs imply the destination address is loaded into
1423 the TEMP register. However the Linux drivers rely on
1424 the value being presrved. */
1425 dest
= read_dword(s
, s
->dsp
);
1427 lsi_memcpy(s
, dest
, addr
, insn
& 0xffffff);
1434 if (insn
& (1 << 28)) {
1435 addr
= s
->dsa
+ sextract32(addr
, 0, 24);
1438 reg
= (insn
>> 16) & 0xff;
1439 if (insn
& (1 << 24)) {
1440 pci_dma_read(pci_dev
, addr
, data
, n
);
1441 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg
, n
,
1442 addr
, *(int *)data
);
1443 for (i
= 0; i
< n
; i
++) {
1444 lsi_reg_writeb(s
, reg
+ i
, data
[i
]);
1447 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg
, n
, addr
);
1448 for (i
= 0; i
< n
; i
++) {
1449 data
[i
] = lsi_reg_readb(s
, reg
+ i
);
1451 pci_dma_write(pci_dev
, addr
, data
, n
);
1455 if (insn_processed
> 10000 && !s
->waiting
) {
1456 /* Some windows drivers make the device spin waiting for a memory
1457 location to change. If we have been executed a lot of code then
1458 assume this is the case and force an unexpected device disconnect.
1459 This is apparently sufficient to beat the drivers into submission.
1461 if (!(s
->sien0
& LSI_SIST0_UDC
))
1462 fprintf(stderr
, "inf. loop with UDC masked\n");
1463 lsi_script_scsi_interrupt(s
, LSI_SIST0_UDC
, 0);
1465 } else if (s
->istat1
& LSI_ISTAT1_SRUN
&& !s
->waiting
) {
1466 if (s
->dcntl
& LSI_DCNTL_SSM
) {
1467 lsi_script_dma_interrupt(s
, LSI_DSTAT_SSI
);
1472 DPRINTF("SCRIPTS execution stopped\n");
1475 static uint8_t lsi_reg_readb(LSIState
*s
, int offset
)
1478 #define CASE_GET_REG24(name, addr) \
1479 case addr: return s->name & 0xff; \
1480 case addr + 1: return (s->name >> 8) & 0xff; \
1481 case addr + 2: return (s->name >> 16) & 0xff;
1483 #define CASE_GET_REG32(name, addr) \
1484 case addr: return s->name & 0xff; \
1485 case addr + 1: return (s->name >> 8) & 0xff; \
1486 case addr + 2: return (s->name >> 16) & 0xff; \
1487 case addr + 3: return (s->name >> 24) & 0xff;
1489 #ifdef DEBUG_LSI_REG
1490 DPRINTF("Read reg %x\n", offset
);
1493 case 0x00: /* SCNTL0 */
1495 case 0x01: /* SCNTL1 */
1497 case 0x02: /* SCNTL2 */
1499 case 0x03: /* SCNTL3 */
1501 case 0x04: /* SCID */
1503 case 0x05: /* SXFER */
1505 case 0x06: /* SDID */
1507 case 0x07: /* GPREG0 */
1509 case 0x08: /* Revision ID */
1511 case 0xa: /* SSID */
1513 case 0xb: /* SBCL */
1514 /* ??? This is not correct. However it's (hopefully) only
1515 used for diagnostics, so should be ok. */
1517 case 0xc: /* DSTAT */
1518 tmp
= s
->dstat
| LSI_DSTAT_DFE
;
1519 if ((s
->istat0
& LSI_ISTAT0_INTF
) == 0)
1523 case 0x0d: /* SSTAT0 */
1525 case 0x0e: /* SSTAT1 */
1527 case 0x0f: /* SSTAT2 */
1528 return s
->scntl1
& LSI_SCNTL1_CON
? 0 : 2;
1529 CASE_GET_REG32(dsa
, 0x10)
1530 case 0x14: /* ISTAT0 */
1532 case 0x15: /* ISTAT1 */
1534 case 0x16: /* MBOX0 */
1536 case 0x17: /* MBOX1 */
1538 case 0x18: /* CTEST0 */
1540 case 0x19: /* CTEST1 */
1542 case 0x1a: /* CTEST2 */
1543 tmp
= s
->ctest2
| LSI_CTEST2_DACK
| LSI_CTEST2_CM
;
1544 if (s
->istat0
& LSI_ISTAT0_SIGP
) {
1545 s
->istat0
&= ~LSI_ISTAT0_SIGP
;
1546 tmp
|= LSI_CTEST2_SIGP
;
1549 case 0x1b: /* CTEST3 */
1551 CASE_GET_REG32(temp
, 0x1c)
1552 case 0x20: /* DFIFO */
1554 case 0x21: /* CTEST4 */
1556 case 0x22: /* CTEST5 */
1558 case 0x23: /* CTEST6 */
1560 CASE_GET_REG24(dbc
, 0x24)
1561 case 0x27: /* DCMD */
1563 CASE_GET_REG32(dnad
, 0x28)
1564 CASE_GET_REG32(dsp
, 0x2c)
1565 CASE_GET_REG32(dsps
, 0x30)
1566 CASE_GET_REG32(scratch
[0], 0x34)
1567 case 0x38: /* DMODE */
1569 case 0x39: /* DIEN */
1571 case 0x3a: /* SBR */
1573 case 0x3b: /* DCNTL */
1575 case 0x40: /* SIEN0 */
1577 case 0x41: /* SIEN1 */
1579 case 0x42: /* SIST0 */
1584 case 0x43: /* SIST1 */
1589 case 0x46: /* MACNTL */
1591 case 0x47: /* GPCNTL0 */
1593 case 0x48: /* STIME0 */
1595 case 0x4a: /* RESPID0 */
1597 case 0x4b: /* RESPID1 */
1599 case 0x4d: /* STEST1 */
1601 case 0x4e: /* STEST2 */
1603 case 0x4f: /* STEST3 */
1605 case 0x50: /* SIDL */
1606 /* This is needed by the linux drivers. We currently only update it
1607 during the MSG IN phase. */
1609 case 0x52: /* STEST4 */
1611 case 0x56: /* CCNTL0 */
1613 case 0x57: /* CCNTL1 */
1615 case 0x58: /* SBDL */
1616 /* Some drivers peek at the data bus during the MSG IN phase. */
1617 if ((s
->sstat1
& PHASE_MASK
) == PHASE_MI
)
1620 case 0x59: /* SBDL high */
1622 CASE_GET_REG32(mmrs
, 0xa0)
1623 CASE_GET_REG32(mmws
, 0xa4)
1624 CASE_GET_REG32(sfs
, 0xa8)
1625 CASE_GET_REG32(drs
, 0xac)
1626 CASE_GET_REG32(sbms
, 0xb0)
1627 CASE_GET_REG32(dbms
, 0xb4)
1628 CASE_GET_REG32(dnad64
, 0xb8)
1629 CASE_GET_REG32(pmjad1
, 0xc0)
1630 CASE_GET_REG32(pmjad2
, 0xc4)
1631 CASE_GET_REG32(rbc
, 0xc8)
1632 CASE_GET_REG32(ua
, 0xcc)
1633 CASE_GET_REG32(ia
, 0xd4)
1634 CASE_GET_REG32(sbc
, 0xd8)
1635 CASE_GET_REG32(csbc
, 0xdc)
1637 if (offset
>= 0x5c && offset
< 0xa0) {
1640 n
= (offset
- 0x58) >> 2;
1641 shift
= (offset
& 3) * 8;
1642 return (s
->scratch
[n
] >> shift
) & 0xff;
1644 BADF("readb 0x%x\n", offset
);
1646 #undef CASE_GET_REG24
1647 #undef CASE_GET_REG32
1650 static void lsi_reg_writeb(LSIState
*s
, int offset
, uint8_t val
)
1652 #define CASE_SET_REG24(name, addr) \
1653 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1654 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1655 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break;
1657 #define CASE_SET_REG32(name, addr) \
1658 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1659 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1660 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1661 case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1663 #ifdef DEBUG_LSI_REG
1664 DPRINTF("Write reg %x = %02x\n", offset
, val
);
1667 case 0x00: /* SCNTL0 */
1669 if (val
& LSI_SCNTL0_START
) {
1670 BADF("Start sequence not implemented\n");
1673 case 0x01: /* SCNTL1 */
1674 s
->scntl1
= val
& ~LSI_SCNTL1_SST
;
1675 if (val
& LSI_SCNTL1_IARB
) {
1676 BADF("Immediate Arbritration not implemented\n");
1678 if (val
& LSI_SCNTL1_RST
) {
1679 if (!(s
->sstat0
& LSI_SSTAT0_RST
)) {
1680 qbus_reset_all(&s
->bus
.qbus
);
1681 s
->sstat0
|= LSI_SSTAT0_RST
;
1682 lsi_script_scsi_interrupt(s
, LSI_SIST0_RST
, 0);
1685 s
->sstat0
&= ~LSI_SSTAT0_RST
;
1688 case 0x02: /* SCNTL2 */
1689 val
&= ~(LSI_SCNTL2_WSR
| LSI_SCNTL2_WSS
);
1692 case 0x03: /* SCNTL3 */
1695 case 0x04: /* SCID */
1698 case 0x05: /* SXFER */
1701 case 0x06: /* SDID */
1702 if ((s
->ssid
& 0x80) && (val
& 0xf) != (s
->ssid
& 0xf)) {
1703 BADF("Destination ID does not match SSID\n");
1705 s
->sdid
= val
& 0xf;
1707 case 0x07: /* GPREG0 */
1709 case 0x08: /* SFBR */
1710 /* The CPU is not allowed to write to this register. However the
1711 SCRIPTS register move instructions are. */
1714 case 0x0a: case 0x0b:
1715 /* Openserver writes to these readonly registers on startup */
1717 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1718 /* Linux writes to these readonly registers on startup. */
1720 CASE_SET_REG32(dsa
, 0x10)
1721 case 0x14: /* ISTAT0 */
1722 s
->istat0
= (s
->istat0
& 0x0f) | (val
& 0xf0);
1723 if (val
& LSI_ISTAT0_ABRT
) {
1724 lsi_script_dma_interrupt(s
, LSI_DSTAT_ABRT
);
1726 if (val
& LSI_ISTAT0_INTF
) {
1727 s
->istat0
&= ~LSI_ISTAT0_INTF
;
1730 if (s
->waiting
== 1 && val
& LSI_ISTAT0_SIGP
) {
1731 DPRINTF("Woken by SIGP\n");
1734 lsi_execute_script(s
);
1736 if (val
& LSI_ISTAT0_SRST
) {
1737 qdev_reset_all(DEVICE(s
));
1740 case 0x16: /* MBOX0 */
1743 case 0x17: /* MBOX1 */
1746 case 0x18: /* CTEST0 */
1749 case 0x1a: /* CTEST2 */
1750 s
->ctest2
= val
& LSI_CTEST2_PCICIE
;
1752 case 0x1b: /* CTEST3 */
1753 s
->ctest3
= val
& 0x0f;
1755 CASE_SET_REG32(temp
, 0x1c)
1756 case 0x21: /* CTEST4 */
1758 BADF("Unimplemented CTEST4-FBL 0x%x\n", val
);
1762 case 0x22: /* CTEST5 */
1763 if (val
& (LSI_CTEST5_ADCK
| LSI_CTEST5_BBCK
)) {
1764 BADF("CTEST5 DMA increment not implemented\n");
1768 CASE_SET_REG24(dbc
, 0x24)
1769 CASE_SET_REG32(dnad
, 0x28)
1770 case 0x2c: /* DSP[0:7] */
1771 s
->dsp
&= 0xffffff00;
1774 case 0x2d: /* DSP[8:15] */
1775 s
->dsp
&= 0xffff00ff;
1778 case 0x2e: /* DSP[16:23] */
1779 s
->dsp
&= 0xff00ffff;
1780 s
->dsp
|= val
<< 16;
1782 case 0x2f: /* DSP[24:31] */
1783 s
->dsp
&= 0x00ffffff;
1784 s
->dsp
|= val
<< 24;
1785 if ((s
->dmode
& LSI_DMODE_MAN
) == 0
1786 && (s
->istat1
& LSI_ISTAT1_SRUN
) == 0)
1787 lsi_execute_script(s
);
1789 CASE_SET_REG32(dsps
, 0x30)
1790 CASE_SET_REG32(scratch
[0], 0x34)
1791 case 0x38: /* DMODE */
1792 if (val
& (LSI_DMODE_SIOM
| LSI_DMODE_DIOM
)) {
1793 BADF("IO mappings not implemented\n");
1797 case 0x39: /* DIEN */
1801 case 0x3a: /* SBR */
1804 case 0x3b: /* DCNTL */
1805 s
->dcntl
= val
& ~(LSI_DCNTL_PFF
| LSI_DCNTL_STD
);
1806 if ((val
& LSI_DCNTL_STD
) && (s
->istat1
& LSI_ISTAT1_SRUN
) == 0)
1807 lsi_execute_script(s
);
1809 case 0x40: /* SIEN0 */
1813 case 0x41: /* SIEN1 */
1817 case 0x47: /* GPCNTL0 */
1819 case 0x48: /* STIME0 */
1822 case 0x49: /* STIME1 */
1824 DPRINTF("General purpose timer not implemented\n");
1825 /* ??? Raising the interrupt immediately seems to be sufficient
1826 to keep the FreeBSD driver happy. */
1827 lsi_script_scsi_interrupt(s
, 0, LSI_SIST1_GEN
);
1830 case 0x4a: /* RESPID0 */
1833 case 0x4b: /* RESPID1 */
1836 case 0x4d: /* STEST1 */
1839 case 0x4e: /* STEST2 */
1841 BADF("Low level mode not implemented\n");
1845 case 0x4f: /* STEST3 */
1847 BADF("SCSI FIFO test mode not implemented\n");
1851 case 0x56: /* CCNTL0 */
1854 case 0x57: /* CCNTL1 */
1857 CASE_SET_REG32(mmrs
, 0xa0)
1858 CASE_SET_REG32(mmws
, 0xa4)
1859 CASE_SET_REG32(sfs
, 0xa8)
1860 CASE_SET_REG32(drs
, 0xac)
1861 CASE_SET_REG32(sbms
, 0xb0)
1862 CASE_SET_REG32(dbms
, 0xb4)
1863 CASE_SET_REG32(dnad64
, 0xb8)
1864 CASE_SET_REG32(pmjad1
, 0xc0)
1865 CASE_SET_REG32(pmjad2
, 0xc4)
1866 CASE_SET_REG32(rbc
, 0xc8)
1867 CASE_SET_REG32(ua
, 0xcc)
1868 CASE_SET_REG32(ia
, 0xd4)
1869 CASE_SET_REG32(sbc
, 0xd8)
1870 CASE_SET_REG32(csbc
, 0xdc)
1872 if (offset
>= 0x5c && offset
< 0xa0) {
1875 n
= (offset
- 0x58) >> 2;
1876 shift
= (offset
& 3) * 8;
1877 s
->scratch
[n
] = deposit32(s
->scratch
[n
], shift
, 8, val
);
1879 BADF("Unhandled writeb 0x%x = 0x%x\n", offset
, val
);
1882 #undef CASE_SET_REG24
1883 #undef CASE_SET_REG32
1886 static void lsi_mmio_write(void *opaque
, hwaddr addr
,
1887 uint64_t val
, unsigned size
)
1889 LSIState
*s
= opaque
;
1891 lsi_reg_writeb(s
, addr
& 0xff, val
);
1894 static uint64_t lsi_mmio_read(void *opaque
, hwaddr addr
,
1897 LSIState
*s
= opaque
;
1899 return lsi_reg_readb(s
, addr
& 0xff);
1902 static const MemoryRegionOps lsi_mmio_ops
= {
1903 .read
= lsi_mmio_read
,
1904 .write
= lsi_mmio_write
,
1905 .endianness
= DEVICE_NATIVE_ENDIAN
,
1907 .min_access_size
= 1,
1908 .max_access_size
= 1,
1912 static void lsi_ram_write(void *opaque
, hwaddr addr
,
1913 uint64_t val
, unsigned size
)
1915 LSIState
*s
= opaque
;
1920 newval
= s
->script_ram
[addr
>> 2];
1921 shift
= (addr
& 3) * 8;
1922 mask
= ((uint64_t)1 << (size
* 8)) - 1;
1923 newval
&= ~(mask
<< shift
);
1924 newval
|= val
<< shift
;
1925 s
->script_ram
[addr
>> 2] = newval
;
1928 static uint64_t lsi_ram_read(void *opaque
, hwaddr addr
,
1931 LSIState
*s
= opaque
;
1935 val
= s
->script_ram
[addr
>> 2];
1936 mask
= ((uint64_t)1 << (size
* 8)) - 1;
1937 val
>>= (addr
& 3) * 8;
1941 static const MemoryRegionOps lsi_ram_ops
= {
1942 .read
= lsi_ram_read
,
1943 .write
= lsi_ram_write
,
1944 .endianness
= DEVICE_NATIVE_ENDIAN
,
1947 static uint64_t lsi_io_read(void *opaque
, hwaddr addr
,
1950 LSIState
*s
= opaque
;
1951 return lsi_reg_readb(s
, addr
& 0xff);
1954 static void lsi_io_write(void *opaque
, hwaddr addr
,
1955 uint64_t val
, unsigned size
)
1957 LSIState
*s
= opaque
;
1958 lsi_reg_writeb(s
, addr
& 0xff, val
);
1961 static const MemoryRegionOps lsi_io_ops
= {
1962 .read
= lsi_io_read
,
1963 .write
= lsi_io_write
,
1964 .endianness
= DEVICE_NATIVE_ENDIAN
,
1966 .min_access_size
= 1,
1967 .max_access_size
= 1,
1971 static void lsi_scsi_reset(DeviceState
*dev
)
1973 LSIState
*s
= LSI53C895A(dev
);
1978 static void lsi_pre_save(void *opaque
)
1980 LSIState
*s
= opaque
;
1983 assert(s
->current
->dma_buf
== NULL
);
1984 assert(s
->current
->dma_len
== 0);
1986 assert(QTAILQ_EMPTY(&s
->queue
));
1989 static const VMStateDescription vmstate_lsi_scsi
= {
1992 .minimum_version_id
= 0,
1993 .minimum_version_id_old
= 0,
1994 .pre_save
= lsi_pre_save
,
1995 .fields
= (VMStateField
[]) {
1996 VMSTATE_PCI_DEVICE(parent_obj
, LSIState
),
1998 VMSTATE_INT32(carry
, LSIState
),
1999 VMSTATE_INT32(status
, LSIState
),
2000 VMSTATE_INT32(msg_action
, LSIState
),
2001 VMSTATE_INT32(msg_len
, LSIState
),
2002 VMSTATE_BUFFER(msg
, LSIState
),
2003 VMSTATE_INT32(waiting
, LSIState
),
2005 VMSTATE_UINT32(dsa
, LSIState
),
2006 VMSTATE_UINT32(temp
, LSIState
),
2007 VMSTATE_UINT32(dnad
, LSIState
),
2008 VMSTATE_UINT32(dbc
, LSIState
),
2009 VMSTATE_UINT8(istat0
, LSIState
),
2010 VMSTATE_UINT8(istat1
, LSIState
),
2011 VMSTATE_UINT8(dcmd
, LSIState
),
2012 VMSTATE_UINT8(dstat
, LSIState
),
2013 VMSTATE_UINT8(dien
, LSIState
),
2014 VMSTATE_UINT8(sist0
, LSIState
),
2015 VMSTATE_UINT8(sist1
, LSIState
),
2016 VMSTATE_UINT8(sien0
, LSIState
),
2017 VMSTATE_UINT8(sien1
, LSIState
),
2018 VMSTATE_UINT8(mbox0
, LSIState
),
2019 VMSTATE_UINT8(mbox1
, LSIState
),
2020 VMSTATE_UINT8(dfifo
, LSIState
),
2021 VMSTATE_UINT8(ctest2
, LSIState
),
2022 VMSTATE_UINT8(ctest3
, LSIState
),
2023 VMSTATE_UINT8(ctest4
, LSIState
),
2024 VMSTATE_UINT8(ctest5
, LSIState
),
2025 VMSTATE_UINT8(ccntl0
, LSIState
),
2026 VMSTATE_UINT8(ccntl1
, LSIState
),
2027 VMSTATE_UINT32(dsp
, LSIState
),
2028 VMSTATE_UINT32(dsps
, LSIState
),
2029 VMSTATE_UINT8(dmode
, LSIState
),
2030 VMSTATE_UINT8(dcntl
, LSIState
),
2031 VMSTATE_UINT8(scntl0
, LSIState
),
2032 VMSTATE_UINT8(scntl1
, LSIState
),
2033 VMSTATE_UINT8(scntl2
, LSIState
),
2034 VMSTATE_UINT8(scntl3
, LSIState
),
2035 VMSTATE_UINT8(sstat0
, LSIState
),
2036 VMSTATE_UINT8(sstat1
, LSIState
),
2037 VMSTATE_UINT8(scid
, LSIState
),
2038 VMSTATE_UINT8(sxfer
, LSIState
),
2039 VMSTATE_UINT8(socl
, LSIState
),
2040 VMSTATE_UINT8(sdid
, LSIState
),
2041 VMSTATE_UINT8(ssid
, LSIState
),
2042 VMSTATE_UINT8(sfbr
, LSIState
),
2043 VMSTATE_UINT8(stest1
, LSIState
),
2044 VMSTATE_UINT8(stest2
, LSIState
),
2045 VMSTATE_UINT8(stest3
, LSIState
),
2046 VMSTATE_UINT8(sidl
, LSIState
),
2047 VMSTATE_UINT8(stime0
, LSIState
),
2048 VMSTATE_UINT8(respid0
, LSIState
),
2049 VMSTATE_UINT8(respid1
, LSIState
),
2050 VMSTATE_UINT32(mmrs
, LSIState
),
2051 VMSTATE_UINT32(mmws
, LSIState
),
2052 VMSTATE_UINT32(sfs
, LSIState
),
2053 VMSTATE_UINT32(drs
, LSIState
),
2054 VMSTATE_UINT32(sbms
, LSIState
),
2055 VMSTATE_UINT32(dbms
, LSIState
),
2056 VMSTATE_UINT32(dnad64
, LSIState
),
2057 VMSTATE_UINT32(pmjad1
, LSIState
),
2058 VMSTATE_UINT32(pmjad2
, LSIState
),
2059 VMSTATE_UINT32(rbc
, LSIState
),
2060 VMSTATE_UINT32(ua
, LSIState
),
2061 VMSTATE_UINT32(ia
, LSIState
),
2062 VMSTATE_UINT32(sbc
, LSIState
),
2063 VMSTATE_UINT32(csbc
, LSIState
),
2064 VMSTATE_BUFFER_UNSAFE(scratch
, LSIState
, 0, 18 * sizeof(uint32_t)),
2065 VMSTATE_UINT8(sbr
, LSIState
),
2067 VMSTATE_BUFFER_UNSAFE(script_ram
, LSIState
, 0, 2048 * sizeof(uint32_t)),
2068 VMSTATE_END_OF_LIST()
2072 static void lsi_scsi_uninit(PCIDevice
*d
)
2074 LSIState
*s
= LSI53C895A(d
);
2076 memory_region_destroy(&s
->mmio_io
);
2077 memory_region_destroy(&s
->ram_io
);
2078 memory_region_destroy(&s
->io_io
);
2081 static const struct SCSIBusInfo lsi_scsi_info
= {
2083 .max_target
= LSI_MAX_DEVS
,
2084 .max_lun
= 0, /* LUN support is buggy */
2086 .transfer_data
= lsi_transfer_data
,
2087 .complete
= lsi_command_complete
,
2088 .cancel
= lsi_request_cancelled
2091 static int lsi_scsi_init(PCIDevice
*dev
)
2093 LSIState
*s
= LSI53C895A(dev
);
2094 DeviceState
*d
= DEVICE(dev
);
2098 pci_conf
= dev
->config
;
2100 /* PCI latency timer = 255 */
2101 pci_conf
[PCI_LATENCY_TIMER
] = 0xff;
2102 /* Interrupt pin A */
2103 pci_conf
[PCI_INTERRUPT_PIN
] = 0x01;
2105 memory_region_init_io(&s
->mmio_io
, OBJECT(s
), &lsi_mmio_ops
, s
,
2107 memory_region_init_io(&s
->ram_io
, OBJECT(s
), &lsi_ram_ops
, s
,
2109 memory_region_init_io(&s
->io_io
, OBJECT(s
), &lsi_io_ops
, s
,
2112 pci_register_bar(dev
, 0, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io_io
);
2113 pci_register_bar(dev
, 1, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->mmio_io
);
2114 pci_register_bar(dev
, 2, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->ram_io
);
2115 QTAILQ_INIT(&s
->queue
);
2117 scsi_bus_new(&s
->bus
, sizeof(s
->bus
), d
, &lsi_scsi_info
, NULL
);
2118 if (!d
->hotplugged
) {
2119 scsi_bus_legacy_handle_cmdline(&s
->bus
, &err
);
2128 static void lsi_class_init(ObjectClass
*klass
, void *data
)
2130 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2131 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2133 k
->init
= lsi_scsi_init
;
2134 k
->exit
= lsi_scsi_uninit
;
2135 k
->vendor_id
= PCI_VENDOR_ID_LSI_LOGIC
;
2136 k
->device_id
= PCI_DEVICE_ID_LSI_53C895A
;
2137 k
->class_id
= PCI_CLASS_STORAGE_SCSI
;
2138 k
->subsystem_id
= 0x1000;
2139 dc
->reset
= lsi_scsi_reset
;
2140 dc
->vmsd
= &vmstate_lsi_scsi
;
2141 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
2144 static const TypeInfo lsi_info
= {
2145 .name
= TYPE_LSI53C895A
,
2146 .parent
= TYPE_PCI_DEVICE
,
2147 .instance_size
= sizeof(LSIState
),
2148 .class_init
= lsi_class_init
,
2151 static void lsi53c895a_register_types(void)
2153 type_register_static(&lsi_info
);
2156 type_init(lsi53c895a_register_types
)