hw/scsi/vmw_pvscsi.c

   1 /*
   2  * QEMU VMWARE PVSCSI paravirtual SCSI bus
   3  *
   4  * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
   5  *
   6  * Developed by Daynix Computing LTD (http://www.daynix.com)
   7  *
   8  * Based on implementation by Paolo Bonzini
   9  * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html
  10  *
  11  * Authors:
  12  * Paolo Bonzini <pbonzini@redhat.com>
  13  * Dmitry Fleytman <dmitry@daynix.com>
  14  * Yan Vugenfirer <yan@daynix.com>
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.
  17  * See the COPYING file in the top-level directory.
  18  *
  19  * NOTE about MSI-X:
  20  * MSI-X support has been removed for the moment because it leads Windows OS
  21  * to crash on startup. The crash happens because Windows driver requires
  22  * MSI-X shared memory to be part of the same BAR used for rings state
  23  * registers, etc. This is not supported by QEMU infrastructure so separate
  24  * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs.
  25  *
  26  */
  27
  28 #include "hw/scsi/scsi.h"
  29 #include <block/scsi.h>
  30 #include "hw/pci/msi.h"
  31 #include "vmw_pvscsi.h"
  32 #include "trace.h"
  33
  34
  35 #define PVSCSI_USE_64BIT         (true)
  36 #define PVSCSI_PER_VECTOR_MASK   (false)
  37
  38 #define PVSCSI_MAX_DEVS                   (64)
  39 #define PVSCSI_MSIX_NUM_VECTORS           (1)
  40
  41 #define PVSCSI_MAX_CMD_DATA_WORDS \
  42     (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
  43
  44 #define RS_GET_FIELD(m, field) \
  45     (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
  46                  (m)->rs_pa + offsetof(struct PVSCSIRingsState, field)))
  47 #define RS_SET_FIELD(m, field, val) \
  48     (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
  49                  (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), val))
  50
  51 typedef struct PVSCSIClass {
  52     PCIDeviceClass parent_class;
  53     DeviceRealize parent_dc_realize;
  54 } PVSCSIClass;
  55
  56 #define TYPE_PVSCSI "pvscsi"
  57 #define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI)
  58
  59 #define PVSCSI_DEVICE_CLASS(klass) \
  60     OBJECT_CLASS_CHECK(PVSCSIClass, (klass), TYPE_PVSCSI)
  61 #define PVSCSI_DEVICE_GET_CLASS(obj) \
  62     OBJECT_GET_CLASS(PVSCSIClass, (obj), TYPE_PVSCSI)
  63
  64 /* Compatability flags for migration */
  65 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0
  66 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \
  67     (1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT)
  68 #define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1
  69 #define PVSCSI_COMPAT_DISABLE_PCIE \
  70     (1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT)
  71
  72 #define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \
  73     ((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION)
  74 #define PVSCSI_MSI_OFFSET(s) \
  75     (PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c)
  76 #define PVSCSI_EXP_EP_OFFSET (0x40)
  77
  78 typedef struct PVSCSIRingInfo {
  79     uint64_t            rs_pa;
  80     uint32_t            txr_len_mask;
  81     uint32_t            rxr_len_mask;
  82     uint32_t            msg_len_mask;
  83     uint64_t            req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
  84     uint64_t            cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
  85     uint64_t            msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES];
  86     uint64_t            consumed_ptr;
  87     uint64_t            filled_cmp_ptr;
  88     uint64_t            filled_msg_ptr;
  89 } PVSCSIRingInfo;
  90
  91 typedef struct PVSCSISGState {
  92     hwaddr elemAddr;
  93     hwaddr dataAddr;
  94     uint32_t resid;
  95 } PVSCSISGState;
  96
  97 typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList;
  98
  99 typedef struct {
 100     PCIDevice parent_obj;
 101     MemoryRegion io_space;
 102     SCSIBus bus;
 103     QEMUBH *completion_worker;
 104     PVSCSIRequestList pending_queue;
 105     PVSCSIRequestList completion_queue;
 106
 107     uint64_t reg_interrupt_status;        /* Interrupt status register value */
 108     uint64_t reg_interrupt_enabled;       /* Interrupt mask register value   */
 109     uint64_t reg_command_status;          /* Command status register value   */
 110
 111     /* Command data adoption mechanism */
 112     uint64_t curr_cmd;                   /* Last command arrived             */
 113     uint32_t curr_cmd_data_cntr;         /* Amount of data for last command  */
 114
 115     /* Collector for current command data */
 116     uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS];
 117
 118     uint8_t rings_info_valid;            /* Whether data rings initialized   */
 119     uint8_t msg_ring_info_valid;         /* Whether message ring initialized */
 120     uint8_t use_msg;                     /* Whether to use message ring      */
 121
 122     uint8_t msi_used;    /* Whether MSI support was installed successfully   */
 123
 124     PVSCSIRingInfo rings;                /* Data transfer rings manager      */
 125     uint32_t resetting;                  /* Reset in progress                */
 126
 127     uint32_t compat_flags;
 128 } PVSCSIState;
 129
 130 typedef struct PVSCSIRequest {
 131     SCSIRequest *sreq;
 132     PVSCSIState *dev;
 133     uint8_t sense_key;
 134     uint8_t completed;
 135     int lun;
 136     QEMUSGList sgl;
 137     PVSCSISGState sg;
 138     struct PVSCSIRingReqDesc req;
 139     struct PVSCSIRingCmpDesc cmp;
 140     QTAILQ_ENTRY(PVSCSIRequest) next;
 141 } PVSCSIRequest;
 142
 143 /* Integer binary logarithm */
 144 static int
 145 pvscsi_log2(uint32_t input)
 146 {
 147     int log = 0;
 148     assert(input > 0);
 149     while (input >> ++log) {
 150     }
 151     return log;
 152 }
 153
 154 static void
 155 pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri)
 156 {
 157     int i;
 158     uint32_t txr_len_log2, rxr_len_log2;
 159     uint32_t req_ring_size, cmp_ring_size;
 160     m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT;
 161
 162     req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 163     cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
 164     txr_len_log2 = pvscsi_log2(req_ring_size - 1);
 165     rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);
 166
 167     m->txr_len_mask = MASK(txr_len_log2);
 168     m->rxr_len_mask = MASK(rxr_len_log2);
 169
 170     m->consumed_ptr = 0;
 171     m->filled_cmp_ptr = 0;
 172
 173     for (i = 0; i < ri->reqRingNumPages; i++) {
 174         m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT;
 175     }
 176
 177     for (i = 0; i < ri->cmpRingNumPages; i++) {
 178         m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT;
 179     }
 180
 181     RS_SET_FIELD(m, reqProdIdx, 0);
 182     RS_SET_FIELD(m, reqConsIdx, 0);
 183     RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2);
 184
 185     RS_SET_FIELD(m, cmpProdIdx, 0);
 186     RS_SET_FIELD(m, cmpConsIdx, 0);
 187     RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2);
 188
 189     trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);
 190
 191     /* Flush ring state page changes */
 192     smp_wmb();
 193 }
 194
 195 static void
 196 pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri)
 197 {
 198     int i;
 199     uint32_t len_log2;
 200     uint32_t ring_size;
 201
 202     ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
 203     len_log2 = pvscsi_log2(ring_size - 1);
 204
 205     m->msg_len_mask = MASK(len_log2);
 206
 207     m->filled_msg_ptr = 0;
 208
 209     for (i = 0; i < ri->numPages; i++) {
 210         m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT;
 211     }
 212
 213     RS_SET_FIELD(m, msgProdIdx, 0);
 214     RS_SET_FIELD(m, msgConsIdx, 0);
 215     RS_SET_FIELD(m, msgNumEntriesLog2, len_log2);
 216
 217     trace_pvscsi_ring_init_msg(len_log2);
 218
 219     /* Flush ring state page changes */
 220     smp_wmb();
 221 }
 222
 223 static void
 224 pvscsi_ring_cleanup(PVSCSIRingInfo *mgr)
 225 {
 226     mgr->rs_pa = 0;
 227     mgr->txr_len_mask = 0;
 228     mgr->rxr_len_mask = 0;
 229     mgr->msg_len_mask = 0;
 230     mgr->consumed_ptr = 0;
 231     mgr->filled_cmp_ptr = 0;
 232     mgr->filled_msg_ptr = 0;
 233     memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa));
 234     memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa));
 235     memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa));
 236 }
 237
 238 static hwaddr
 239 pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr)
 240 {
 241     uint32_t ready_ptr = RS_GET_FIELD(mgr, reqProdIdx);
 242
 243     if (ready_ptr != mgr->consumed_ptr) {
 244         uint32_t next_ready_ptr =
 245             mgr->consumed_ptr++ & mgr->txr_len_mask;
 246         uint32_t next_ready_page =
 247             next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 248         uint32_t inpage_idx =
 249             next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 250
 251         return mgr->req_ring_pages_pa[next_ready_page] +
 252                inpage_idx * sizeof(PVSCSIRingReqDesc);
 253     } else {
 254         return 0;
 255     }
 256 }
 257
 258 static void
 259 pvscsi_ring_flush_req(PVSCSIRingInfo *mgr)
 260 {
 261     RS_SET_FIELD(mgr, reqConsIdx, mgr->consumed_ptr);
 262 }
 263
 264 static hwaddr
 265 pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr)
 266 {
 267     /*
 268      * According to Linux driver code it explicitly verifies that number
 269      * of requests being processed by device is less then the size of
 270      * completion queue, so device may omit completion queue overflow
 271      * conditions check. We assume that this is true for other (Windows)
 272      * drivers as well.
 273      */
 274
 275     uint32_t free_cmp_ptr =
 276         mgr->filled_cmp_ptr++ & mgr->rxr_len_mask;
 277     uint32_t free_cmp_page =
 278         free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
 279     uint32_t inpage_idx =
 280         free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
 281     return mgr->cmp_ring_pages_pa[free_cmp_page] +
 282            inpage_idx * sizeof(PVSCSIRingCmpDesc);
 283 }
 284
 285 static hwaddr
 286 pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr)
 287 {
 288     uint32_t free_msg_ptr =
 289         mgr->filled_msg_ptr++ & mgr->msg_len_mask;
 290     uint32_t free_msg_page =
 291         free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
 292     uint32_t inpage_idx =
 293         free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
 294     return mgr->msg_ring_pages_pa[free_msg_page] +
 295            inpage_idx * sizeof(PVSCSIRingMsgDesc);
 296 }
 297
 298 static void
 299 pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr)
 300 {
 301     /* Flush descriptor changes */
 302     smp_wmb();
 303
 304     trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr);
 305
 306     RS_SET_FIELD(mgr, cmpProdIdx, mgr->filled_cmp_ptr);
 307 }
 308
 309 static bool
 310 pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr)
 311 {
 312     uint32_t prodIdx = RS_GET_FIELD(mgr, msgProdIdx);
 313     uint32_t consIdx = RS_GET_FIELD(mgr, msgConsIdx);
 314
 315     return (prodIdx - consIdx) < (mgr->msg_len_mask + 1);
 316 }
 317
 318 static void
 319 pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr)
 320 {
 321     /* Flush descriptor changes */
 322     smp_wmb();
 323
 324     trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr);
 325
 326     RS_SET_FIELD(mgr, msgProdIdx, mgr->filled_msg_ptr);
 327 }
 328
 329 static void
 330 pvscsi_reset_state(PVSCSIState *s)
 331 {
 332     s->curr_cmd = PVSCSI_CMD_FIRST;
 333     s->curr_cmd_data_cntr = 0;
 334     s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 335     s->reg_interrupt_status = 0;
 336     pvscsi_ring_cleanup(&s->rings);
 337     s->rings_info_valid = FALSE;
 338     s->msg_ring_info_valid = FALSE;
 339     QTAILQ_INIT(&s->pending_queue);
 340     QTAILQ_INIT(&s->completion_queue);
 341 }
 342
 343 static void
 344 pvscsi_update_irq_status(PVSCSIState *s)
 345 {
 346     PCIDevice *d = PCI_DEVICE(s);
 347     bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status;
 348
 349     trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled,
 350                                   s->reg_interrupt_status);
 351
 352     if (s->msi_used && msi_enabled(d)) {
 353         if (should_raise) {
 354             trace_pvscsi_update_irq_msi();
 355             msi_notify(d, PVSCSI_VECTOR_COMPLETION);
 356         }
 357         return;
 358     }
 359
 360     pci_set_irq(d, !!should_raise);
 361 }
 362
 363 static void
 364 pvscsi_raise_completion_interrupt(PVSCSIState *s)
 365 {
 366     s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0;
 367
 368     /* Memory barrier to flush interrupt status register changes*/
 369     smp_wmb();
 370
 371     pvscsi_update_irq_status(s);
 372 }
 373
 374 static void
 375 pvscsi_raise_message_interrupt(PVSCSIState *s)
 376 {
 377     s->reg_interrupt_status |= PVSCSI_INTR_MSG_0;
 378
 379     /* Memory barrier to flush interrupt status register changes*/
 380     smp_wmb();
 381
 382     pvscsi_update_irq_status(s);
 383 }
 384
 385 static void
 386 pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc)
 387 {
 388     hwaddr cmp_descr_pa;
 389
 390     cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings);
 391     trace_pvscsi_cmp_ring_put(cmp_descr_pa);
 392     cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc,
 393                               sizeof(*cmp_desc));
 394 }
 395
 396 static void
 397 pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc)
 398 {
 399     hwaddr msg_descr_pa;
 400
 401     msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings);
 402     trace_pvscsi_msg_ring_put(msg_descr_pa);
 403     cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc,
 404                               sizeof(*msg_desc));
 405 }
 406
 407 static void
 408 pvscsi_process_completion_queue(void *opaque)
 409 {
 410     PVSCSIState *s = opaque;
 411     PVSCSIRequest *pvscsi_req;
 412     bool has_completed = false;
 413
 414     while (!QTAILQ_EMPTY(&s->completion_queue)) {
 415         pvscsi_req = QTAILQ_FIRST(&s->completion_queue);
 416         QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next);
 417         pvscsi_cmp_ring_put(s, &pvscsi_req->cmp);
 418         g_free(pvscsi_req);
 419         has_completed = true;
 420     }
 421
 422     if (has_completed) {
 423         pvscsi_ring_flush_cmp(&s->rings);
 424         pvscsi_raise_completion_interrupt(s);
 425     }
 426 }
 427
 428 static void
 429 pvscsi_reset_adapter(PVSCSIState *s)
 430 {
 431     s->resetting++;
 432     qbus_reset_all_fn(&s->bus);
 433     s->resetting--;
 434     pvscsi_process_completion_queue(s);
 435     assert(QTAILQ_EMPTY(&s->pending_queue));
 436     pvscsi_reset_state(s);
 437 }
 438
 439 static void
 440 pvscsi_schedule_completion_processing(PVSCSIState *s)
 441 {
 442     /* Try putting more complete requests on the ring. */
 443     if (!QTAILQ_EMPTY(&s->completion_queue)) {
 444         qemu_bh_schedule(s->completion_worker);
 445     }
 446 }
 447
 448 static void
 449 pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r)
 450 {
 451     assert(!r->completed);
 452
 453     trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen,
 454                                   r->sense_key);
 455     if (r->sreq != NULL) {
 456         scsi_req_unref(r->sreq);
 457         r->sreq = NULL;
 458     }
 459     r->completed = 1;
 460     QTAILQ_REMOVE(&s->pending_queue, r, next);
 461     QTAILQ_INSERT_TAIL(&s->completion_queue, r, next);
 462     pvscsi_schedule_completion_processing(s);
 463 }
 464
 465 static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r)
 466 {
 467     PVSCSIRequest *req = r->hba_private;
 468
 469     trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size);
 470
 471     return &req->sgl;
 472 }
 473
 474 static void
 475 pvscsi_get_next_sg_elem(PVSCSISGState *sg)
 476 {
 477     struct PVSCSISGElement elem;
 478
 479     cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem));
 480     if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) {
 481         /*
 482             * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in
 483             * header file but its value is unknown. This flag requires
 484             * additional processing, so we put warning here to catch it
 485             * some day and make proper implementation
 486             */
 487         trace_pvscsi_get_next_sg_elem(elem.flags);
 488     }
 489
 490     sg->elemAddr += sizeof(elem);
 491     sg->dataAddr = elem.addr;
 492     sg->resid = elem.length;
 493 }
 494
 495 static void
 496 pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len)
 497 {
 498     r->cmp.senseLen = MIN(r->req.senseLen, len);
 499     r->sense_key = sense[(sense[0] & 2) ? 1 : 2];
 500     cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen);
 501 }
 502
 503 static void
 504 pvscsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid)
 505 {
 506     PVSCSIRequest *pvscsi_req = req->hba_private;
 507     PVSCSIState *s;
 508
 509     if (!pvscsi_req) {
 510         trace_pvscsi_command_complete_not_found(req->tag);
 511         return;
 512     }
 513     s = pvscsi_req->dev;
 514
 515     if (resid) {
 516         /* Short transfer.  */
 517         trace_pvscsi_command_complete_data_run();
 518         pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN;
 519     }
 520
 521     pvscsi_req->cmp.scsiStatus = status;
 522     if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) {
 523         uint8_t sense[SCSI_SENSE_BUF_SIZE];
 524         int sense_len =
 525             scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense));
 526
 527         trace_pvscsi_command_complete_sense_len(sense_len);
 528         pvscsi_write_sense(pvscsi_req, sense, sense_len);
 529     }
 530     qemu_sglist_destroy(&pvscsi_req->sgl);
 531     pvscsi_complete_request(s, pvscsi_req);
 532 }
 533
 534 static void
 535 pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type)
 536 {
 537     if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) {
 538         PVSCSIMsgDescDevStatusChanged msg = {0};
 539
 540         msg.type = msg_type;
 541         msg.bus = dev->channel;
 542         msg.target = dev->id;
 543         msg.lun[1] = dev->lun;
 544
 545         pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg);
 546         pvscsi_ring_flush_msg(&s->rings);
 547         pvscsi_raise_message_interrupt(s);
 548     }
 549 }
 550
 551 static void
 552 pvscsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
 553 {
 554     PVSCSIState *s = PVSCSI(hotplug_dev);
 555
 556     pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_ADDED);
 557 }
 558
 559 static void
 560 pvscsi_hot_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
 561 {
 562     PVSCSIState *s = PVSCSI(hotplug_dev);
 563
 564     pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_REMOVED);
 565     qdev_simple_device_unplug_cb(hotplug_dev, dev, errp);
 566 }
 567
 568 static void
 569 pvscsi_request_cancelled(SCSIRequest *req)
 570 {
 571     PVSCSIRequest *pvscsi_req = req->hba_private;
 572     PVSCSIState *s = pvscsi_req->dev;
 573
 574     if (pvscsi_req->completed) {
 575         return;
 576     }
 577
 578    if (pvscsi_req->dev->resetting) {
 579        pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET;
 580     } else {
 581        pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE;
 582     }
 583
 584     pvscsi_complete_request(s, pvscsi_req);
 585 }
 586
 587 static SCSIDevice*
 588 pvscsi_device_find(PVSCSIState *s, int channel, int target,
 589                    uint8_t *requested_lun, uint8_t *target_lun)
 590 {
 591     if (requested_lun[0] || requested_lun[2] || requested_lun[3] ||
 592         requested_lun[4] || requested_lun[5] || requested_lun[6] ||
 593         requested_lun[7] || (target > PVSCSI_MAX_DEVS)) {
 594         return NULL;
 595     } else {
 596         *target_lun = requested_lun[1];
 597         return scsi_device_find(&s->bus, channel, target, *target_lun);
 598     }
 599 }
 600
 601 static PVSCSIRequest *
 602 pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d,
 603                                 struct PVSCSIRingReqDesc *descr)
 604 {
 605     PVSCSIRequest *pvscsi_req;
 606     uint8_t lun;
 607
 608     pvscsi_req = g_malloc0(sizeof(*pvscsi_req));
 609     pvscsi_req->dev = s;
 610     pvscsi_req->req = *descr;
 611     pvscsi_req->cmp.context = pvscsi_req->req.context;
 612     QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next);
 613
 614     *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun);
 615     if (*d) {
 616         pvscsi_req->lun = lun;
 617     }
 618
 619     return pvscsi_req;
 620 }
 621
 622 static void
 623 pvscsi_convert_sglist(PVSCSIRequest *r)
 624 {
 625     int chunk_size;
 626     uint64_t data_length = r->req.dataLen;
 627     PVSCSISGState sg = r->sg;
 628     while (data_length) {
 629         while (!sg.resid) {
 630             pvscsi_get_next_sg_elem(&sg);
 631             trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr,
 632                                         r->sg.resid);
 633         }
 634         assert(data_length > 0);
 635         chunk_size = MIN((unsigned) data_length, sg.resid);
 636         if (chunk_size) {
 637             qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size);
 638         }
 639
 640         sg.dataAddr += chunk_size;
 641         data_length -= chunk_size;
 642         sg.resid -= chunk_size;
 643     }
 644 }
 645
 646 static void
 647 pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r)
 648 {
 649     PCIDevice *d = PCI_DEVICE(s);
 650
 651     pci_dma_sglist_init(&r->sgl, d, 1);
 652     if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
 653         pvscsi_convert_sglist(r);
 654     } else {
 655         qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen);
 656     }
 657 }
 658
 659 static void
 660 pvscsi_process_request_descriptor(PVSCSIState *s,
 661                                   struct PVSCSIRingReqDesc *descr)
 662 {
 663     SCSIDevice *d;
 664     PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr);
 665     int64_t n;
 666
 667     trace_pvscsi_process_req_descr(descr->cdb[0], descr->context);
 668
 669     if (!d) {
 670         r->cmp.hostStatus = BTSTAT_SELTIMEO;
 671         trace_pvscsi_process_req_descr_unknown_device();
 672         pvscsi_complete_request(s, r);
 673         return;
 674     }
 675
 676     if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
 677         r->sg.elemAddr = descr->dataAddr;
 678     }
 679
 680     r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r);
 681     if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV &&
 682         (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) {
 683         r->cmp.hostStatus = BTSTAT_BADMSG;
 684         trace_pvscsi_process_req_descr_invalid_dir();
 685         scsi_req_cancel(r->sreq);
 686         return;
 687     }
 688     if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV &&
 689         (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) {
 690         r->cmp.hostStatus = BTSTAT_BADMSG;
 691         trace_pvscsi_process_req_descr_invalid_dir();
 692         scsi_req_cancel(r->sreq);
 693         return;
 694     }
 695
 696     pvscsi_build_sglist(s, r);
 697     n = scsi_req_enqueue(r->sreq);
 698
 699     if (n) {
 700         scsi_req_continue(r->sreq);
 701     }
 702 }
 703
 704 static void
 705 pvscsi_process_io(PVSCSIState *s)
 706 {
 707     PVSCSIRingReqDesc descr;
 708     hwaddr next_descr_pa;
 709
 710     assert(s->rings_info_valid);
 711     while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) {
 712
 713         /* Only read after production index verification */
 714         smp_rmb();
 715
 716         trace_pvscsi_process_io(next_descr_pa);
 717         cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr));
 718         pvscsi_process_request_descriptor(s, &descr);
 719     }
 720
 721     pvscsi_ring_flush_req(&s->rings);
 722 }
 723
 724 static void
 725 pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc)
 726 {
 727     int i;
 728     trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN);
 729
 730     trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages);
 731     for (i = 0; i < rc->reqRingNumPages; i++) {
 732         trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]);
 733     }
 734
 735     trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages);
 736     for (i = 0; i < rc->cmpRingNumPages; i++) {
 737         trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->reqRingPPNs[i]);
 738     }
 739 }
 740
 741 static uint64_t
 742 pvscsi_on_cmd_config(PVSCSIState *s)
 743 {
 744     trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG");
 745     return PVSCSI_COMMAND_PROCESSING_FAILED;
 746 }
 747
 748 static uint64_t
 749 pvscsi_on_cmd_unplug(PVSCSIState *s)
 750 {
 751     trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG");
 752     return PVSCSI_COMMAND_PROCESSING_FAILED;
 753 }
 754
 755 static uint64_t
 756 pvscsi_on_issue_scsi(PVSCSIState *s)
 757 {
 758     trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI");
 759     return PVSCSI_COMMAND_PROCESSING_FAILED;
 760 }
 761
 762 static uint64_t
 763 pvscsi_on_cmd_setup_rings(PVSCSIState *s)
 764 {
 765     PVSCSICmdDescSetupRings *rc =
 766         (PVSCSICmdDescSetupRings *) s->curr_cmd_data;
 767
 768     trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS");
 769
 770     pvscsi_dbg_dump_tx_rings_config(rc);
 771     pvscsi_ring_init_data(&s->rings, rc);
 772     s->rings_info_valid = TRUE;
 773     return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 774 }
 775
 776 static uint64_t
 777 pvscsi_on_cmd_abort(PVSCSIState *s)
 778 {
 779     PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data;
 780     PVSCSIRequest *r, *next;
 781
 782     trace_pvscsi_on_cmd_abort(cmd->context, cmd->target);
 783
 784     QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) {
 785         if (r->req.context == cmd->context) {
 786             break;
 787         }
 788     }
 789     if (r) {
 790         assert(!r->completed);
 791         r->cmp.hostStatus = BTSTAT_ABORTQUEUE;
 792         scsi_req_cancel(r->sreq);
 793     }
 794
 795     return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 796 }
 797
 798 static uint64_t
 799 pvscsi_on_cmd_unknown(PVSCSIState *s)
 800 {
 801     trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]);
 802     return PVSCSI_COMMAND_PROCESSING_FAILED;
 803 }
 804
 805 static uint64_t
 806 pvscsi_on_cmd_reset_device(PVSCSIState *s)
 807 {
 808     uint8_t target_lun = 0;
 809     struct PVSCSICmdDescResetDevice *cmd =
 810         (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data;
 811     SCSIDevice *sdev;
 812
 813     sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun);
 814
 815     trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev);
 816
 817     if (sdev != NULL) {
 818         s->resetting++;
 819         device_reset(&sdev->qdev);
 820         s->resetting--;
 821         return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 822     }
 823
 824     return PVSCSI_COMMAND_PROCESSING_FAILED;
 825 }
 826
 827 static uint64_t
 828 pvscsi_on_cmd_reset_bus(PVSCSIState *s)
 829 {
 830     trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS");
 831
 832     s->resetting++;
 833     qbus_reset_all_fn(&s->bus);
 834     s->resetting--;
 835     return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 836 }
 837
 838 static uint64_t
 839 pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s)
 840 {
 841     PVSCSICmdDescSetupMsgRing *rc =
 842         (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data;
 843
 844     trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING");
 845
 846     if (!s->use_msg) {
 847         return PVSCSI_COMMAND_PROCESSING_FAILED;
 848     }
 849
 850     if (s->rings_info_valid) {
 851         pvscsi_ring_init_msg(&s->rings, rc);
 852         s->msg_ring_info_valid = TRUE;
 853     }
 854     return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t);
 855 }
 856
 857 static uint64_t
 858 pvscsi_on_cmd_adapter_reset(PVSCSIState *s)
 859 {
 860     trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET");
 861
 862     pvscsi_reset_adapter(s);
 863     return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 864 }
 865
 866 static const struct {
 867     int       data_size;
 868     uint64_t  (*handler_fn)(PVSCSIState *s);
 869 } pvscsi_commands[] = {
 870     [PVSCSI_CMD_FIRST] = {
 871         .data_size = 0,
 872         .handler_fn = pvscsi_on_cmd_unknown,
 873     },
 874
 875     /* Not implemented, data size defined based on what arrives on windows */
 876     [PVSCSI_CMD_CONFIG] = {
 877         .data_size = 6 * sizeof(uint32_t),
 878         .handler_fn = pvscsi_on_cmd_config,
 879     },
 880
 881     /* Command not implemented, data size is unknown */
 882     [PVSCSI_CMD_ISSUE_SCSI] = {
 883         .data_size = 0,
 884         .handler_fn = pvscsi_on_issue_scsi,
 885     },
 886
 887     /* Command not implemented, data size is unknown */
 888     [PVSCSI_CMD_DEVICE_UNPLUG] = {
 889         .data_size = 0,
 890         .handler_fn = pvscsi_on_cmd_unplug,
 891     },
 892
 893     [PVSCSI_CMD_SETUP_RINGS] = {
 894         .data_size = sizeof(PVSCSICmdDescSetupRings),
 895         .handler_fn = pvscsi_on_cmd_setup_rings,
 896     },
 897
 898     [PVSCSI_CMD_RESET_DEVICE] = {
 899         .data_size = sizeof(struct PVSCSICmdDescResetDevice),
 900         .handler_fn = pvscsi_on_cmd_reset_device,
 901     },
 902
 903     [PVSCSI_CMD_RESET_BUS] = {
 904         .data_size = 0,
 905         .handler_fn = pvscsi_on_cmd_reset_bus,
 906     },
 907
 908     [PVSCSI_CMD_SETUP_MSG_RING] = {
 909         .data_size = sizeof(PVSCSICmdDescSetupMsgRing),
 910         .handler_fn = pvscsi_on_cmd_setup_msg_ring,
 911     },
 912
 913     [PVSCSI_CMD_ADAPTER_RESET] = {
 914         .data_size = 0,
 915         .handler_fn = pvscsi_on_cmd_adapter_reset,
 916     },
 917
 918     [PVSCSI_CMD_ABORT_CMD] = {
 919         .data_size = sizeof(struct PVSCSICmdDescAbortCmd),
 920         .handler_fn = pvscsi_on_cmd_abort,
 921     },
 922 };
 923
 924 static void
 925 pvscsi_do_command_processing(PVSCSIState *s)
 926 {
 927     size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
 928
 929     assert(s->curr_cmd < PVSCSI_CMD_LAST);
 930     if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) {
 931         s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s);
 932         s->curr_cmd = PVSCSI_CMD_FIRST;
 933         s->curr_cmd_data_cntr   = 0;
 934     }
 935 }
 936
 937 static void
 938 pvscsi_on_command_data(PVSCSIState *s, uint32_t value)
 939 {
 940     size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
 941
 942     assert(bytes_arrived < sizeof(s->curr_cmd_data));
 943     s->curr_cmd_data[s->curr_cmd_data_cntr++] = value;
 944
 945     pvscsi_do_command_processing(s);
 946 }
 947
 948 static void
 949 pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id)
 950 {
 951     if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) {
 952         s->curr_cmd = cmd_id;
 953     } else {
 954         s->curr_cmd = PVSCSI_CMD_FIRST;
 955         trace_pvscsi_on_cmd_unknown(cmd_id);
 956     }
 957
 958     s->curr_cmd_data_cntr = 0;
 959     s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA;
 960
 961     pvscsi_do_command_processing(s);
 962 }
 963
 964 static void
 965 pvscsi_io_write(void *opaque, hwaddr addr,
 966                 uint64_t val, unsigned size)
 967 {
 968     PVSCSIState *s = opaque;
 969
 970     switch (addr) {
 971     case PVSCSI_REG_OFFSET_COMMAND:
 972         pvscsi_on_command(s, val);
 973         break;
 974
 975     case PVSCSI_REG_OFFSET_COMMAND_DATA:
 976         pvscsi_on_command_data(s, (uint32_t) val);
 977         break;
 978
 979     case PVSCSI_REG_OFFSET_INTR_STATUS:
 980         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val);
 981         s->reg_interrupt_status &= ~val;
 982         pvscsi_update_irq_status(s);
 983         pvscsi_schedule_completion_processing(s);
 984         break;
 985
 986     case PVSCSI_REG_OFFSET_INTR_MASK:
 987         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val);
 988         s->reg_interrupt_enabled = val;
 989         pvscsi_update_irq_status(s);
 990         break;
 991
 992     case PVSCSI_REG_OFFSET_KICK_NON_RW_IO:
 993         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val);
 994         pvscsi_process_io(s);
 995         break;
 996
 997     case PVSCSI_REG_OFFSET_KICK_RW_IO:
 998         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val);
 999         pvscsi_process_io(s);
1000         break;
1001
1002     case PVSCSI_REG_OFFSET_DEBUG:
1003         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val);
1004         break;
1005
1006     default:
1007         trace_pvscsi_io_write_unknown(addr, size, val);
1008         break;
1009     }
1010
1011 }
1012
1013 static uint64_t
1014 pvscsi_io_read(void *opaque, hwaddr addr, unsigned size)
1015 {
1016     PVSCSIState *s = opaque;
1017
1018     switch (addr) {
1019     case PVSCSI_REG_OFFSET_INTR_STATUS:
1020         trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS",
1021                              s->reg_interrupt_status);
1022         return s->reg_interrupt_status;
1023
1024     case PVSCSI_REG_OFFSET_INTR_MASK:
1025         trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK",
1026                              s->reg_interrupt_status);
1027         return s->reg_interrupt_enabled;
1028
1029     case PVSCSI_REG_OFFSET_COMMAND_STATUS:
1030         trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS",
1031                              s->reg_interrupt_status);
1032         return s->reg_command_status;
1033
1034     default:
1035         trace_pvscsi_io_read_unknown(addr, size);
1036         return 0;
1037     }
1038 }
1039
1040
1041 static bool
1042 pvscsi_init_msi(PVSCSIState *s)
1043 {
1044     int res;
1045     PCIDevice *d = PCI_DEVICE(s);
1046
1047     res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS,
1048                    PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK);
1049     if (res < 0) {
1050         trace_pvscsi_init_msi_fail(res);
1051         s->msi_used = false;
1052     } else {
1053         s->msi_used = true;
1054     }
1055
1056     return s->msi_used;
1057 }
1058
1059 static void
1060 pvscsi_cleanup_msi(PVSCSIState *s)
1061 {
1062     PCIDevice *d = PCI_DEVICE(s);
1063
1064     if (s->msi_used) {
1065         msi_uninit(d);
1066     }
1067 }
1068
1069 static const MemoryRegionOps pvscsi_ops = {
1070         .read = pvscsi_io_read,
1071         .write = pvscsi_io_write,
1072         .endianness = DEVICE_LITTLE_ENDIAN,
1073         .impl = {
1074                 .min_access_size = 4,
1075                 .max_access_size = 4,
1076         },
1077 };
1078
1079 static const struct SCSIBusInfo pvscsi_scsi_info = {
1080         .tcq = true,
1081         .max_target = PVSCSI_MAX_DEVS,
1082         .max_channel = 0,
1083         .max_lun = 0,
1084
1085         .get_sg_list = pvscsi_get_sg_list,
1086         .complete = pvscsi_command_complete,
1087         .cancel = pvscsi_request_cancelled,
1088 };
1089
1090 static int
1091 pvscsi_init(PCIDevice *pci_dev)
1092 {
1093     PVSCSIState *s = PVSCSI(pci_dev);
1094
1095     trace_pvscsi_state("init");
1096
1097     /* PCI subsystem ID, subsystem vendor ID, revision */
1098     if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) {
1099         pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000);
1100     } else {
1101         pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1102                      PCI_VENDOR_ID_VMWARE);
1103         pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1104                      PCI_DEVICE_ID_VMWARE_PVSCSI);
1105         pci_config_set_revision(pci_dev->config, 0x2);
1106     }
1107
1108     /* PCI latency timer = 255 */
1109     pci_dev->config[PCI_LATENCY_TIMER] = 0xff;
1110
1111     /* Interrupt pin A */
1112     pci_config_set_interrupt_pin(pci_dev->config, 1);
1113
1114     memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s,
1115                           "pvscsi-io", PVSCSI_MEM_SPACE_SIZE);
1116     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space);
1117
1118     pvscsi_init_msi(s);
1119
1120     if (pci_is_express(pci_dev) && pci_bus_is_express(pci_dev->bus)) {
1121         pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET);
1122     }
1123
1124     s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s);
1125     if (!s->completion_worker) {
1126         pvscsi_cleanup_msi(s);
1127         return -ENOMEM;
1128     }
1129
1130     scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
1131                  &pvscsi_scsi_info, NULL);
1132     /* override default SCSI bus hotplug-handler, with pvscsi's one */
1133     qbus_set_hotplug_handler(BUS(&s->bus), DEVICE(s), &error_abort);
1134     pvscsi_reset_state(s);
1135
1136     return 0;
1137 }
1138
1139 static void
1140 pvscsi_uninit(PCIDevice *pci_dev)
1141 {
1142     PVSCSIState *s = PVSCSI(pci_dev);
1143
1144     trace_pvscsi_state("uninit");
1145     qemu_bh_delete(s->completion_worker);
1146
1147     pvscsi_cleanup_msi(s);
1148 }
1149
1150 static void
1151 pvscsi_reset(DeviceState *dev)
1152 {
1153     PCIDevice *d = PCI_DEVICE(dev);
1154     PVSCSIState *s = PVSCSI(d);
1155
1156     trace_pvscsi_state("reset");
1157     pvscsi_reset_adapter(s);
1158 }
1159
1160 static void
1161 pvscsi_pre_save(void *opaque)
1162 {
1163     PVSCSIState *s = (PVSCSIState *) opaque;
1164
1165     trace_pvscsi_state("presave");
1166
1167     assert(QTAILQ_EMPTY(&s->pending_queue));
1168     assert(QTAILQ_EMPTY(&s->completion_queue));
1169 }
1170
1171 static int
1172 pvscsi_post_load(void *opaque, int version_id)
1173 {
1174     trace_pvscsi_state("postload");
1175     return 0;
1176 }
1177
1178 static bool pvscsi_vmstate_need_pcie_device(void *opaque)
1179 {
1180     PVSCSIState *s = PVSCSI(opaque);
1181
1182     return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE);
1183 }
1184
1185 static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id)
1186 {
1187     return !pvscsi_vmstate_need_pcie_device(opaque);
1188 }
1189
1190 static const VMStateDescription vmstate_pvscsi_pcie_device = {
1191     .name = "pvscsi/pcie",
1192     .needed = pvscsi_vmstate_need_pcie_device,
1193     .fields = (VMStateField[]) {
1194         VMSTATE_PCIE_DEVICE(parent_obj, PVSCSIState),
1195         VMSTATE_END_OF_LIST()
1196     }
1197 };
1198
1199 static const VMStateDescription vmstate_pvscsi = {
1200     .name = "pvscsi",
1201     .version_id = 0,
1202     .minimum_version_id = 0,
1203     .pre_save = pvscsi_pre_save,
1204     .post_load = pvscsi_post_load,
1205     .fields = (VMStateField[]) {
1206         VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState,
1207                             pvscsi_vmstate_test_pci_device, 0,
1208                             vmstate_pci_device, PCIDevice),
1209         VMSTATE_UINT8(msi_used, PVSCSIState),
1210         VMSTATE_UINT32(resetting, PVSCSIState),
1211         VMSTATE_UINT64(reg_interrupt_status, PVSCSIState),
1212         VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState),
1213         VMSTATE_UINT64(reg_command_status, PVSCSIState),
1214         VMSTATE_UINT64(curr_cmd, PVSCSIState),
1215         VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState),
1216         VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState,
1217                              ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)),
1218         VMSTATE_UINT8(rings_info_valid, PVSCSIState),
1219         VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState),
1220         VMSTATE_UINT8(use_msg, PVSCSIState),
1221
1222         VMSTATE_UINT64(rings.rs_pa, PVSCSIState),
1223         VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState),
1224         VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState),
1225         VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState,
1226                              PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1227         VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState,
1228                              PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1229         VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState),
1230         VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState),
1231
1232         VMSTATE_END_OF_LIST()
1233     },
1234     .subsections = (const VMStateDescription*[]) {
1235         &vmstate_pvscsi_pcie_device,
1236         NULL
1237     }
1238 };
1239
1240 static Property pvscsi_properties[] = {
1241     DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
1242     DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags,
1243                     PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false),
1244     DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags,
1245                     PVSCSI_COMPAT_DISABLE_PCIE_BIT, false),
1246     DEFINE_PROP_END_OF_LIST(),
1247 };
1248
1249 static void pvscsi_realize(DeviceState *qdev, Error **errp)
1250 {
1251     PVSCSIClass *pvs_c = PVSCSI_DEVICE_GET_CLASS(qdev);
1252     PCIDevice *pci_dev = PCI_DEVICE(qdev);
1253     PVSCSIState *s = PVSCSI(qdev);
1254
1255     if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) {
1256         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1257     }
1258
1259     pvs_c->parent_dc_realize(qdev, errp);
1260 }
1261
1262 static void pvscsi_class_init(ObjectClass *klass, void *data)
1263 {
1264     DeviceClass *dc = DEVICE_CLASS(klass);
1265     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1266     PVSCSIClass *pvs_k = PVSCSI_DEVICE_CLASS(klass);
1267     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
1268
1269     k->init = pvscsi_init;
1270     k->exit = pvscsi_uninit;
1271     k->vendor_id = PCI_VENDOR_ID_VMWARE;
1272     k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI;
1273     k->class_id = PCI_CLASS_STORAGE_SCSI;
1274     k->subsystem_id = 0x1000;
1275     pvs_k->parent_dc_realize = dc->realize;
1276     dc->realize = pvscsi_realize;
1277     dc->reset = pvscsi_reset;
1278     dc->vmsd = &vmstate_pvscsi;
1279     dc->props = pvscsi_properties;
1280     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1281     hc->unplug = pvscsi_hot_unplug;
1282     hc->plug = pvscsi_hotplug;
1283 }
1284
1285 static const TypeInfo pvscsi_info = {
1286     .name          = TYPE_PVSCSI,
1287     .parent        = TYPE_PCI_DEVICE,
1288     .class_size    = sizeof(PVSCSIClass),
1289     .instance_size = sizeof(PVSCSIState),
1290     .class_init    = pvscsi_class_init,
1291     .interfaces = (InterfaceInfo[]) {
1292         { TYPE_HOTPLUG_HANDLER },
1293         { }
1294     }
1295 };
1296
1297 static void
1298 pvscsi_register_types(void)
1299 {
1300     type_register_static(&pvscsi_info);
1301 }
1302
1303 type_init(pvscsi_register_types);