hw/sd/bcm2835_sdhost.c

   1 /*
   2  * Raspberry Pi (BCM2835) SD Host Controller
   3  *
   4  * Copyright (c) 2017 Antfield SAS
   5  *
   6  * Authors:
   7  *  Clement Deschamps <clement.deschamps@antfield.fr>
   8  *  Luc Michel <luc.michel@antfield.fr>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu/log.h"
  16 #include "qemu/module.h"
  17 #include "sysemu/blockdev.h"
  18 #include "hw/sd/bcm2835_sdhost.h"
  19 #include "trace.h"
  20
  21 #define TYPE_BCM2835_SDHOST_BUS "bcm2835-sdhost-bus"
  22 #define BCM2835_SDHOST_BUS(obj) \
  23     OBJECT_CHECK(SDBus, (obj), TYPE_BCM2835_SDHOST_BUS)
  24
  25 #define SDCMD  0x00 /* Command to SD card              - 16 R/W */
  26 #define SDARG  0x04 /* Argument to SD card             - 32 R/W */
  27 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
  28 #define SDCDIV 0x0c /* Start value for clock divider   - 11 R/W */
  29 #define SDRSP0 0x10 /* SD card rsp (31:0)         - 32 R   */
  30 #define SDRSP1 0x14 /* SD card rsp (63:32)        - 32 R   */
  31 #define SDRSP2 0x18 /* SD card rsp (95:64)        - 32 R   */
  32 #define SDRSP3 0x1c /* SD card rsp (127:96)       - 32 R   */
  33 #define SDHSTS 0x20 /* SD host status                  - 11 R   */
  34 #define SDVDD  0x30 /* SD card power control           -  1 R/W */
  35 #define SDEDM  0x34 /* Emergency Debug Mode            - 13 R/W */
  36 #define SDHCFG 0x38 /* Host configuration              -  2 R/W */
  37 #define SDHBCT 0x3c /* Host byte count (debug)         - 32 R/W */
  38 #define SDDATA 0x40 /* Data to/from SD card            - 32 R/W */
  39 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC)    -  9 R/W */
  40
  41 #define SDCMD_NEW_FLAG                  0x8000
  42 #define SDCMD_FAIL_FLAG                 0x4000
  43 #define SDCMD_BUSYWAIT                  0x800
  44 #define SDCMD_NO_RESPONSE               0x400
  45 #define SDCMD_LONG_RESPONSE             0x200
  46 #define SDCMD_WRITE_CMD                 0x80
  47 #define SDCMD_READ_CMD                  0x40
  48 #define SDCMD_CMD_MASK                  0x3f
  49
  50 #define SDCDIV_MAX_CDIV                 0x7ff
  51
  52 #define SDHSTS_BUSY_IRPT                0x400
  53 #define SDHSTS_BLOCK_IRPT               0x200
  54 #define SDHSTS_SDIO_IRPT                0x100
  55 #define SDHSTS_REW_TIME_OUT             0x80
  56 #define SDHSTS_CMD_TIME_OUT             0x40
  57 #define SDHSTS_CRC16_ERROR              0x20
  58 #define SDHSTS_CRC7_ERROR               0x10
  59 #define SDHSTS_FIFO_ERROR               0x08
  60 /* Reserved */
  61 /* Reserved */
  62 #define SDHSTS_DATA_FLAG                0x01
  63
  64 #define SDHCFG_BUSY_IRPT_EN     (1 << 10)
  65 #define SDHCFG_BLOCK_IRPT_EN    (1 << 8)
  66 #define SDHCFG_SDIO_IRPT_EN     (1 << 5)
  67 #define SDHCFG_DATA_IRPT_EN     (1 << 4)
  68 #define SDHCFG_SLOW_CARD        (1 << 3)
  69 #define SDHCFG_WIDE_EXT_BUS     (1 << 2)
  70 #define SDHCFG_WIDE_INT_BUS     (1 << 1)
  71 #define SDHCFG_REL_CMD_LINE     (1 << 0)
  72
  73 #define SDEDM_FORCE_DATA_MODE   (1 << 19)
  74 #define SDEDM_CLOCK_PULSE       (1 << 20)
  75 #define SDEDM_BYPASS            (1 << 21)
  76
  77 #define SDEDM_WRITE_THRESHOLD_SHIFT 9
  78 #define SDEDM_READ_THRESHOLD_SHIFT 14
  79 #define SDEDM_THRESHOLD_MASK     0x1f
  80
  81 #define SDEDM_FSM_MASK           0xf
  82 #define SDEDM_FSM_IDENTMODE      0x0
  83 #define SDEDM_FSM_DATAMODE       0x1
  84 #define SDEDM_FSM_READDATA       0x2
  85 #define SDEDM_FSM_WRITEDATA      0x3
  86 #define SDEDM_FSM_READWAIT       0x4
  87 #define SDEDM_FSM_READCRC        0x5
  88 #define SDEDM_FSM_WRITECRC       0x6
  89 #define SDEDM_FSM_WRITEWAIT1     0x7
  90 #define SDEDM_FSM_POWERDOWN      0x8
  91 #define SDEDM_FSM_POWERUP        0x9
  92 #define SDEDM_FSM_WRITESTART1    0xa
  93 #define SDEDM_FSM_WRITESTART2    0xb
  94 #define SDEDM_FSM_GENPULSES      0xc
  95 #define SDEDM_FSM_WRITEWAIT2     0xd
  96 #define SDEDM_FSM_STARTPOWDOWN   0xf
  97
  98 #define SDDATA_FIFO_WORDS        16
  99
 100 static void bcm2835_sdhost_update_irq(BCM2835SDHostState *s)
 101 {
 102     uint32_t irq = s->status &
 103         (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT | SDHSTS_SDIO_IRPT);
 104     trace_bcm2835_sdhost_update_irq(irq);
 105     qemu_set_irq(s->irq, !!irq);
 106 }
 107
 108 static void bcm2835_sdhost_send_command(BCM2835SDHostState *s)
 109 {
 110     SDRequest request;
 111     uint8_t rsp[16];
 112     int rlen;
 113
 114     request.cmd = s->cmd & SDCMD_CMD_MASK;
 115     request.arg = s->cmdarg;
 116
 117     rlen = sdbus_do_command(&s->sdbus, &request, rsp);
 118     if (rlen < 0) {
 119         goto error;
 120     }
 121     if (!(s->cmd & SDCMD_NO_RESPONSE)) {
 122         if (rlen == 0 || (rlen == 4 && (s->cmd & SDCMD_LONG_RESPONSE))) {
 123             goto error;
 124         }
 125         if (rlen != 4 && rlen != 16) {
 126             goto error;
 127         }
 128         if (rlen == 4) {
 129             s->rsp[0] = ldl_be_p(&rsp[0]);
 130             s->rsp[1] = s->rsp[2] = s->rsp[3] = 0;
 131         } else {
 132             s->rsp[0] = ldl_be_p(&rsp[12]);
 133             s->rsp[1] = ldl_be_p(&rsp[8]);
 134             s->rsp[2] = ldl_be_p(&rsp[4]);
 135             s->rsp[3] = ldl_be_p(&rsp[0]);
 136         }
 137     }
 138     /* We never really delay commands, so if this was a 'busywait' command
 139      * then we've completed it now and can raise the interrupt.
 140      */
 141     if ((s->cmd & SDCMD_BUSYWAIT) && (s->config & SDHCFG_BUSY_IRPT_EN)) {
 142         s->status |= SDHSTS_BUSY_IRPT;
 143     }
 144     return;
 145
 146 error:
 147     s->cmd |= SDCMD_FAIL_FLAG;
 148     s->status |= SDHSTS_CMD_TIME_OUT;
 149 }
 150
 151 static void bcm2835_sdhost_fifo_push(BCM2835SDHostState *s, uint32_t value)
 152 {
 153     int n;
 154
 155     if (s->fifo_len == BCM2835_SDHOST_FIFO_LEN) {
 156         /* FIFO overflow */
 157         return;
 158     }
 159     n = (s->fifo_pos + s->fifo_len) & (BCM2835_SDHOST_FIFO_LEN - 1);
 160     s->fifo_len++;
 161     s->fifo[n] = value;
 162 }
 163
 164 static uint32_t bcm2835_sdhost_fifo_pop(BCM2835SDHostState *s)
 165 {
 166     uint32_t value;
 167
 168     if (s->fifo_len == 0) {
 169         /* FIFO underflow */
 170         return 0;
 171     }
 172     value = s->fifo[s->fifo_pos];
 173     s->fifo_len--;
 174     s->fifo_pos = (s->fifo_pos + 1) & (BCM2835_SDHOST_FIFO_LEN - 1);
 175     return value;
 176 }
 177
 178 static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
 179 {
 180     uint32_t value = 0;
 181     int n;
 182     int is_read;
 183     int is_write;
 184
 185     is_read = (s->cmd & SDCMD_READ_CMD) != 0;
 186     is_write = (s->cmd & SDCMD_WRITE_CMD) != 0;
 187     if (s->datacnt != 0 && (is_write || sdbus_data_ready(&s->sdbus))) {
 188         if (is_read) {
 189             n = 0;
 190             while (s->datacnt && s->fifo_len < BCM2835_SDHOST_FIFO_LEN) {
 191                 value |= (uint32_t)sdbus_read_data(&s->sdbus) << (n * 8);
 192                 s->datacnt--;
 193                 n++;
 194                 if (n == 4) {
 195                     bcm2835_sdhost_fifo_push(s, value);
 196                     s->status |= SDHSTS_DATA_FLAG;
 197                     if (s->config & SDHCFG_DATA_IRPT_EN) {
 198                         s->status |= SDHSTS_SDIO_IRPT;
 199                     }
 200                     n = 0;
 201                     value = 0;
 202                 }
 203             }
 204             if (n != 0) {
 205                 bcm2835_sdhost_fifo_push(s, value);
 206                 s->status |= SDHSTS_DATA_FLAG;
 207                 if (s->config & SDHCFG_DATA_IRPT_EN) {
 208                     s->status |= SDHSTS_SDIO_IRPT;
 209                 }
 210             }
 211         } else if (is_write) { /* write */
 212             n = 0;
 213             while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) {
 214                 if (n == 0) {
 215                     value = bcm2835_sdhost_fifo_pop(s);
 216                     s->status |= SDHSTS_DATA_FLAG;
 217                     if (s->config & SDHCFG_DATA_IRPT_EN) {
 218                         s->status |= SDHSTS_SDIO_IRPT;
 219                     }
 220                     n = 4;
 221                 }
 222                 n--;
 223                 s->datacnt--;
 224                 sdbus_write_data(&s->sdbus, value & 0xff);
 225                 value >>= 8;
 226             }
 227         }
 228         if (s->datacnt == 0) {
 229             s->edm &= ~SDEDM_FSM_MASK;
 230             s->edm |= SDEDM_FSM_DATAMODE;
 231             trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm);
 232         }
 233         if (is_write) {
 234             /* set block interrupt at end of each block transfer */
 235             if (s->hbct && s->datacnt % s->hbct == 0 &&
 236                 (s->config & SDHCFG_BLOCK_IRPT_EN)) {
 237                 s->status |= SDHSTS_BLOCK_IRPT;
 238             }
 239             /* set data interrupt after each transfer */
 240             s->status |= SDHSTS_DATA_FLAG;
 241             if (s->config & SDHCFG_DATA_IRPT_EN) {
 242                 s->status |= SDHSTS_SDIO_IRPT;
 243             }
 244         }
 245     }
 246
 247     bcm2835_sdhost_update_irq(s);
 248
 249     s->edm &= ~(0x1f << 4);
 250     s->edm |= ((s->fifo_len & 0x1f) << 4);
 251     trace_bcm2835_sdhost_edm_change("fifo run", s->edm);
 252 }
 253
 254 static uint64_t bcm2835_sdhost_read(void *opaque, hwaddr offset,
 255     unsigned size)
 256 {
 257     BCM2835SDHostState *s = (BCM2835SDHostState *)opaque;
 258     uint32_t res = 0;
 259
 260     switch (offset) {
 261     case SDCMD:
 262         res = s->cmd;
 263         break;
 264     case SDHSTS:
 265         res = s->status;
 266         break;
 267     case SDRSP0:
 268         res = s->rsp[0];
 269         break;
 270     case SDRSP1:
 271         res = s->rsp[1];
 272         break;
 273     case SDRSP2:
 274         res = s->rsp[2];
 275         break;
 276     case SDRSP3:
 277         res = s->rsp[3];
 278         break;
 279     case SDEDM:
 280         res = s->edm;
 281         break;
 282     case SDVDD:
 283         res = s->vdd;
 284         break;
 285     case SDDATA:
 286         res = bcm2835_sdhost_fifo_pop(s);
 287         bcm2835_sdhost_fifo_run(s);
 288         break;
 289     case SDHBCT:
 290         res = s->hbct;
 291         break;
 292     case SDHBLC:
 293         res = s->hblc;
 294         break;
 295
 296     default:
 297         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 298                       __func__, offset);
 299         res = 0;
 300         break;
 301     }
 302
 303     trace_bcm2835_sdhost_read(offset, res, size);
 304
 305     return res;
 306 }
 307
 308 static void bcm2835_sdhost_write(void *opaque, hwaddr offset,
 309     uint64_t value, unsigned size)
 310 {
 311     BCM2835SDHostState *s = (BCM2835SDHostState *)opaque;
 312
 313     trace_bcm2835_sdhost_write(offset, value, size);
 314
 315     switch (offset) {
 316     case SDCMD:
 317         s->cmd = value;
 318         if (value & SDCMD_NEW_FLAG) {
 319             bcm2835_sdhost_send_command(s);
 320             bcm2835_sdhost_fifo_run(s);
 321             s->cmd &= ~SDCMD_NEW_FLAG;
 322         }
 323         break;
 324     case SDTOUT:
 325         break;
 326     case SDCDIV:
 327         break;
 328     case SDHSTS:
 329         s->status &= ~value;
 330         bcm2835_sdhost_update_irq(s);
 331         break;
 332     case SDARG:
 333         s->cmdarg = value;
 334         break;
 335     case SDEDM:
 336         if ((value & 0xf) == 0xf) {
 337             /* power down */
 338             value &= ~0xf;
 339         }
 340         s->edm = value;
 341         trace_bcm2835_sdhost_edm_change("guest register write", s->edm);
 342         break;
 343     case SDHCFG:
 344         s->config = value;
 345         bcm2835_sdhost_fifo_run(s);
 346         break;
 347     case SDVDD:
 348         s->vdd = value;
 349         break;
 350     case SDDATA:
 351         bcm2835_sdhost_fifo_push(s, value);
 352         bcm2835_sdhost_fifo_run(s);
 353         break;
 354     case SDHBCT:
 355         s->hbct = value;
 356         break;
 357     case SDHBLC:
 358         s->hblc = value;
 359         s->datacnt = s->hblc * s->hbct;
 360         bcm2835_sdhost_fifo_run(s);
 361         break;
 362
 363     default:
 364         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 365                       __func__, offset);
 366         break;
 367     }
 368 }
 369
 370 static const MemoryRegionOps bcm2835_sdhost_ops = {
 371     .read = bcm2835_sdhost_read,
 372     .write = bcm2835_sdhost_write,
 373     .endianness = DEVICE_NATIVE_ENDIAN,
 374 };
 375
 376 static const VMStateDescription vmstate_bcm2835_sdhost = {
 377     .name = TYPE_BCM2835_SDHOST,
 378     .version_id = 1,
 379     .minimum_version_id = 1,
 380     .fields = (VMStateField[]) {
 381         VMSTATE_UINT32(cmd, BCM2835SDHostState),
 382         VMSTATE_UINT32(cmdarg, BCM2835SDHostState),
 383         VMSTATE_UINT32(status, BCM2835SDHostState),
 384         VMSTATE_UINT32_ARRAY(rsp, BCM2835SDHostState, 4),
 385         VMSTATE_UINT32(config, BCM2835SDHostState),
 386         VMSTATE_UINT32(edm, BCM2835SDHostState),
 387         VMSTATE_UINT32(vdd, BCM2835SDHostState),
 388         VMSTATE_UINT32(hbct, BCM2835SDHostState),
 389         VMSTATE_UINT32(hblc, BCM2835SDHostState),
 390         VMSTATE_INT32(fifo_pos, BCM2835SDHostState),
 391         VMSTATE_INT32(fifo_len, BCM2835SDHostState),
 392         VMSTATE_UINT32_ARRAY(fifo, BCM2835SDHostState, BCM2835_SDHOST_FIFO_LEN),
 393         VMSTATE_UINT32(datacnt, BCM2835SDHostState),
 394         VMSTATE_END_OF_LIST()
 395     }
 396 };
 397
 398 static void bcm2835_sdhost_init(Object *obj)
 399 {
 400     BCM2835SDHostState *s = BCM2835_SDHOST(obj);
 401
 402     qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
 403                         TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus");
 404
 405     memory_region_init_io(&s->iomem, obj, &bcm2835_sdhost_ops, s,
 406                           TYPE_BCM2835_SDHOST, 0x1000);
 407     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 408     sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
 409 }
 410
 411 static void bcm2835_sdhost_reset(DeviceState *dev)
 412 {
 413     BCM2835SDHostState *s = BCM2835_SDHOST(dev);
 414
 415     s->cmd = 0;
 416     s->cmdarg = 0;
 417     s->edm = 0x0000c60f;
 418     trace_bcm2835_sdhost_edm_change("device reset", s->edm);
 419     s->config = 0;
 420     s->hbct = 0;
 421     s->hblc = 0;
 422     s->datacnt = 0;
 423     s->fifo_pos = 0;
 424     s->fifo_len = 0;
 425 }
 426
 427 static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data)
 428 {
 429     DeviceClass *dc = DEVICE_CLASS(klass);
 430
 431     dc->reset = bcm2835_sdhost_reset;
 432     dc->vmsd = &vmstate_bcm2835_sdhost;
 433 }
 434
 435 static TypeInfo bcm2835_sdhost_info = {
 436     .name          = TYPE_BCM2835_SDHOST,
 437     .parent        = TYPE_SYS_BUS_DEVICE,
 438     .instance_size = sizeof(BCM2835SDHostState),
 439     .class_init    = bcm2835_sdhost_class_init,
 440     .instance_init = bcm2835_sdhost_init,
 441 };
 442
 443 static const TypeInfo bcm2835_sdhost_bus_info = {
 444     .name = TYPE_BCM2835_SDHOST_BUS,
 445     .parent = TYPE_SD_BUS,
 446     .instance_size = sizeof(SDBus),
 447 };
 448
 449 static void bcm2835_sdhost_register_types(void)
 450 {
 451     type_register_static(&bcm2835_sdhost_info);
 452     type_register_static(&bcm2835_sdhost_bus_info);
 453 }
 454
 455 type_init(bcm2835_sdhost_register_types)