hw/sd/milkymist-memcard.c

   1 /*
   2  *  QEMU model of the Milkymist SD Card Controller.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://milkymist.walle.cc/socdoc/memcard.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qemu/log.h"
  26 #include "qemu/module.h"
  27 #include "hw/sysbus.h"
  28 #include "migration/vmstate.h"
  29 #include "trace.h"
  30 #include "qapi/error.h"
  31 #include "sysemu/block-backend.h"
  32 #include "sysemu/blockdev.h"
  33 #include "hw/qdev-properties.h"
  34 #include "hw/sd/sd.h"
  35 #include "qom/object.h"
  36
  37 enum {
  38     ENABLE_CMD_TX   = (1<<0),
  39     ENABLE_CMD_RX   = (1<<1),
  40     ENABLE_DAT_TX   = (1<<2),
  41     ENABLE_DAT_RX   = (1<<3),
  42 };
  43
  44 enum {
  45     PENDING_CMD_TX   = (1<<0),
  46     PENDING_CMD_RX   = (1<<1),
  47     PENDING_DAT_TX   = (1<<2),
  48     PENDING_DAT_RX   = (1<<3),
  49 };
  50
  51 enum {
  52     START_CMD_TX    = (1<<0),
  53     START_DAT_RX    = (1<<1),
  54 };
  55
  56 enum {
  57     R_CLK2XDIV = 0,
  58     R_ENABLE,
  59     R_PENDING,
  60     R_START,
  61     R_CMD,
  62     R_DAT,
  63     R_MAX
  64 };
  65
  66 #define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
  67 typedef struct MilkymistMemcardState MilkymistMemcardState;
  68 DECLARE_INSTANCE_CHECKER(MilkymistMemcardState, MILKYMIST_MEMCARD,
  69                          TYPE_MILKYMIST_MEMCARD)
  70
  71 #define TYPE_MILKYMIST_SDBUS "milkymist-sdbus"
  72
  73 struct MilkymistMemcardState {
  74     SysBusDevice parent_obj;
  75
  76     MemoryRegion regs_region;
  77     SDBus sdbus;
  78
  79     int command_write_ptr;
  80     int response_read_ptr;
  81     int response_len;
  82     int ignore_next_cmd;
  83     int enabled;
  84     uint8_t command[6];
  85     uint8_t response[17];
  86     uint32_t regs[R_MAX];
  87 };
  88
  89 static void update_pending_bits(MilkymistMemcardState *s)
  90 {
  91     /* transmits are instantaneous, thus tx pending bits are never set */
  92     s->regs[R_PENDING] = 0;
  93     /* if rx is enabled the corresponding pending bits are always set */
  94     if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
  95         s->regs[R_PENDING] |= PENDING_CMD_RX;
  96     }
  97     if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
  98         s->regs[R_PENDING] |= PENDING_DAT_RX;
  99     }
 100 }
 101
 102 static void memcard_sd_command(MilkymistMemcardState *s)
 103 {
 104     SDRequest req;
 105
 106     req.cmd = s->command[0] & 0x3f;
 107     req.arg = ldl_be_p(s->command + 1);
 108     req.crc = s->command[5];
 109
 110     s->response[0] = req.cmd;
 111     s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1);
 112     s->response_read_ptr = 0;
 113
 114     if (s->response_len == 16) {
 115         /* R2 response */
 116         s->response[0] = 0x3f;
 117         s->response_len += 1;
 118     } else if (s->response_len == 4) {
 119         /* no crc calculation, insert dummy byte */
 120         s->response[5] = 0;
 121         s->response_len += 2;
 122     }
 123
 124     if (req.cmd == 0) {
 125         /* next write is a dummy byte to clock the initialization of the sd
 126          * card */
 127         s->ignore_next_cmd = 1;
 128     }
 129 }
 130
 131 static uint64_t memcard_read(void *opaque, hwaddr addr,
 132                              unsigned size)
 133 {
 134     MilkymistMemcardState *s = opaque;
 135     uint32_t r = 0;
 136
 137     addr >>= 2;
 138     switch (addr) {
 139     case R_CMD:
 140         if (!s->enabled) {
 141             r = 0xff;
 142         } else {
 143             r = s->response[s->response_read_ptr++];
 144             if (s->response_read_ptr > s->response_len) {
 145                 qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
 146                               "read more cmd bytes than available: clipping\n");
 147                 s->response_read_ptr = 0;
 148             }
 149         }
 150         break;
 151     case R_DAT:
 152         if (!s->enabled) {
 153             r = 0xffffffff;
 154         } else {
 155             sdbus_read_data(&s->sdbus, &r, sizeof(r));
 156             be32_to_cpus(&r);
 157         }
 158         break;
 159     case R_CLK2XDIV:
 160     case R_ENABLE:
 161     case R_PENDING:
 162     case R_START:
 163         r = s->regs[addr];
 164         break;
 165
 166     default:
 167         qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
 168                       "read access to unknown register 0x%" HWADDR_PRIx "\n",
 169                       addr << 2);
 170         break;
 171     }
 172
 173     trace_milkymist_memcard_memory_read(addr << 2, r);
 174
 175     return r;
 176 }
 177
 178 static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
 179                           unsigned size)
 180 {
 181     MilkymistMemcardState *s = opaque;
 182     uint32_t val32;
 183
 184     trace_milkymist_memcard_memory_write(addr, value);
 185
 186     addr >>= 2;
 187     switch (addr) {
 188     case R_PENDING:
 189         /* clear rx pending bits */
 190         s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
 191         update_pending_bits(s);
 192         break;
 193     case R_CMD:
 194         if (!s->enabled) {
 195             break;
 196         }
 197         if (s->ignore_next_cmd) {
 198             s->ignore_next_cmd = 0;
 199             break;
 200         }
 201         s->command[s->command_write_ptr] = value & 0xff;
 202         s->command_write_ptr = (s->command_write_ptr + 1) % 6;
 203         if (s->command_write_ptr == 0) {
 204             memcard_sd_command(s);
 205         }
 206         break;
 207     case R_DAT:
 208         if (!s->enabled) {
 209             break;
 210         }
 211         val32 = cpu_to_be32(value);
 212         sdbus_write_data(&s->sdbus, &val32, sizeof(val32));
 213         break;
 214     case R_ENABLE:
 215         s->regs[addr] = value;
 216         update_pending_bits(s);
 217         break;
 218     case R_CLK2XDIV:
 219     case R_START:
 220         s->regs[addr] = value;
 221         break;
 222
 223     default:
 224         qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
 225                       "write access to unknown register 0x%" HWADDR_PRIx " "
 226                       "(value 0x%" PRIx64 ")\n", addr << 2, value);
 227         break;
 228     }
 229 }
 230
 231 static const MemoryRegionOps memcard_mmio_ops = {
 232     .read = memcard_read,
 233     .write = memcard_write,
 234     .valid = {
 235         .min_access_size = 4,
 236         .max_access_size = 4,
 237     },
 238     .endianness = DEVICE_NATIVE_ENDIAN,
 239 };
 240
 241 static void milkymist_memcard_reset(DeviceState *d)
 242 {
 243     MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
 244     int i;
 245
 246     s->command_write_ptr = 0;
 247     s->response_read_ptr = 0;
 248     s->response_len = 0;
 249
 250     for (i = 0; i < R_MAX; i++) {
 251         s->regs[i] = 0;
 252     }
 253 }
 254
 255 static void milkymist_memcard_set_readonly(DeviceState *dev, bool level)
 256 {
 257     qemu_log_mask(LOG_UNIMP,
 258                   "milkymist_memcard: read-only mode not supported\n");
 259 }
 260
 261 static void milkymist_memcard_set_inserted(DeviceState *dev, bool level)
 262 {
 263     MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
 264
 265     s->enabled = !!level;
 266 }
 267
 268 static void milkymist_memcard_init(Object *obj)
 269 {
 270     MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj);
 271     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 272
 273     memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
 274             "milkymist-memcard", R_MAX * 4);
 275     sysbus_init_mmio(dev, &s->regs_region);
 276
 277     qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
 278                         DEVICE(obj), "sd-bus");
 279 }
 280
 281 static const VMStateDescription vmstate_milkymist_memcard = {
 282     .name = "milkymist-memcard",
 283     .version_id = 1,
 284     .minimum_version_id = 1,
 285     .fields = (VMStateField[]) {
 286         VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
 287         VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
 288         VMSTATE_INT32(response_len, MilkymistMemcardState),
 289         VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
 290         VMSTATE_INT32(enabled, MilkymistMemcardState),
 291         VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
 292         VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
 293         VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
 294         VMSTATE_END_OF_LIST()
 295     }
 296 };
 297
 298 static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
 299 {
 300     DeviceClass *dc = DEVICE_CLASS(klass);
 301
 302     dc->reset = milkymist_memcard_reset;
 303     dc->vmsd = &vmstate_milkymist_memcard;
 304     /* Reason: output IRQs should be wired up */
 305     dc->user_creatable = false;
 306 }
 307
 308 static const TypeInfo milkymist_memcard_info = {
 309     .name          = TYPE_MILKYMIST_MEMCARD,
 310     .parent        = TYPE_SYS_BUS_DEVICE,
 311     .instance_size = sizeof(MilkymistMemcardState),
 312     .instance_init = milkymist_memcard_init,
 313     .class_init    = milkymist_memcard_class_init,
 314 };
 315
 316 static void milkymist_sdbus_class_init(ObjectClass *klass, void *data)
 317 {
 318     SDBusClass *sbc = SD_BUS_CLASS(klass);
 319
 320     sbc->set_inserted = milkymist_memcard_set_inserted;
 321     sbc->set_readonly = milkymist_memcard_set_readonly;
 322 }
 323
 324 static const TypeInfo milkymist_sdbus_info = {
 325     .name = TYPE_MILKYMIST_SDBUS,
 326     .parent = TYPE_SD_BUS,
 327     .instance_size = sizeof(SDBus),
 328     .class_init = milkymist_sdbus_class_init,
 329 };
 330
 331 static void milkymist_memcard_register_types(void)
 332 {
 333     type_register_static(&milkymist_memcard_info);
 334     type_register_static(&milkymist_sdbus_info);
 335 }
 336
 337 type_init(milkymist_memcard_register_types)