hw/sd/omap_mmc.c

   1 /*
   2  * OMAP on-chip MMC/SD host emulation.
   3  *
   4  * Copyright (C) 2006-2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "qemu/log.h"
  21 #include "hw/hw.h"
  22 #include "hw/arm/omap.h"
  23 #include "hw/sd/sd.h"
  24
  25 struct omap_mmc_s {
  26     qemu_irq irq;
  27     qemu_irq *dma;
  28     qemu_irq coverswitch;
  29     MemoryRegion iomem;
  30     omap_clk clk;
  31     SDState *card;
  32     uint16_t last_cmd;
  33     uint16_t sdio;
  34     uint16_t rsp[8];
  35     uint32_t arg;
  36     int lines;
  37     int dw;
  38     int mode;
  39     int enable;
  40     int be;
  41     int rev;
  42     uint16_t status;
  43     uint16_t mask;
  44     uint8_t cto;
  45     uint16_t dto;
  46     int clkdiv;
  47     uint16_t fifo[32];
  48     int fifo_start;
  49     int fifo_len;
  50     uint16_t blen;
  51     uint16_t blen_counter;
  52     uint16_t nblk;
  53     uint16_t nblk_counter;
  54     int tx_dma;
  55     int rx_dma;
  56     int af_level;
  57     int ae_level;
  58
  59     int ddir;
  60     int transfer;
  61
  62     int cdet_wakeup;
  63     int cdet_enable;
  64     int cdet_state;
  65     qemu_irq cdet;
  66 };
  67
  68 static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
  69 {
  70     qemu_set_irq(s->irq, !!(s->status & s->mask));
  71 }
  72
  73 static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
  74 {
  75     if (!host->transfer && !host->fifo_len) {
  76         host->status &= 0xf3ff;
  77         return;
  78     }
  79
  80     if (host->fifo_len > host->af_level && host->ddir) {
  81         if (host->rx_dma) {
  82             host->status &= 0xfbff;
  83             qemu_irq_raise(host->dma[1]);
  84         } else
  85             host->status |= 0x0400;
  86     } else {
  87         host->status &= 0xfbff;
  88         qemu_irq_lower(host->dma[1]);
  89     }
  90
  91     if (host->fifo_len < host->ae_level && !host->ddir) {
  92         if (host->tx_dma) {
  93             host->status &= 0xf7ff;
  94             qemu_irq_raise(host->dma[0]);
  95         } else
  96             host->status |= 0x0800;
  97     } else {
  98         qemu_irq_lower(host->dma[0]);
  99         host->status &= 0xf7ff;
 100     }
 101 }
 102
 103 typedef enum {
 104     sd_nore = 0,        /* no response */
 105     sd_r1,              /* normal response command */
 106     sd_r2,              /* CID, CSD registers */
 107     sd_r3,              /* OCR register */
 108     sd_r6 = 6,          /* Published RCA response */
 109     sd_r1b = -1,
 110 } sd_rsp_type_t;
 111
 112 static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
 113                 sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
 114 {
 115     uint32_t rspstatus, mask;
 116     int rsplen, timeout;
 117     SDRequest request;
 118     uint8_t response[16];
 119
 120     if (init && cmd == 0) {
 121         host->status |= 0x0001;
 122         return;
 123     }
 124
 125     if (resptype == sd_r1 && busy)
 126         resptype = sd_r1b;
 127
 128     if (type == sd_adtc) {
 129         host->fifo_start = 0;
 130         host->fifo_len = 0;
 131         host->transfer = 1;
 132         host->ddir = dir;
 133     } else
 134         host->transfer = 0;
 135     timeout = 0;
 136     mask = 0;
 137     rspstatus = 0;
 138
 139     request.cmd = cmd;
 140     request.arg = host->arg;
 141     request.crc = 0; /* FIXME */
 142
 143     rsplen = sd_do_command(host->card, &request, response);
 144
 145     /* TODO: validate CRCs */
 146     switch (resptype) {
 147     case sd_nore:
 148         rsplen = 0;
 149         break;
 150
 151     case sd_r1:
 152     case sd_r1b:
 153         if (rsplen < 4) {
 154             timeout = 1;
 155             break;
 156         }
 157         rsplen = 4;
 158
 159         mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
 160                 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
 161                 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
 162                 CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
 163                 CID_CSD_OVERWRITE;
 164         if (host->sdio & (1 << 13))
 165             mask |= AKE_SEQ_ERROR;
 166         rspstatus = ldl_be_p(response);
 167         break;
 168
 169     case sd_r2:
 170         if (rsplen < 16) {
 171             timeout = 1;
 172             break;
 173         }
 174         rsplen = 16;
 175         break;
 176
 177     case sd_r3:
 178         if (rsplen < 4) {
 179             timeout = 1;
 180             break;
 181         }
 182         rsplen = 4;
 183
 184         rspstatus = ldl_be_p(response);
 185         if (rspstatus & 0x80000000)
 186             host->status &= 0xe000;
 187         else
 188             host->status |= 0x1000;
 189         break;
 190
 191     case sd_r6:
 192         if (rsplen < 4) {
 193             timeout = 1;
 194             break;
 195         }
 196         rsplen = 4;
 197
 198         mask = 0xe000 | AKE_SEQ_ERROR;
 199         rspstatus = (response[2] << 8) | (response[3] << 0);
 200     }
 201
 202     if (rspstatus & mask)
 203         host->status |= 0x4000;
 204     else
 205         host->status &= 0xb000;
 206
 207     if (rsplen)
 208         for (rsplen = 0; rsplen < 8; rsplen ++)
 209             host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
 210                     (response[(rsplen << 1) | 0] << 8);
 211
 212     if (timeout)
 213         host->status |= 0x0080;
 214     else if (cmd == 12)
 215         host->status |= 0x0005; /* Makes it more real */
 216     else
 217         host->status |= 0x0001;
 218 }
 219
 220 static void omap_mmc_transfer(struct omap_mmc_s *host)
 221 {
 222     uint8_t value;
 223
 224     if (!host->transfer)
 225         return;
 226
 227     while (1) {
 228         if (host->ddir) {
 229             if (host->fifo_len > host->af_level)
 230                 break;
 231
 232             value = sd_read_data(host->card);
 233             host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
 234             if (-- host->blen_counter) {
 235                 value = sd_read_data(host->card);
 236                 host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
 237                         value << 8;
 238                 host->blen_counter --;
 239             }
 240
 241             host->fifo_len ++;
 242         } else {
 243             if (!host->fifo_len)
 244                 break;
 245
 246             value = host->fifo[host->fifo_start] & 0xff;
 247             sd_write_data(host->card, value);
 248             if (-- host->blen_counter) {
 249                 value = host->fifo[host->fifo_start] >> 8;
 250                 sd_write_data(host->card, value);
 251                 host->blen_counter --;
 252             }
 253
 254             host->fifo_start ++;
 255             host->fifo_len --;
 256             host->fifo_start &= 31;
 257         }
 258
 259         if (host->blen_counter == 0) {
 260             host->nblk_counter --;
 261             host->blen_counter = host->blen;
 262
 263             if (host->nblk_counter == 0) {
 264                 host->nblk_counter = host->nblk;
 265                 host->transfer = 0;
 266                 host->status |= 0x0008;
 267                 break;
 268             }
 269         }
 270     }
 271 }
 272
 273 static void omap_mmc_update(void *opaque)
 274 {
 275     struct omap_mmc_s *s = opaque;
 276     omap_mmc_transfer(s);
 277     omap_mmc_fifolevel_update(s);
 278     omap_mmc_interrupts_update(s);
 279 }
 280
 281 void omap_mmc_reset(struct omap_mmc_s *host)
 282 {
 283     host->last_cmd = 0;
 284     memset(host->rsp, 0, sizeof(host->rsp));
 285     host->arg = 0;
 286     host->dw = 0;
 287     host->mode = 0;
 288     host->enable = 0;
 289     host->status = 0;
 290     host->mask = 0;
 291     host->cto = 0;
 292     host->dto = 0;
 293     host->fifo_len = 0;
 294     host->blen = 0;
 295     host->blen_counter = 0;
 296     host->nblk = 0;
 297     host->nblk_counter = 0;
 298     host->tx_dma = 0;
 299     host->rx_dma = 0;
 300     host->ae_level = 0x00;
 301     host->af_level = 0x1f;
 302     host->transfer = 0;
 303     host->cdet_wakeup = 0;
 304     host->cdet_enable = 0;
 305     qemu_set_irq(host->coverswitch, host->cdet_state);
 306     host->clkdiv = 0;
 307
 308     /* Since we're still using the legacy SD API the card is not plugged
 309      * into any bus, and we must reset it manually. When omap_mmc is
 310      * QOMified this must move into the QOM reset function.
 311      */
 312     device_reset(DEVICE(host->card));
 313 }
 314
 315 static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
 316                               unsigned size)
 317 {
 318     uint16_t i;
 319     struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
 320
 321     if (size != 2) {
 322         return omap_badwidth_read16(opaque, offset);
 323     }
 324
 325     switch (offset) {
 326     case 0x00:  /* MMC_CMD */
 327         return s->last_cmd;
 328
 329     case 0x04:  /* MMC_ARGL */
 330         return s->arg & 0x0000ffff;
 331
 332     case 0x08:  /* MMC_ARGH */
 333         return s->arg >> 16;
 334
 335     case 0x0c:  /* MMC_CON */
 336         return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) |
 337                 (s->be << 10) | s->clkdiv;
 338
 339     case 0x10:  /* MMC_STAT */
 340         return s->status;
 341
 342     case 0x14:  /* MMC_IE */
 343         return s->mask;
 344
 345     case 0x18:  /* MMC_CTO */
 346         return s->cto;
 347
 348     case 0x1c:  /* MMC_DTO */
 349         return s->dto;
 350
 351     case 0x20:  /* MMC_DATA */
 352         /* TODO: support 8-bit access */
 353         i = s->fifo[s->fifo_start];
 354         if (s->fifo_len == 0) {
 355             printf("MMC: FIFO underrun\n");
 356             return i;
 357         }
 358         s->fifo_start ++;
 359         s->fifo_len --;
 360         s->fifo_start &= 31;
 361         omap_mmc_transfer(s);
 362         omap_mmc_fifolevel_update(s);
 363         omap_mmc_interrupts_update(s);
 364         return i;
 365
 366     case 0x24:  /* MMC_BLEN */
 367         return s->blen_counter;
 368
 369     case 0x28:  /* MMC_NBLK */
 370         return s->nblk_counter;
 371
 372     case 0x2c:  /* MMC_BUF */
 373         return (s->rx_dma << 15) | (s->af_level << 8) |
 374             (s->tx_dma << 7) | s->ae_level;
 375
 376     case 0x30:  /* MMC_SPI */
 377         return 0x0000;
 378     case 0x34:  /* MMC_SDIO */
 379         return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio;
 380     case 0x38:  /* MMC_SYST */
 381         return 0x0000;
 382
 383     case 0x3c:  /* MMC_REV */
 384         return s->rev;
 385
 386     case 0x40:  /* MMC_RSP0 */
 387     case 0x44:  /* MMC_RSP1 */
 388     case 0x48:  /* MMC_RSP2 */
 389     case 0x4c:  /* MMC_RSP3 */
 390     case 0x50:  /* MMC_RSP4 */
 391     case 0x54:  /* MMC_RSP5 */
 392     case 0x58:  /* MMC_RSP6 */
 393     case 0x5c:  /* MMC_RSP7 */
 394         return s->rsp[(offset - 0x40) >> 2];
 395
 396     /* OMAP2-specific */
 397     case 0x60:  /* MMC_IOSR */
 398     case 0x64:  /* MMC_SYSC */
 399         return 0;
 400     case 0x68:  /* MMC_SYSS */
 401         return 1;                                               /* RSTD */
 402     }
 403
 404     OMAP_BAD_REG(offset);
 405     return 0;
 406 }
 407
 408 static void omap_mmc_write(void *opaque, hwaddr offset,
 409                            uint64_t value, unsigned size)
 410 {
 411     int i;
 412     struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
 413
 414     if (size != 2) {
 415         omap_badwidth_write16(opaque, offset, value);
 416         return;
 417     }
 418
 419     switch (offset) {
 420     case 0x00:  /* MMC_CMD */
 421         if (!s->enable)
 422             break;
 423
 424         s->last_cmd = value;
 425         for (i = 0; i < 8; i ++)
 426             s->rsp[i] = 0x0000;
 427         omap_mmc_command(s, value & 63, (value >> 15) & 1,
 428                 (sd_cmd_type_t) ((value >> 12) & 3),
 429                 (value >> 11) & 1,
 430                 (sd_rsp_type_t) ((value >> 8) & 7),
 431                 (value >> 7) & 1);
 432         omap_mmc_update(s);
 433         break;
 434
 435     case 0x04:  /* MMC_ARGL */
 436         s->arg &= 0xffff0000;
 437         s->arg |= 0x0000ffff & value;
 438         break;
 439
 440     case 0x08:  /* MMC_ARGH */
 441         s->arg &= 0x0000ffff;
 442         s->arg |= value << 16;
 443         break;
 444
 445     case 0x0c:  /* MMC_CON */
 446         s->dw = (value >> 15) & 1;
 447         s->mode = (value >> 12) & 3;
 448         s->enable = (value >> 11) & 1;
 449         s->be = (value >> 10) & 1;
 450         s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
 451         if (s->mode != 0) {
 452             qemu_log_mask(LOG_UNIMP,
 453                           "omap_mmc_wr: mode #%i unimplemented\n", s->mode);
 454         }
 455         if (s->be != 0) {
 456             qemu_log_mask(LOG_UNIMP,
 457                           "omap_mmc_wr: Big Endian not implemented\n");
 458         }
 459         if (s->dw != 0 && s->lines < 4)
 460             printf("4-bit SD bus enabled\n");
 461         if (!s->enable)
 462             omap_mmc_reset(s);
 463         break;
 464
 465     case 0x10:  /* MMC_STAT */
 466         s->status &= ~value;
 467         omap_mmc_interrupts_update(s);
 468         break;
 469
 470     case 0x14:  /* MMC_IE */
 471         s->mask = value & 0x7fff;
 472         omap_mmc_interrupts_update(s);
 473         break;
 474
 475     case 0x18:  /* MMC_CTO */
 476         s->cto = value & 0xff;
 477         if (s->cto > 0xfd && s->rev <= 1)
 478             printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
 479         break;
 480
 481     case 0x1c:  /* MMC_DTO */
 482         s->dto = value & 0xffff;
 483         break;
 484
 485     case 0x20:  /* MMC_DATA */
 486         /* TODO: support 8-bit access */
 487         if (s->fifo_len == 32)
 488             break;
 489         s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
 490         s->fifo_len ++;
 491         omap_mmc_transfer(s);
 492         omap_mmc_fifolevel_update(s);
 493         omap_mmc_interrupts_update(s);
 494         break;
 495
 496     case 0x24:  /* MMC_BLEN */
 497         s->blen = (value & 0x07ff) + 1;
 498         s->blen_counter = s->blen;
 499         break;
 500
 501     case 0x28:  /* MMC_NBLK */
 502         s->nblk = (value & 0x07ff) + 1;
 503         s->nblk_counter = s->nblk;
 504         s->blen_counter = s->blen;
 505         break;
 506
 507     case 0x2c:  /* MMC_BUF */
 508         s->rx_dma = (value >> 15) & 1;
 509         s->af_level = (value >> 8) & 0x1f;
 510         s->tx_dma = (value >> 7) & 1;
 511         s->ae_level = value & 0x1f;
 512
 513         if (s->rx_dma)
 514             s->status &= 0xfbff;
 515         if (s->tx_dma)
 516             s->status &= 0xf7ff;
 517         omap_mmc_fifolevel_update(s);
 518         omap_mmc_interrupts_update(s);
 519         break;
 520
 521     /* SPI, SDIO and TEST modes unimplemented */
 522     case 0x30:  /* MMC_SPI (OMAP1 only) */
 523         break;
 524     case 0x34:  /* MMC_SDIO */
 525         s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
 526         s->cdet_wakeup = (value >> 9) & 1;
 527         s->cdet_enable = (value >> 2) & 1;
 528         break;
 529     case 0x38:  /* MMC_SYST */
 530         break;
 531
 532     case 0x3c:  /* MMC_REV */
 533     case 0x40:  /* MMC_RSP0 */
 534     case 0x44:  /* MMC_RSP1 */
 535     case 0x48:  /* MMC_RSP2 */
 536     case 0x4c:  /* MMC_RSP3 */
 537     case 0x50:  /* MMC_RSP4 */
 538     case 0x54:  /* MMC_RSP5 */
 539     case 0x58:  /* MMC_RSP6 */
 540     case 0x5c:  /* MMC_RSP7 */
 541         OMAP_RO_REG(offset);
 542         break;
 543
 544     /* OMAP2-specific */
 545     case 0x60:  /* MMC_IOSR */
 546         if (value & 0xf)
 547             printf("MMC: SDIO bits used!\n");
 548         break;
 549     case 0x64:  /* MMC_SYSC */
 550         if (value & (1 << 2))                                   /* SRTS */
 551             omap_mmc_reset(s);
 552         break;
 553     case 0x68:  /* MMC_SYSS */
 554         OMAP_RO_REG(offset);
 555         break;
 556
 557     default:
 558         OMAP_BAD_REG(offset);
 559     }
 560 }
 561
 562 static const MemoryRegionOps omap_mmc_ops = {
 563     .read = omap_mmc_read,
 564     .write = omap_mmc_write,
 565     .endianness = DEVICE_NATIVE_ENDIAN,
 566 };
 567
 568 static void omap_mmc_cover_cb(void *opaque, int line, int level)
 569 {
 570     struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
 571
 572     if (!host->cdet_state && level) {
 573         host->status |= 0x0002;
 574         omap_mmc_interrupts_update(host);
 575         if (host->cdet_wakeup) {
 576             /* TODO: Assert wake-up */
 577         }
 578     }
 579
 580     if (host->cdet_state != level) {
 581         qemu_set_irq(host->coverswitch, level);
 582         host->cdet_state = level;
 583     }
 584 }
 585
 586 struct omap_mmc_s *omap_mmc_init(hwaddr base,
 587                 MemoryRegion *sysmem,
 588                 BlockBackend *blk,
 589                 qemu_irq irq, qemu_irq dma[], omap_clk clk)
 590 {
 591     struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
 592
 593     s->irq = irq;
 594     s->dma = dma;
 595     s->clk = clk;
 596     s->lines = 1;       /* TODO: needs to be settable per-board */
 597     s->rev = 1;
 598
 599     memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
 600     memory_region_add_subregion(sysmem, base, &s->iomem);
 601
 602     /* Instantiate the storage */
 603     s->card = sd_init(blk, false);
 604     if (s->card == NULL) {
 605         exit(1);
 606     }
 607
 608     omap_mmc_reset(s);
 609
 610     return s;
 611 }
 612
 613 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
 614                 BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
 615                 omap_clk fclk, omap_clk iclk)
 616 {
 617     struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
 618
 619     s->irq = irq;
 620     s->dma = dma;
 621     s->clk = fclk;
 622     s->lines = 4;
 623     s->rev = 2;
 624
 625     memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
 626                           omap_l4_region_size(ta, 0));
 627     omap_l4_attach(ta, 0, &s->iomem);
 628
 629     /* Instantiate the storage */
 630     s->card = sd_init(blk, false);
 631     if (s->card == NULL) {
 632         exit(1);
 633     }
 634
 635     s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
 636     sd_set_cb(s->card, NULL, s->cdet);
 637
 638     omap_mmc_reset(s);
 639
 640     return s;
 641 }
 642
 643 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
 644 {
 645     if (s->cdet) {
 646         sd_set_cb(s->card, ro, s->cdet);
 647         s->coverswitch = cover;
 648         qemu_set_irq(cover, s->cdet_state);
 649     } else
 650         sd_set_cb(s->card, ro, cover);
 651 }
 652
 653 void omap_mmc_enable(struct omap_mmc_s *s, int enable)
 654 {
 655     sd_enable(s->card, enable);
 656 }