hw/sd/pxa2xx_mmci.c

   1 /*
   2  * Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GPLv2.
   8  *
   9  * Contributions after 2012-01-13 are licensed under the terms of the
  10  * GNU GPL, version 2 or (at your option) any later version.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "hw/hw.h"
  15 #include "hw/sysbus.h"
  16 #include "hw/arm/pxa.h"
  17 #include "hw/sd/sd.h"
  18 #include "hw/qdev.h"
  19 #include "hw/qdev-properties.h"
  20 #include "qemu/error-report.h"
  21
  22 #define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
  23 #define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
  24
  25 #define TYPE_PXA2XX_MMCI_BUS "pxa2xx-mmci-bus"
  26 #define PXA2XX_MMCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_PXA2XX_MMCI_BUS)
  27
  28 struct PXA2xxMMCIState {
  29     SysBusDevice parent_obj;
  30
  31     MemoryRegion iomem;
  32     qemu_irq irq;
  33     qemu_irq rx_dma;
  34     qemu_irq tx_dma;
  35     qemu_irq inserted;
  36     qemu_irq readonly;
  37
  38     BlockBackend *blk;
  39     SDBus sdbus;
  40
  41     uint32_t status;
  42     uint32_t clkrt;
  43     uint32_t spi;
  44     uint32_t cmdat;
  45     uint32_t resp_tout;
  46     uint32_t read_tout;
  47     int32_t blklen;
  48     int32_t numblk;
  49     uint32_t intmask;
  50     uint32_t intreq;
  51     int32_t cmd;
  52     uint32_t arg;
  53
  54     int32_t active;
  55     int32_t bytesleft;
  56     uint8_t tx_fifo[64];
  57     uint32_t tx_start;
  58     uint32_t tx_len;
  59     uint8_t rx_fifo[32];
  60     uint32_t rx_start;
  61     uint32_t rx_len;
  62     uint16_t resp_fifo[9];
  63     uint32_t resp_len;
  64
  65     int32_t cmdreq;
  66 };
  67
  68 static bool pxa2xx_mmci_vmstate_validate(void *opaque, int version_id)
  69 {
  70     PXA2xxMMCIState *s = opaque;
  71
  72     return s->tx_start < ARRAY_SIZE(s->tx_fifo)
  73         && s->rx_start < ARRAY_SIZE(s->rx_fifo)
  74         && s->tx_len <= ARRAY_SIZE(s->tx_fifo)
  75         && s->rx_len <= ARRAY_SIZE(s->rx_fifo)
  76         && s->resp_len <= ARRAY_SIZE(s->resp_fifo);
  77 }
  78
  79
  80 static const VMStateDescription vmstate_pxa2xx_mmci = {
  81     .name = "pxa2xx-mmci",
  82     .version_id = 2,
  83     .minimum_version_id = 2,
  84     .fields = (VMStateField[]) {
  85         VMSTATE_UINT32(status, PXA2xxMMCIState),
  86         VMSTATE_UINT32(clkrt, PXA2xxMMCIState),
  87         VMSTATE_UINT32(spi, PXA2xxMMCIState),
  88         VMSTATE_UINT32(cmdat, PXA2xxMMCIState),
  89         VMSTATE_UINT32(resp_tout, PXA2xxMMCIState),
  90         VMSTATE_UINT32(read_tout, PXA2xxMMCIState),
  91         VMSTATE_INT32(blklen, PXA2xxMMCIState),
  92         VMSTATE_INT32(numblk, PXA2xxMMCIState),
  93         VMSTATE_UINT32(intmask, PXA2xxMMCIState),
  94         VMSTATE_UINT32(intreq, PXA2xxMMCIState),
  95         VMSTATE_INT32(cmd, PXA2xxMMCIState),
  96         VMSTATE_UINT32(arg, PXA2xxMMCIState),
  97         VMSTATE_INT32(cmdreq, PXA2xxMMCIState),
  98         VMSTATE_INT32(active, PXA2xxMMCIState),
  99         VMSTATE_INT32(bytesleft, PXA2xxMMCIState),
 100         VMSTATE_UINT32(tx_start, PXA2xxMMCIState),
 101         VMSTATE_UINT32(tx_len, PXA2xxMMCIState),
 102         VMSTATE_UINT32(rx_start, PXA2xxMMCIState),
 103         VMSTATE_UINT32(rx_len, PXA2xxMMCIState),
 104         VMSTATE_UINT32(resp_len, PXA2xxMMCIState),
 105         VMSTATE_VALIDATE("fifo size incorrect", pxa2xx_mmci_vmstate_validate),
 106         VMSTATE_UINT8_ARRAY(tx_fifo, PXA2xxMMCIState, 64),
 107         VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxMMCIState, 32),
 108         VMSTATE_UINT16_ARRAY(resp_fifo, PXA2xxMMCIState, 9),
 109         VMSTATE_END_OF_LIST()
 110     }
 111 };
 112
 113 #define MMC_STRPCL      0x00    /* MMC Clock Start/Stop register */
 114 #define MMC_STAT        0x04    /* MMC Status register */
 115 #define MMC_CLKRT       0x08    /* MMC Clock Rate register */
 116 #define MMC_SPI         0x0c    /* MMC SPI Mode register */
 117 #define MMC_CMDAT       0x10    /* MMC Command/Data register */
 118 #define MMC_RESTO       0x14    /* MMC Response Time-Out register */
 119 #define MMC_RDTO        0x18    /* MMC Read Time-Out register */
 120 #define MMC_BLKLEN      0x1c    /* MMC Block Length register */
 121 #define MMC_NUMBLK      0x20    /* MMC Number of Blocks register */
 122 #define MMC_PRTBUF      0x24    /* MMC Buffer Partly Full register */
 123 #define MMC_I_MASK      0x28    /* MMC Interrupt Mask register */
 124 #define MMC_I_REG       0x2c    /* MMC Interrupt Request register */
 125 #define MMC_CMD         0x30    /* MMC Command register */
 126 #define MMC_ARGH        0x34    /* MMC Argument High register */
 127 #define MMC_ARGL        0x38    /* MMC Argument Low register */
 128 #define MMC_RES         0x3c    /* MMC Response FIFO */
 129 #define MMC_RXFIFO      0x40    /* MMC Receive FIFO */
 130 #define MMC_TXFIFO      0x44    /* MMC Transmit FIFO */
 131 #define MMC_RDWAIT      0x48    /* MMC RD_WAIT register */
 132 #define MMC_BLKS_REM    0x4c    /* MMC Blocks Remaining register */
 133
 134 /* Bitfield masks */
 135 #define STRPCL_STOP_CLK (1 << 0)
 136 #define STRPCL_STRT_CLK (1 << 1)
 137 #define STAT_TOUT_RES   (1 << 1)
 138 #define STAT_CLK_EN     (1 << 8)
 139 #define STAT_DATA_DONE  (1 << 11)
 140 #define STAT_PRG_DONE   (1 << 12)
 141 #define STAT_END_CMDRES (1 << 13)
 142 #define SPI_SPI_MODE    (1 << 0)
 143 #define CMDAT_RES_TYPE  (3 << 0)
 144 #define CMDAT_DATA_EN   (1 << 2)
 145 #define CMDAT_WR_RD     (1 << 3)
 146 #define CMDAT_DMA_EN    (1 << 7)
 147 #define CMDAT_STOP_TRAN (1 << 10)
 148 #define INT_DATA_DONE   (1 << 0)
 149 #define INT_PRG_DONE    (1 << 1)
 150 #define INT_END_CMD     (1 << 2)
 151 #define INT_STOP_CMD    (1 << 3)
 152 #define INT_CLK_OFF     (1 << 4)
 153 #define INT_RXFIFO_REQ  (1 << 5)
 154 #define INT_TXFIFO_REQ  (1 << 6)
 155 #define INT_TINT        (1 << 7)
 156 #define INT_DAT_ERR     (1 << 8)
 157 #define INT_RES_ERR     (1 << 9)
 158 #define INT_RD_STALLED  (1 << 10)
 159 #define INT_SDIO_INT    (1 << 11)
 160 #define INT_SDIO_SACK   (1 << 12)
 161 #define PRTBUF_PRT_BUF  (1 << 0)
 162
 163 /* Route internal interrupt lines to the global IC and DMA */
 164 static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
 165 {
 166     uint32_t mask = s->intmask;
 167     if (s->cmdat & CMDAT_DMA_EN) {
 168         mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;
 169
 170         qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
 171         qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
 172     }
 173
 174     qemu_set_irq(s->irq, !!(s->intreq & ~mask));
 175 }
 176
 177 static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
 178 {
 179     if (!s->active)
 180         return;
 181
 182     if (s->cmdat & CMDAT_WR_RD) {
 183         while (s->bytesleft && s->tx_len) {
 184             sdbus_write_data(&s->sdbus, s->tx_fifo[s->tx_start++]);
 185             s->tx_start &= 0x1f;
 186             s->tx_len --;
 187             s->bytesleft --;
 188         }
 189         if (s->bytesleft)
 190             s->intreq |= INT_TXFIFO_REQ;
 191     } else
 192         while (s->bytesleft && s->rx_len < 32) {
 193             s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
 194                 sdbus_read_data(&s->sdbus);
 195             s->bytesleft --;
 196             s->intreq |= INT_RXFIFO_REQ;
 197         }
 198
 199     if (!s->bytesleft) {
 200         s->active = 0;
 201         s->intreq |= INT_DATA_DONE;
 202         s->status |= STAT_DATA_DONE;
 203
 204         if (s->cmdat & CMDAT_WR_RD) {
 205             s->intreq |= INT_PRG_DONE;
 206             s->status |= STAT_PRG_DONE;
 207         }
 208     }
 209
 210     pxa2xx_mmci_int_update(s);
 211 }
 212
 213 static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
 214 {
 215     int rsplen, i;
 216     SDRequest request;
 217     uint8_t response[16];
 218
 219     s->active = 1;
 220     s->rx_len = 0;
 221     s->tx_len = 0;
 222     s->cmdreq = 0;
 223
 224     request.cmd = s->cmd;
 225     request.arg = s->arg;
 226     request.crc = 0;    /* FIXME */
 227
 228     rsplen = sdbus_do_command(&s->sdbus, &request, response);
 229     s->intreq |= INT_END_CMD;
 230
 231     memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
 232     switch (s->cmdat & CMDAT_RES_TYPE) {
 233 #define PXAMMCI_RESP(wd, value0, value1)        \
 234         s->resp_fifo[(wd) + 0] |= (value0);     \
 235         s->resp_fifo[(wd) + 1] |= (value1) << 8;
 236     case 0:     /* No response */
 237         goto complete;
 238
 239     case 1:     /* R1, R4, R5 or R6 */
 240         if (rsplen < 4)
 241             goto timeout;
 242         goto complete;
 243
 244     case 2:     /* R2 */
 245         if (rsplen < 16)
 246             goto timeout;
 247         goto complete;
 248
 249     case 3:     /* R3 */
 250         if (rsplen < 4)
 251             goto timeout;
 252         goto complete;
 253
 254     complete:
 255         for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
 256             PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
 257         }
 258         s->status |= STAT_END_CMDRES;
 259
 260         if (!(s->cmdat & CMDAT_DATA_EN))
 261             s->active = 0;
 262         else
 263             s->bytesleft = s->numblk * s->blklen;
 264
 265         s->resp_len = 0;
 266         break;
 267
 268     timeout:
 269         s->active = 0;
 270         s->status |= STAT_TOUT_RES;
 271         break;
 272     }
 273
 274     pxa2xx_mmci_fifo_update(s);
 275 }
 276
 277 static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
 278 {
 279     PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
 280     uint32_t ret;
 281
 282     switch (offset) {
 283     case MMC_STRPCL:
 284         return 0;
 285     case MMC_STAT:
 286         return s->status;
 287     case MMC_CLKRT:
 288         return s->clkrt;
 289     case MMC_SPI:
 290         return s->spi;
 291     case MMC_CMDAT:
 292         return s->cmdat;
 293     case MMC_RESTO:
 294         return s->resp_tout;
 295     case MMC_RDTO:
 296         return s->read_tout;
 297     case MMC_BLKLEN:
 298         return s->blklen;
 299     case MMC_NUMBLK:
 300         return s->numblk;
 301     case MMC_PRTBUF:
 302         return 0;
 303     case MMC_I_MASK:
 304         return s->intmask;
 305     case MMC_I_REG:
 306         return s->intreq;
 307     case MMC_CMD:
 308         return s->cmd | 0x40;
 309     case MMC_ARGH:
 310         return s->arg >> 16;
 311     case MMC_ARGL:
 312         return s->arg & 0xffff;
 313     case MMC_RES:
 314         if (s->resp_len < 9)
 315             return s->resp_fifo[s->resp_len ++];
 316         return 0;
 317     case MMC_RXFIFO:
 318         ret = 0;
 319         while (size-- && s->rx_len) {
 320             ret |= s->rx_fifo[s->rx_start++] << (size << 3);
 321             s->rx_start &= 0x1f;
 322             s->rx_len --;
 323         }
 324         s->intreq &= ~INT_RXFIFO_REQ;
 325         pxa2xx_mmci_fifo_update(s);
 326         return ret;
 327     case MMC_RDWAIT:
 328         return 0;
 329     case MMC_BLKS_REM:
 330         return s->numblk;
 331     default:
 332         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 333     }
 334
 335     return 0;
 336 }
 337
 338 static void pxa2xx_mmci_write(void *opaque,
 339                               hwaddr offset, uint64_t value, unsigned size)
 340 {
 341     PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
 342
 343     switch (offset) {
 344     case MMC_STRPCL:
 345         if (value & STRPCL_STRT_CLK) {
 346             s->status |= STAT_CLK_EN;
 347             s->intreq &= ~INT_CLK_OFF;
 348
 349             if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
 350                 s->status &= STAT_CLK_EN;
 351                 pxa2xx_mmci_wakequeues(s);
 352             }
 353         }
 354
 355         if (value & STRPCL_STOP_CLK) {
 356             s->status &= ~STAT_CLK_EN;
 357             s->intreq |= INT_CLK_OFF;
 358             s->active = 0;
 359         }
 360
 361         pxa2xx_mmci_int_update(s);
 362         break;
 363
 364     case MMC_CLKRT:
 365         s->clkrt = value & 7;
 366         break;
 367
 368     case MMC_SPI:
 369         s->spi = value & 0xf;
 370         if (value & SPI_SPI_MODE)
 371             printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
 372         break;
 373
 374     case MMC_CMDAT:
 375         s->cmdat = value & 0x3dff;
 376         s->active = 0;
 377         s->cmdreq = 1;
 378         if (!(value & CMDAT_STOP_TRAN)) {
 379             s->status &= STAT_CLK_EN;
 380
 381             if (s->status & STAT_CLK_EN)
 382                 pxa2xx_mmci_wakequeues(s);
 383         }
 384
 385         pxa2xx_mmci_int_update(s);
 386         break;
 387
 388     case MMC_RESTO:
 389         s->resp_tout = value & 0x7f;
 390         break;
 391
 392     case MMC_RDTO:
 393         s->read_tout = value & 0xffff;
 394         break;
 395
 396     case MMC_BLKLEN:
 397         s->blklen = value & 0xfff;
 398         break;
 399
 400     case MMC_NUMBLK:
 401         s->numblk = value & 0xffff;
 402         break;
 403
 404     case MMC_PRTBUF:
 405         if (value & PRTBUF_PRT_BUF) {
 406             s->tx_start ^= 32;
 407             s->tx_len = 0;
 408         }
 409         pxa2xx_mmci_fifo_update(s);
 410         break;
 411
 412     case MMC_I_MASK:
 413         s->intmask = value & 0x1fff;
 414         pxa2xx_mmci_int_update(s);
 415         break;
 416
 417     case MMC_CMD:
 418         s->cmd = value & 0x3f;
 419         break;
 420
 421     case MMC_ARGH:
 422         s->arg &= 0x0000ffff;
 423         s->arg |= value << 16;
 424         break;
 425
 426     case MMC_ARGL:
 427         s->arg &= 0xffff0000;
 428         s->arg |= value & 0x0000ffff;
 429         break;
 430
 431     case MMC_TXFIFO:
 432         while (size-- && s->tx_len < 0x20)
 433             s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
 434                     (value >> (size << 3)) & 0xff;
 435         s->intreq &= ~INT_TXFIFO_REQ;
 436         pxa2xx_mmci_fifo_update(s);
 437         break;
 438
 439     case MMC_RDWAIT:
 440     case MMC_BLKS_REM:
 441         break;
 442
 443     default:
 444         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 445     }
 446 }
 447
 448 static const MemoryRegionOps pxa2xx_mmci_ops = {
 449     .read = pxa2xx_mmci_read,
 450     .write = pxa2xx_mmci_write,
 451     .endianness = DEVICE_NATIVE_ENDIAN,
 452 };
 453
 454 PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
 455                 hwaddr base,
 456                 BlockBackend *blk, qemu_irq irq,
 457                 qemu_irq rx_dma, qemu_irq tx_dma)
 458 {
 459     DeviceState *dev, *carddev;
 460     SysBusDevice *sbd;
 461     PXA2xxMMCIState *s;
 462     Error *err = NULL;
 463
 464     dev = qdev_create(NULL, TYPE_PXA2XX_MMCI);
 465     s = PXA2XX_MMCI(dev);
 466     sbd = SYS_BUS_DEVICE(dev);
 467     sysbus_mmio_map(sbd, 0, base);
 468     sysbus_connect_irq(sbd, 0, irq);
 469     qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
 470     qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
 471
 472     /* Create and plug in the sd card */
 473     carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
 474     qdev_prop_set_drive(carddev, "drive", blk, &err);
 475     if (err) {
 476         error_report("failed to init SD card: %s", error_get_pretty(err));
 477         return NULL;
 478     }
 479     object_property_set_bool(OBJECT(carddev), true, "realized", &err);
 480     if (err) {
 481         error_report("failed to init SD card: %s", error_get_pretty(err));
 482         return NULL;
 483     }
 484
 485     return s;
 486 }
 487
 488 static void pxa2xx_mmci_set_inserted(DeviceState *dev, bool inserted)
 489 {
 490     PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
 491
 492     qemu_set_irq(s->inserted, inserted);
 493 }
 494
 495 static void pxa2xx_mmci_set_readonly(DeviceState *dev, bool readonly)
 496 {
 497     PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
 498
 499     qemu_set_irq(s->readonly, readonly);
 500 }
 501
 502 void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
 503                           qemu_irq coverswitch)
 504 {
 505     DeviceState *dev = DEVICE(s);
 506
 507     s->readonly = readonly;
 508     s->inserted = coverswitch;
 509
 510     pxa2xx_mmci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
 511     pxa2xx_mmci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
 512 }
 513
 514 static void pxa2xx_mmci_reset(DeviceState *d)
 515 {
 516     PXA2xxMMCIState *s = PXA2XX_MMCI(d);
 517
 518     s->status = 0;
 519     s->clkrt = 0;
 520     s->spi = 0;
 521     s->cmdat = 0;
 522     s->resp_tout = 0;
 523     s->read_tout = 0;
 524     s->blklen = 0;
 525     s->numblk = 0;
 526     s->intmask = 0;
 527     s->intreq = 0;
 528     s->cmd = 0;
 529     s->arg = 0;
 530     s->active = 0;
 531     s->bytesleft = 0;
 532     s->tx_start = 0;
 533     s->tx_len = 0;
 534     s->rx_start = 0;
 535     s->rx_len = 0;
 536     s->resp_len = 0;
 537     s->cmdreq = 0;
 538     memset(s->tx_fifo, 0, sizeof(s->tx_fifo));
 539     memset(s->rx_fifo, 0, sizeof(s->rx_fifo));
 540     memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
 541 }
 542
 543 static void pxa2xx_mmci_instance_init(Object *obj)
 544 {
 545     PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
 546     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 547     DeviceState *dev = DEVICE(obj);
 548
 549     memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
 550                           "pxa2xx-mmci", 0x00100000);
 551     sysbus_init_mmio(sbd, &s->iomem);
 552     sysbus_init_irq(sbd, &s->irq);
 553     qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
 554     qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
 555
 556     qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
 557                         TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
 558 }
 559
 560 static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data)
 561 {
 562     DeviceClass *dc = DEVICE_CLASS(klass);
 563
 564     dc->vmsd = &vmstate_pxa2xx_mmci;
 565     dc->reset = pxa2xx_mmci_reset;
 566 }
 567
 568 static void pxa2xx_mmci_bus_class_init(ObjectClass *klass, void *data)
 569 {
 570     SDBusClass *sbc = SD_BUS_CLASS(klass);
 571
 572     sbc->set_inserted = pxa2xx_mmci_set_inserted;
 573     sbc->set_readonly = pxa2xx_mmci_set_readonly;
 574 }
 575
 576 static const TypeInfo pxa2xx_mmci_info = {
 577     .name = TYPE_PXA2XX_MMCI,
 578     .parent = TYPE_SYS_BUS_DEVICE,
 579     .instance_size = sizeof(PXA2xxMMCIState),
 580     .instance_init = pxa2xx_mmci_instance_init,
 581     .class_init = pxa2xx_mmci_class_init,
 582 };
 583
 584 static const TypeInfo pxa2xx_mmci_bus_info = {
 585     .name = TYPE_PXA2XX_MMCI_BUS,
 586     .parent = TYPE_SD_BUS,
 587     .instance_size = sizeof(SDBus),
 588     .class_init = pxa2xx_mmci_bus_class_init,
 589 };
 590
 591 static void pxa2xx_mmci_register_types(void)
 592 {
 593     type_register_static(&pxa2xx_mmci_info);
 594     type_register_static(&pxa2xx_mmci_bus_info);
 595 }
 596
 597 type_init(pxa2xx_mmci_register_types)