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2 * QEMU 16450 UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
41 #include <netinet/in.h>
46 //#define DEBUG_SERIAL
48 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
50 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
51 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
52 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
53 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
55 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
56 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
58 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
59 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
60 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
61 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
64 * These are the definitions for the Modem Control Register
66 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
67 #define UART_MCR_OUT2 0x08 /* Out2 complement */
68 #define UART_MCR_OUT1 0x04 /* Out1 complement */
69 #define UART_MCR_RTS 0x02 /* RTS complement */
70 #define UART_MCR_DTR 0x01 /* DTR complement */
73 * These are the definitions for the Modem Status Register
75 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
76 #define UART_MSR_RI 0x40 /* Ring Indicator */
77 #define UART_MSR_DSR 0x20 /* Data Set Ready */
78 #define UART_MSR_CTS 0x10 /* Clear to Send */
79 #define UART_MSR_DDCD 0x08 /* Delta DCD */
80 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
81 #define UART_MSR_DDSR 0x02 /* Delta DSR */
82 #define UART_MSR_DCTS 0x01 /* Delta CTS */
83 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
85 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
86 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
87 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
88 #define UART_LSR_FE 0x08 /* Frame error indicator */
89 #define UART_LSR_PE 0x04 /* Parity error indicator */
90 #define UART_LSR_OE 0x02 /* Overrun error indicator */
91 #define UART_LSR_DR 0x01 /* Receiver data ready */
93 typedef struct SerialState
{
95 uint8_t rbr
; /* receive register */
97 uint8_t iir
; /* read only */
100 uint8_t lsr
; /* read only */
103 /* NOTE: this hidden state is necessary for tx irq generation as
104 it can be reset while reading iir */
109 SerialState serial_ports
[1];
111 void serial_update_irq(void)
113 SerialState
*s
= &serial_ports
[0];
115 if ((s
->lsr
& UART_LSR_DR
) && (s
->ier
& UART_IER_RDI
)) {
116 s
->iir
= UART_IIR_RDI
;
117 } else if (s
->thr_ipending
&& (s
->ier
& UART_IER_THRI
)) {
118 s
->iir
= UART_IIR_THRI
;
120 s
->iir
= UART_IIR_NO_INT
;
122 if (s
->iir
!= UART_IIR_NO_INT
) {
123 pic_set_irq(s
->irq
, 1);
125 pic_set_irq(s
->irq
, 0);
129 void serial_ioport_write(CPUState
*env
, uint32_t addr
, uint32_t val
)
131 SerialState
*s
= &serial_ports
[0];
137 printf("serial: write addr=0x%02x val=0x%02x\n", addr
, val
);
142 if (s
->lcr
& UART_LCR_DLAB
) {
143 s
->divider
= (s
->divider
& 0xff00) | val
;
146 s
->lsr
&= ~UART_LSR_THRE
;
151 ret
= write(1, &ch
, 1);
154 s
->lsr
|= UART_LSR_THRE
;
155 s
->lsr
|= UART_LSR_TEMT
;
160 if (s
->lcr
& UART_LCR_DLAB
) {
161 s
->divider
= (s
->divider
& 0x00ff) | (val
<< 8);
186 uint32_t serial_ioport_read(CPUState
*env
, uint32_t addr
)
188 SerialState
*s
= &serial_ports
[0];
195 if (s
->lcr
& UART_LCR_DLAB
) {
196 ret
= s
->divider
& 0xff;
199 s
->lsr
&= ~(UART_LSR_DR
| UART_LSR_BI
);
204 if (s
->lcr
& UART_LCR_DLAB
) {
205 ret
= (s
->divider
>> 8) & 0xff;
212 /* reset THR pending bit */
213 if ((ret
& 0x7) == UART_IIR_THRI
)
227 if (s
->mcr
& UART_MCR_LOOP
) {
228 /* in loopback, the modem output pins are connected to the
230 ret
= (s
->mcr
& 0x0c) << 4;
231 ret
|= (s
->mcr
& 0x02) << 3;
232 ret
|= (s
->mcr
& 0x01) << 5;
242 printf("serial: read addr=0x%02x val=0x%02x\n", addr
, ret
);
247 int serial_can_receive(void)
249 SerialState
*s
= &serial_ports
[0];
250 return !(s
->lsr
& UART_LSR_DR
);
253 void serial_receive_byte(int ch
)
255 SerialState
*s
= &serial_ports
[0];
258 s
->lsr
|= UART_LSR_DR
;
262 void serial_receive_break(void)
264 SerialState
*s
= &serial_ports
[0];
267 s
->lsr
|= UART_LSR_BI
| UART_LSR_DR
;
271 void serial_init(int base
, int irq
)
273 SerialState
*s
= &serial_ports
[0];
276 s
->lsr
= UART_LSR_TEMT
| UART_LSR_THRE
;
277 s
->iir
= UART_IIR_NO_INT
;
279 register_ioport_write(base
, 8, serial_ioport_write
, 1);
280 register_ioport_read(base
, 8, serial_ioport_read
, 1);