hw/serial.c

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "qemu-char.h"
  27 #include "isa.h"
  28 #include "pc.h"
  29 #include "qemu-timer.h"
  30
  31 //#define DEBUG_SERIAL
  32
  33 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  34
  35 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  36 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  37 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  38 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  39
  40 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  41 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  42
  43 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  44 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  45 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  46 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  47 #define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  48
  49 #define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  50 #define UART_IIR_FE     0xC0    /* Fifo enabled */
  51
  52 /*
  53  * These are the definitions for the Modem Control Register
  54  */
  55 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  56 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  57 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  58 #define UART_MCR_RTS    0x02    /* RTS complement */
  59 #define UART_MCR_DTR    0x01    /* DTR complement */
  60
  61 /*
  62  * These are the definitions for the Modem Status Register
  63  */
  64 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  65 #define UART_MSR_RI     0x40    /* Ring Indicator */
  66 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  67 #define UART_MSR_CTS    0x10    /* Clear to Send */
  68 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  69 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  70 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  71 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  72 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  73
  74 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  75 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  76 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  77 #define UART_LSR_FE     0x08    /* Frame error indicator */
  78 #define UART_LSR_PE     0x04    /* Parity error indicator */
  79 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  80 #define UART_LSR_DR     0x01    /* Receiver data ready */
  81 #define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  82
  83 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  84
  85 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  86 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  87 #define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  88 #define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  89
  90 #define UART_FCR_DMS        0x08    /* DMA Mode Select */
  91 #define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  92 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  93 #define UART_FCR_FE         0x01    /* FIFO Enable */
  94
  95 #define UART_FIFO_LENGTH    16      /* 16550A Fifo Length */
  96
  97 #define XMIT_FIFO           0
  98 #define RECV_FIFO           1
  99 #define MAX_XMIT_RETRY      4
 100
 101 typedef struct SerialFIFO {
 102     uint8_t data[UART_FIFO_LENGTH];
 103     uint8_t count;
 104     uint8_t itl;                        /* Interrupt Trigger Level */
 105     uint8_t tail;
 106     uint8_t head;
 107 } SerialFIFO;
 108
 109 struct SerialState {
 110     uint16_t divider;
 111     uint8_t rbr; /* receive register */
 112     uint8_t thr; /* transmit holding register */
 113     uint8_t tsr; /* transmit shift register */
 114     uint8_t ier;
 115     uint8_t iir; /* read only */
 116     uint8_t lcr;
 117     uint8_t mcr;
 118     uint8_t lsr; /* read only */
 119     uint8_t msr; /* read only */
 120     uint8_t scr;
 121     uint8_t fcr;
 122     uint8_t fcr_vmstate; /* we can't write directly this value
 123                             it has side effects */
 124     /* NOTE: this hidden state is necessary for tx irq generation as
 125        it can be reset while reading iir */
 126     int thr_ipending;
 127     qemu_irq irq;
 128     CharDriverState *chr;
 129     int last_break_enable;
 130     int it_shift;
 131     int baudbase;
 132     int tsr_retry;
 133
 134     uint64_t last_xmit_ts;              /* Time when the last byte was successfully sent out of the tsr */
 135     SerialFIFO recv_fifo;
 136     SerialFIFO xmit_fifo;
 137
 138     struct QEMUTimer *fifo_timeout_timer;
 139     int timeout_ipending;                   /* timeout interrupt pending state */
 140     struct QEMUTimer *transmit_timer;
 141
 142
 143     uint64_t char_transmit_time;               /* time to transmit a char in ticks*/
 144     int poll_msl;
 145
 146     struct QEMUTimer *modem_status_poll;
 147 };
 148
 149 typedef struct ISASerialState {
 150     ISADevice dev;
 151     uint32_t index;
 152     uint32_t iobase;
 153     uint32_t isairq;
 154     SerialState state;
 155 } ISASerialState;
 156
 157 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 158
 159 static void fifo_clear(SerialState *s, int fifo)
 160 {
 161     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 162     memset(f->data, 0, UART_FIFO_LENGTH);
 163     f->count = 0;
 164     f->head = 0;
 165     f->tail = 0;
 166 }
 167
 168 static int fifo_put(SerialState *s, int fifo, uint8_t chr)
 169 {
 170     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 171
 172     f->data[f->head++] = chr;
 173
 174     if (f->head == UART_FIFO_LENGTH)
 175         f->head = 0;
 176     f->count++;
 177
 178     return 1;
 179 }
 180
 181 static uint8_t fifo_get(SerialState *s, int fifo)
 182 {
 183     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 184     uint8_t c;
 185
 186     if(f->count == 0)
 187         return 0;
 188
 189     c = f->data[f->tail++];
 190     if (f->tail == UART_FIFO_LENGTH)
 191         f->tail = 0;
 192     f->count--;
 193
 194     return c;
 195 }
 196
 197 static void serial_update_irq(SerialState *s)
 198 {
 199     uint8_t tmp_iir = UART_IIR_NO_INT;
 200
 201     if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 202         tmp_iir = UART_IIR_RLSI;
 203     } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 204         /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
 205          * this is not in the specification but is observed on existing
 206          * hardware.  */
 207         tmp_iir = UART_IIR_CTI;
 208     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
 209                (!(s->fcr & UART_FCR_FE) ||
 210                 s->recv_fifo.count >= s->recv_fifo.itl)) {
 211         tmp_iir = UART_IIR_RDI;
 212     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 213         tmp_iir = UART_IIR_THRI;
 214     } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 215         tmp_iir = UART_IIR_MSI;
 216     }
 217
 218     s->iir = tmp_iir | (s->iir & 0xF0);
 219
 220     if (tmp_iir != UART_IIR_NO_INT) {
 221         qemu_irq_raise(s->irq);
 222     } else {
 223         qemu_irq_lower(s->irq);
 224     }
 225 }
 226
 227 static void serial_update_parameters(SerialState *s)
 228 {
 229     int speed, parity, data_bits, stop_bits, frame_size;
 230     QEMUSerialSetParams ssp;
 231
 232     if (s->divider == 0)
 233         return;
 234
 235     frame_size = 1;
 236     if (s->lcr & 0x08) {
 237         if (s->lcr & 0x10)
 238             parity = 'E';
 239         else
 240             parity = 'O';
 241     } else {
 242             parity = 'N';
 243             frame_size = 0;
 244     }
 245     if (s->lcr & 0x04)
 246         stop_bits = 2;
 247     else
 248         stop_bits = 1;
 249
 250     data_bits = (s->lcr & 0x03) + 5;
 251     frame_size += data_bits + stop_bits;
 252     speed = s->baudbase / s->divider;
 253     ssp.speed = speed;
 254     ssp.parity = parity;
 255     ssp.data_bits = data_bits;
 256     ssp.stop_bits = stop_bits;
 257     s->char_transmit_time =  (get_ticks_per_sec() / speed) * frame_size;
 258     qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 259 #if 0
 260     printf("speed=%d parity=%c data=%d stop=%d\n",
 261            speed, parity, data_bits, stop_bits);
 262 #endif
 263 }
 264
 265 static void serial_update_msl(SerialState *s)
 266 {
 267     uint8_t omsr;
 268     int flags;
 269
 270     qemu_del_timer(s->modem_status_poll);
 271
 272     if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
 273         s->poll_msl = -1;
 274         return;
 275     }
 276
 277     omsr = s->msr;
 278
 279     s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 280     s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 281     s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 282     s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 283
 284     if (s->msr != omsr) {
 285          /* Set delta bits */
 286          s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 287          /* UART_MSR_TERI only if change was from 1 -> 0 */
 288          if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 289              s->msr &= ~UART_MSR_TERI;
 290          serial_update_irq(s);
 291     }
 292
 293     /* The real 16550A apparently has a 250ns response latency to line status changes.
 294        We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 295
 296     if (s->poll_msl)
 297         qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + get_ticks_per_sec() / 100);
 298 }
 299
 300 static void serial_xmit(void *opaque)
 301 {
 302     SerialState *s = opaque;
 303     uint64_t new_xmit_ts = qemu_get_clock(vm_clock);
 304
 305     if (s->tsr_retry <= 0) {
 306         if (s->fcr & UART_FCR_FE) {
 307             s->tsr = fifo_get(s,XMIT_FIFO);
 308             if (!s->xmit_fifo.count)
 309                 s->lsr |= UART_LSR_THRE;
 310         } else {
 311             s->tsr = s->thr;
 312             s->lsr |= UART_LSR_THRE;
 313         }
 314     }
 315
 316     if (s->mcr & UART_MCR_LOOP) {
 317         /* in loopback mode, say that we just received a char */
 318         serial_receive1(s, &s->tsr, 1);
 319     } else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) {
 320         if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
 321             s->tsr_retry++;
 322             qemu_mod_timer(s->transmit_timer,  new_xmit_ts + s->char_transmit_time);
 323             return;
 324         } else if (s->poll_msl < 0) {
 325             /* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
 326             drop any further failed writes instantly, until we get one that goes through.
 327             This is to prevent guests that log to unconnected pipes or pty's from stalling. */
 328             s->tsr_retry = -1;
 329         }
 330     }
 331     else {
 332         s->tsr_retry = 0;
 333     }
 334
 335     s->last_xmit_ts = qemu_get_clock(vm_clock);
 336     if (!(s->lsr & UART_LSR_THRE))
 337         qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time);
 338
 339     if (s->lsr & UART_LSR_THRE) {
 340         s->lsr |= UART_LSR_TEMT;
 341         s->thr_ipending = 1;
 342         serial_update_irq(s);
 343     }
 344 }
 345
 346
 347 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 348 {
 349     SerialState *s = opaque;
 350
 351     addr &= 7;
 352 #ifdef DEBUG_SERIAL
 353     printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
 354 #endif
 355     switch(addr) {
 356     default:
 357     case 0:
 358         if (s->lcr & UART_LCR_DLAB) {
 359             s->divider = (s->divider & 0xff00) | val;
 360             serial_update_parameters(s);
 361         } else {
 362             s->thr = (uint8_t) val;
 363             if(s->fcr & UART_FCR_FE) {
 364                   fifo_put(s, XMIT_FIFO, s->thr);
 365             s->thr_ipending = 0;
 366                   s->lsr &= ~UART_LSR_TEMT;
 367             s->lsr &= ~UART_LSR_THRE;
 368             serial_update_irq(s);
 369             } else {
 370                   s->thr_ipending = 0;
 371                   s->lsr &= ~UART_LSR_THRE;
 372                   serial_update_irq(s);
 373             }
 374             serial_xmit(s);
 375         }
 376         break;
 377     case 1:
 378         if (s->lcr & UART_LCR_DLAB) {
 379             s->divider = (s->divider & 0x00ff) | (val << 8);
 380             serial_update_parameters(s);
 381         } else {
 382             s->ier = val & 0x0f;
 383             /* If the backend device is a real serial port, turn polling of the modem
 384                status lines on physical port on or off depending on UART_IER_MSI state */
 385             if (s->poll_msl >= 0) {
 386                 if (s->ier & UART_IER_MSI) {
 387                      s->poll_msl = 1;
 388                      serial_update_msl(s);
 389                 } else {
 390                      qemu_del_timer(s->modem_status_poll);
 391                      s->poll_msl = 0;
 392                 }
 393             }
 394             if (s->lsr & UART_LSR_THRE) {
 395                 s->thr_ipending = 1;
 396                 serial_update_irq(s);
 397             }
 398         }
 399         break;
 400     case 2:
 401         val = val & 0xFF;
 402
 403         if (s->fcr == val)
 404             break;
 405
 406         /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 407         if ((val ^ s->fcr) & UART_FCR_FE)
 408             val |= UART_FCR_XFR | UART_FCR_RFR;
 409
 410         /* FIFO clear */
 411
 412         if (val & UART_FCR_RFR) {
 413             qemu_del_timer(s->fifo_timeout_timer);
 414             s->timeout_ipending=0;
 415             fifo_clear(s,RECV_FIFO);
 416         }
 417
 418         if (val & UART_FCR_XFR) {
 419             fifo_clear(s,XMIT_FIFO);
 420         }
 421
 422         if (val & UART_FCR_FE) {
 423             s->iir |= UART_IIR_FE;
 424             /* Set RECV_FIFO trigger Level */
 425             switch (val & 0xC0) {
 426             case UART_FCR_ITL_1:
 427                 s->recv_fifo.itl = 1;
 428                 break;
 429             case UART_FCR_ITL_2:
 430                 s->recv_fifo.itl = 4;
 431                 break;
 432             case UART_FCR_ITL_3:
 433                 s->recv_fifo.itl = 8;
 434                 break;
 435             case UART_FCR_ITL_4:
 436                 s->recv_fifo.itl = 14;
 437                 break;
 438             }
 439         } else
 440             s->iir &= ~UART_IIR_FE;
 441
 442         /* Set fcr - or at least the bits in it that are supposed to "stick" */
 443         s->fcr = val & 0xC9;
 444         serial_update_irq(s);
 445         break;
 446     case 3:
 447         {
 448             int break_enable;
 449             s->lcr = val;
 450             serial_update_parameters(s);
 451             break_enable = (val >> 6) & 1;
 452             if (break_enable != s->last_break_enable) {
 453                 s->last_break_enable = break_enable;
 454                 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 455                                &break_enable);
 456             }
 457         }
 458         break;
 459     case 4:
 460         {
 461             int flags;
 462             int old_mcr = s->mcr;
 463             s->mcr = val & 0x1f;
 464             if (val & UART_MCR_LOOP)
 465                 break;
 466
 467             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 468
 469                 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 470
 471                 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 472
 473                 if (val & UART_MCR_RTS)
 474                     flags |= CHR_TIOCM_RTS;
 475                 if (val & UART_MCR_DTR)
 476                     flags |= CHR_TIOCM_DTR;
 477
 478                 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 479                 /* Update the modem status after a one-character-send wait-time, since there may be a response
 480                    from the device/computer at the other end of the serial line */
 481                 qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time);
 482             }
 483         }
 484         break;
 485     case 5:
 486         break;
 487     case 6:
 488         break;
 489     case 7:
 490         s->scr = val;
 491         break;
 492     }
 493 }
 494
 495 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
 496 {
 497     SerialState *s = opaque;
 498     uint32_t ret;
 499
 500     addr &= 7;
 501     switch(addr) {
 502     default:
 503     case 0:
 504         if (s->lcr & UART_LCR_DLAB) {
 505             ret = s->divider & 0xff;
 506         } else {
 507             if(s->fcr & UART_FCR_FE) {
 508                 ret = fifo_get(s,RECV_FIFO);
 509                 if (s->recv_fifo.count == 0)
 510                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 511                 else
 512                     qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
 513                 s->timeout_ipending = 0;
 514             } else {
 515                 ret = s->rbr;
 516                 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 517             }
 518             serial_update_irq(s);
 519             if (!(s->mcr & UART_MCR_LOOP)) {
 520                 /* in loopback mode, don't receive any data */
 521                 qemu_chr_accept_input(s->chr);
 522             }
 523         }
 524         break;
 525     case 1:
 526         if (s->lcr & UART_LCR_DLAB) {
 527             ret = (s->divider >> 8) & 0xff;
 528         } else {
 529             ret = s->ier;
 530         }
 531         break;
 532     case 2:
 533         ret = s->iir;
 534             s->thr_ipending = 0;
 535         serial_update_irq(s);
 536         break;
 537     case 3:
 538         ret = s->lcr;
 539         break;
 540     case 4:
 541         ret = s->mcr;
 542         break;
 543     case 5:
 544         ret = s->lsr;
 545         /* Clear break interrupt */
 546         if (s->lsr & UART_LSR_BI) {
 547             s->lsr &= ~UART_LSR_BI;
 548             serial_update_irq(s);
 549         }
 550         break;
 551     case 6:
 552         if (s->mcr & UART_MCR_LOOP) {
 553             /* in loopback, the modem output pins are connected to the
 554                inputs */
 555             ret = (s->mcr & 0x0c) << 4;
 556             ret |= (s->mcr & 0x02) << 3;
 557             ret |= (s->mcr & 0x01) << 5;
 558         } else {
 559             if (s->poll_msl >= 0)
 560                 serial_update_msl(s);
 561             ret = s->msr;
 562             /* Clear delta bits & msr int after read, if they were set */
 563             if (s->msr & UART_MSR_ANY_DELTA) {
 564                 s->msr &= 0xF0;
 565                 serial_update_irq(s);
 566             }
 567         }
 568         break;
 569     case 7:
 570         ret = s->scr;
 571         break;
 572     }
 573 #ifdef DEBUG_SERIAL
 574     printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
 575 #endif
 576     return ret;
 577 }
 578
 579 static int serial_can_receive(SerialState *s)
 580 {
 581     if(s->fcr & UART_FCR_FE) {
 582         if(s->recv_fifo.count < UART_FIFO_LENGTH)
 583         /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
 584         advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
 585         effectively overriding the ITL that the guest has set. */
 586              return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
 587         else
 588              return 0;
 589     } else {
 590     return !(s->lsr & UART_LSR_DR);
 591     }
 592 }
 593
 594 static void serial_receive_break(SerialState *s)
 595 {
 596     s->rbr = 0;
 597     /* When the LSR_DR is set a null byte is pushed into the fifo */
 598     fifo_put(s, RECV_FIFO, '\0');
 599     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 600     serial_update_irq(s);
 601 }
 602
 603 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 604 static void fifo_timeout_int (void *opaque) {
 605     SerialState *s = opaque;
 606     if (s->recv_fifo.count) {
 607         s->timeout_ipending = 1;
 608         serial_update_irq(s);
 609     }
 610 }
 611
 612 static int serial_can_receive1(void *opaque)
 613 {
 614     SerialState *s = opaque;
 615     return serial_can_receive(s);
 616 }
 617
 618 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 619 {
 620     SerialState *s = opaque;
 621     if(s->fcr & UART_FCR_FE) {
 622         int i;
 623         for (i = 0; i < size; i++) {
 624             fifo_put(s, RECV_FIFO, buf[i]);
 625         }
 626         s->lsr |= UART_LSR_DR;
 627         /* call the timeout receive callback in 4 char transmit time */
 628         qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
 629     } else {
 630         s->rbr = buf[0];
 631         s->lsr |= UART_LSR_DR;
 632     }
 633     serial_update_irq(s);
 634 }
 635
 636 static void serial_event(void *opaque, int event)
 637 {
 638     SerialState *s = opaque;
 639 #ifdef DEBUG_SERIAL
 640     printf("serial: event %x\n", event);
 641 #endif
 642     if (event == CHR_EVENT_BREAK)
 643         serial_receive_break(s);
 644 }
 645
 646 static void serial_pre_save(void *opaque)
 647 {
 648     SerialState *s = opaque;
 649     s->fcr_vmstate = s->fcr;
 650 }
 651
 652 static int serial_post_load(void *opaque, int version_id)
 653 {
 654     SerialState *s = opaque;
 655
 656     if (version_id < 3) {
 657         s->fcr_vmstate = 0;
 658     }
 659     /* Initialize fcr via setter to perform essential side-effects */
 660     serial_ioport_write(s, 0x02, s->fcr_vmstate);
 661     return 0;
 662 }
 663
 664 static const VMStateDescription vmstate_serial = {
 665     .name = "serial",
 666     .version_id = 3,
 667     .minimum_version_id = 2,
 668     .pre_save = serial_pre_save,
 669     .post_load = serial_post_load,
 670     .fields      = (VMStateField []) {
 671         VMSTATE_UINT16_V(divider, SerialState, 2),
 672         VMSTATE_UINT8(rbr, SerialState),
 673         VMSTATE_UINT8(ier, SerialState),
 674         VMSTATE_UINT8(iir, SerialState),
 675         VMSTATE_UINT8(lcr, SerialState),
 676         VMSTATE_UINT8(mcr, SerialState),
 677         VMSTATE_UINT8(lsr, SerialState),
 678         VMSTATE_UINT8(msr, SerialState),
 679         VMSTATE_UINT8(scr, SerialState),
 680         VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
 681         VMSTATE_END_OF_LIST()
 682     }
 683 };
 684
 685 static void serial_reset(void *opaque)
 686 {
 687     SerialState *s = opaque;
 688
 689     s->rbr = 0;
 690     s->ier = 0;
 691     s->iir = UART_IIR_NO_INT;
 692     s->lcr = 0;
 693     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 694     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 695     /* Default to 9600 baud, no parity, one stop bit */
 696     s->divider = 0x0C;
 697     s->mcr = UART_MCR_OUT2;
 698     s->scr = 0;
 699     s->tsr_retry = 0;
 700     s->char_transmit_time = (get_ticks_per_sec() / 9600) * 9;
 701     s->poll_msl = 0;
 702
 703     fifo_clear(s,RECV_FIFO);
 704     fifo_clear(s,XMIT_FIFO);
 705
 706     s->last_xmit_ts = qemu_get_clock(vm_clock);
 707
 708     s->thr_ipending = 0;
 709     s->last_break_enable = 0;
 710     qemu_irq_lower(s->irq);
 711 }
 712
 713 static void serial_init_core(SerialState *s)
 714 {
 715     if (!s->chr) {
 716         fprintf(stderr, "Can't create serial device, empty char device\n");
 717         exit(1);
 718     }
 719
 720     s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
 721
 722     s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
 723     s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s);
 724
 725     qemu_register_reset(serial_reset, s);
 726     serial_reset(s);
 727
 728     qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
 729                           serial_event, s);
 730 }
 731
 732 static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 733 static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 734
 735 static int serial_isa_initfn(ISADevice *dev)
 736 {
 737     static int index;
 738     ISASerialState *isa = DO_UPCAST(ISASerialState, dev, dev);
 739     SerialState *s = &isa->state;
 740
 741     if (isa->index == -1)
 742         isa->index = index;
 743     if (isa->index >= MAX_SERIAL_PORTS)
 744         return -1;
 745     if (isa->iobase == -1)
 746         isa->iobase = isa_serial_io[isa->index];
 747     if (isa->isairq == -1)
 748         isa->isairq = isa_serial_irq[isa->index];
 749     index++;
 750
 751     s->baudbase = 115200;
 752     isa_init_irq(dev, &s->irq, isa->isairq);
 753     serial_init_core(s);
 754     vmstate_register(isa->iobase, &vmstate_serial, s);
 755
 756     register_ioport_write(isa->iobase, 8, 1, serial_ioport_write, s);
 757     register_ioport_read(isa->iobase, 8, 1, serial_ioport_read, s);
 758     return 0;
 759 }
 760
 761 SerialState *serial_isa_init(int index, CharDriverState *chr)
 762 {
 763     ISADevice *dev;
 764
 765     dev = isa_create("isa-serial");
 766     qdev_prop_set_uint32(&dev->qdev, "index", index);
 767     qdev_prop_set_chr(&dev->qdev, "chardev", chr);
 768     if (qdev_init(&dev->qdev) < 0)
 769         return NULL;
 770     return &DO_UPCAST(ISASerialState, dev, dev)->state;
 771 }
 772
 773 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 774                          CharDriverState *chr)
 775 {
 776     SerialState *s;
 777
 778     s = qemu_mallocz(sizeof(SerialState));
 779
 780     s->irq = irq;
 781     s->baudbase = baudbase;
 782     s->chr = chr;
 783     serial_init_core(s);
 784
 785     vmstate_register(base, &vmstate_serial, s);
 786
 787     register_ioport_write(base, 8, 1, serial_ioport_write, s);
 788     register_ioport_read(base, 8, 1, serial_ioport_read, s);
 789     return s;
 790 }
 791
 792 /* Memory mapped interface */
 793 static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr)
 794 {
 795     SerialState *s = opaque;
 796
 797     return serial_ioport_read(s, addr >> s->it_shift) & 0xFF;
 798 }
 799
 800 static void serial_mm_writeb(void *opaque, target_phys_addr_t addr,
 801                              uint32_t value)
 802 {
 803     SerialState *s = opaque;
 804
 805     serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
 806 }
 807
 808 static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr)
 809 {
 810     SerialState *s = opaque;
 811     uint32_t val;
 812
 813     val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
 814 #ifdef TARGET_WORDS_BIGENDIAN
 815     val = bswap16(val);
 816 #endif
 817     return val;
 818 }
 819
 820 static void serial_mm_writew(void *opaque, target_phys_addr_t addr,
 821                              uint32_t value)
 822 {
 823     SerialState *s = opaque;
 824 #ifdef TARGET_WORDS_BIGENDIAN
 825     value = bswap16(value);
 826 #endif
 827     serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
 828 }
 829
 830 static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr)
 831 {
 832     SerialState *s = opaque;
 833     uint32_t val;
 834
 835     val = serial_ioport_read(s, addr >> s->it_shift);
 836 #ifdef TARGET_WORDS_BIGENDIAN
 837     val = bswap32(val);
 838 #endif
 839     return val;
 840 }
 841
 842 static void serial_mm_writel(void *opaque, target_phys_addr_t addr,
 843                              uint32_t value)
 844 {
 845     SerialState *s = opaque;
 846 #ifdef TARGET_WORDS_BIGENDIAN
 847     value = bswap32(value);
 848 #endif
 849     serial_ioport_write(s, addr >> s->it_shift, value);
 850 }
 851
 852 static CPUReadMemoryFunc * const serial_mm_read[] = {
 853     &serial_mm_readb,
 854     &serial_mm_readw,
 855     &serial_mm_readl,
 856 };
 857
 858 static CPUWriteMemoryFunc * const serial_mm_write[] = {
 859     &serial_mm_writeb,
 860     &serial_mm_writew,
 861     &serial_mm_writel,
 862 };
 863
 864 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
 865                              qemu_irq irq, int baudbase,
 866                              CharDriverState *chr, int ioregister)
 867 {
 868     SerialState *s;
 869     int s_io_memory;
 870
 871     s = qemu_mallocz(sizeof(SerialState));
 872
 873     s->it_shift = it_shift;
 874     s->irq = irq;
 875     s->baudbase = baudbase;
 876     s->chr = chr;
 877
 878     serial_init_core(s);
 879     vmstate_register(base, &vmstate_serial, s);
 880
 881     if (ioregister) {
 882         s_io_memory = cpu_register_io_memory(serial_mm_read,
 883                                              serial_mm_write, s);
 884         cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
 885     }
 886     serial_update_msl(s);
 887     return s;
 888 }
 889
 890 static ISADeviceInfo serial_isa_info = {
 891     .qdev.name  = "isa-serial",
 892     .qdev.size  = sizeof(ISASerialState),
 893     .init       = serial_isa_initfn,
 894     .qdev.props = (Property[]) {
 895         DEFINE_PROP_HEX32("index",  ISASerialState, index,   -1),
 896         DEFINE_PROP_HEX32("iobase", ISASerialState, iobase,  -1),
 897         DEFINE_PROP_UINT32("irq",   ISASerialState, isairq,  -1),
 898         DEFINE_PROP_CHR("chardev",  ISASerialState, state.chr),
 899         DEFINE_PROP_END_OF_LIST(),
 900     },
 901 };
 902
 903 static void serial_register_devices(void)
 904 {
 905     isa_qdev_register(&serial_isa_info);
 906 }
 907
 908 device_init(serial_register_devices)