hw/serial.h

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw.h"
  27 #include "sysemu.h"
  28 #include "memory.h"
  29
  30 #define UART_FIFO_LENGTH    16      /* 16550A Fifo Length */
  31
  32 typedef struct SerialFIFO {
  33     uint8_t data[UART_FIFO_LENGTH];
  34     uint8_t count;
  35     uint8_t itl;                        /* Interrupt Trigger Level */
  36     uint8_t tail;
  37     uint8_t head;
  38 } SerialFIFO;
  39
  40 struct SerialState {
  41     uint16_t divider;
  42     uint8_t rbr; /* receive register */
  43     uint8_t thr; /* transmit holding register */
  44     uint8_t tsr; /* transmit shift register */
  45     uint8_t ier;
  46     uint8_t iir; /* read only */
  47     uint8_t lcr;
  48     uint8_t mcr;
  49     uint8_t lsr; /* read only */
  50     uint8_t msr; /* read only */
  51     uint8_t scr;
  52     uint8_t fcr;
  53     uint8_t fcr_vmstate; /* we can't write directly this value
  54                             it has side effects */
  55     /* NOTE: this hidden state is necessary for tx irq generation as
  56        it can be reset while reading iir */
  57     int thr_ipending;
  58     qemu_irq irq;
  59     CharDriverState *chr;
  60     int last_break_enable;
  61     int it_shift;
  62     int baudbase;
  63     int tsr_retry;
  64     uint32_t wakeup;
  65
  66     /* Time when the last byte was successfully sent out of the tsr */
  67     uint64_t last_xmit_ts;
  68     SerialFIFO recv_fifo;
  69     SerialFIFO xmit_fifo;
  70
  71     struct QEMUTimer *fifo_timeout_timer;
  72     int timeout_ipending;           /* timeout interrupt pending state */
  73     struct QEMUTimer *transmit_timer;
  74
  75
  76     uint64_t char_transmit_time;    /* time to transmit a char in ticks */
  77     int poll_msl;
  78
  79     struct QEMUTimer *modem_status_poll;
  80     MemoryRegion io;
  81 };
  82
  83 extern const VMStateDescription vmstate_serial;
  84 extern const MemoryRegionOps serial_io_ops;
  85
  86 void serial_init_core(SerialState *s);
  87 void serial_exit_core(SerialState *s);
  88 void serial_set_frequency(SerialState *s, uint32_t frequency);
  89
  90 /* legacy pre qom */
  91 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
  92                          CharDriverState *chr, MemoryRegion *system_io);
  93 SerialState *serial_mm_init(MemoryRegion *address_space,
  94                             hwaddr base, int it_shift,
  95                             qemu_irq irq, int baudbase,
  96                             CharDriverState *chr, enum device_endian end);
  97
  98 /* serial-isa.c */
  99 bool serial_isa_init(ISABus *bus, int index, CharDriverState *chr);