hw/sh4/r2d.c

   1 /*
   2  * Renesas SH7751R R2D-PLUS emulation
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Copyright (c) 2008 Paul Mundt
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw/sysbus.h"
  27 #include "hw/hw.h"
  28 #include "hw/sh4/sh.h"
  29 #include "hw/devices.h"
  30 #include "sysemu/sysemu.h"
  31 #include "hw/boards.h"
  32 #include "hw/pci/pci.h"
  33 #include "net/net.h"
  34 #include "sh7750_regs.h"
  35 #include "hw/ide.h"
  36 #include "hw/loader.h"
  37 #include "hw/usb.h"
  38 #include "hw/block/flash.h"
  39 #include "sysemu/block-backend.h"
  40 #include "sysemu/blockdev.h"
  41 #include "exec/address-spaces.h"
  42
  43 #define FLASH_BASE 0x00000000
  44 #define FLASH_SIZE 0x02000000
  45
  46 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
  47 #define SDRAM_SIZE 0x04000000
  48
  49 #define SM501_VRAM_SIZE 0x800000
  50
  51 #define BOOT_PARAMS_OFFSET 0x0010000
  52 /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
  53 #define LINUX_LOAD_OFFSET  0x0800000
  54 #define INITRD_LOAD_OFFSET 0x1800000
  55
  56 #define PA_IRLMSK       0x00
  57 #define PA_POWOFF       0x30
  58 #define PA_VERREG       0x32
  59 #define PA_OUTPORT      0x36
  60
  61 typedef struct {
  62     uint16_t bcr;
  63     uint16_t irlmsk;
  64     uint16_t irlmon;
  65     uint16_t cfctl;
  66     uint16_t cfpow;
  67     uint16_t dispctl;
  68     uint16_t sdmpow;
  69     uint16_t rtcce;
  70     uint16_t pcicd;
  71     uint16_t voyagerrts;
  72     uint16_t cfrst;
  73     uint16_t admrts;
  74     uint16_t extrst;
  75     uint16_t cfcdintclr;
  76     uint16_t keyctlclr;
  77     uint16_t pad0;
  78     uint16_t pad1;
  79     uint16_t verreg;
  80     uint16_t inport;
  81     uint16_t outport;
  82     uint16_t bverreg;
  83
  84 /* output pin */
  85     qemu_irq irl;
  86     MemoryRegion iomem;
  87 } r2d_fpga_t;
  88
  89 enum r2d_fpga_irq {
  90     PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
  91     SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
  92     NR_IRQS
  93 };
  94
  95 static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
  96     [CF_IDE]    = {  1, 1<<9 },
  97     [CF_CD]     = {  2, 1<<8 },
  98     [PCI_INTA]  = {  9, 1<<14 },
  99     [PCI_INTB]  = { 10, 1<<13 },
 100     [PCI_INTC]  = {  3, 1<<12 },
 101     [PCI_INTD]  = {  0, 1<<11 },
 102     [SM501]     = {  4, 1<<10 },
 103     [KEY]       = {  5, 1<<6 },
 104     [RTC_A]     = {  6, 1<<5 },
 105     [RTC_T]     = {  7, 1<<4 },
 106     [SDCARD]    = {  8, 1<<7 },
 107     [EXT]       = { 11, 1<<0 },
 108     [TP]        = { 12, 1<<15 },
 109 };
 110
 111 static void update_irl(r2d_fpga_t *fpga)
 112 {
 113     int i, irl = 15;
 114     for (i = 0; i < NR_IRQS; i++)
 115         if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
 116             if (irqtab[i].irl < irl)
 117                 irl = irqtab[i].irl;
 118     qemu_set_irq(fpga->irl, irl ^ 15);
 119 }
 120
 121 static void r2d_fpga_irq_set(void *opaque, int n, int level)
 122 {
 123     r2d_fpga_t *fpga = opaque;
 124     if (level)
 125         fpga->irlmon |= irqtab[n].msk;
 126     else
 127         fpga->irlmon &= ~irqtab[n].msk;
 128     update_irl(fpga);
 129 }
 130
 131 static uint32_t r2d_fpga_read(void *opaque, hwaddr addr)
 132 {
 133     r2d_fpga_t *s = opaque;
 134
 135     switch (addr) {
 136     case PA_IRLMSK:
 137         return s->irlmsk;
 138     case PA_OUTPORT:
 139         return s->outport;
 140     case PA_POWOFF:
 141         return 0x00;
 142     case PA_VERREG:
 143         return 0x10;
 144     }
 145
 146     return 0;
 147 }
 148
 149 static void
 150 r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value)
 151 {
 152     r2d_fpga_t *s = opaque;
 153
 154     switch (addr) {
 155     case PA_IRLMSK:
 156         s->irlmsk = value;
 157         update_irl(s);
 158         break;
 159     case PA_OUTPORT:
 160         s->outport = value;
 161         break;
 162     case PA_POWOFF:
 163         if (value & 1) {
 164             qemu_system_shutdown_request();
 165         }
 166         break;
 167     case PA_VERREG:
 168         /* Discard writes */
 169         break;
 170     }
 171 }
 172
 173 static const MemoryRegionOps r2d_fpga_ops = {
 174     .old_mmio = {
 175         .read = { r2d_fpga_read, r2d_fpga_read, NULL, },
 176         .write = { r2d_fpga_write, r2d_fpga_write, NULL, },
 177     },
 178     .endianness = DEVICE_NATIVE_ENDIAN,
 179 };
 180
 181 static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
 182                                hwaddr base, qemu_irq irl)
 183 {
 184     r2d_fpga_t *s;
 185
 186     s = g_malloc0(sizeof(r2d_fpga_t));
 187
 188     s->irl = irl;
 189
 190     memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
 191     memory_region_add_subregion(sysmem, base, &s->iomem);
 192     return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
 193 }
 194
 195 typedef struct ResetData {
 196     SuperHCPU *cpu;
 197     uint32_t vector;
 198 } ResetData;
 199
 200 static void main_cpu_reset(void *opaque)
 201 {
 202     ResetData *s = (ResetData *)opaque;
 203     CPUSH4State *env = &s->cpu->env;
 204
 205     cpu_reset(CPU(s->cpu));
 206     env->pc = s->vector;
 207 }
 208
 209 static struct QEMU_PACKED
 210 {
 211     int mount_root_rdonly;
 212     int ramdisk_flags;
 213     int orig_root_dev;
 214     int loader_type;
 215     int initrd_start;
 216     int initrd_size;
 217
 218     char pad[232];
 219
 220     char kernel_cmdline[256];
 221 } boot_params;
 222
 223 static void r2d_init(MachineState *machine)
 224 {
 225     const char *cpu_model = machine->cpu_model;
 226     const char *kernel_filename = machine->kernel_filename;
 227     const char *kernel_cmdline = machine->kernel_cmdline;
 228     const char *initrd_filename = machine->initrd_filename;
 229     SuperHCPU *cpu;
 230     CPUSH4State *env;
 231     ResetData *reset_info;
 232     struct SH7750State *s;
 233     MemoryRegion *sdram = g_new(MemoryRegion, 1);
 234     qemu_irq *irq;
 235     DriveInfo *dinfo;
 236     int i;
 237     DeviceState *dev;
 238     SysBusDevice *busdev;
 239     MemoryRegion *address_space_mem = get_system_memory();
 240     PCIBus *pci_bus;
 241
 242     if (cpu_model == NULL) {
 243         cpu_model = "SH7751R";
 244     }
 245
 246     cpu = cpu_sh4_init(cpu_model);
 247     if (cpu == NULL) {
 248         fprintf(stderr, "Unable to find CPU definition\n");
 249         exit(1);
 250     }
 251     env = &cpu->env;
 252
 253     reset_info = g_malloc0(sizeof(ResetData));
 254     reset_info->cpu = cpu;
 255     reset_info->vector = env->pc;
 256     qemu_register_reset(main_cpu_reset, reset_info);
 257
 258     /* Allocate memory space */
 259     memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE, &error_abort);
 260     vmstate_register_ram_global(sdram);
 261     memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
 262     /* Register peripherals */
 263     s = sh7750_init(cpu, address_space_mem);
 264     irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
 265
 266     dev = qdev_create(NULL, "sh_pci");
 267     busdev = SYS_BUS_DEVICE(dev);
 268     qdev_init_nofail(dev);
 269     pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
 270     sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
 271     sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
 272     sysbus_connect_irq(busdev, 0, irq[PCI_INTA]);
 273     sysbus_connect_irq(busdev, 1, irq[PCI_INTB]);
 274     sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
 275     sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);
 276
 277     sm501_init(address_space_mem, 0x10000000, SM501_VRAM_SIZE,
 278                irq[SM501], serial_hds[2]);
 279
 280     /* onboard CF (True IDE mode, Master only). */
 281     dinfo = drive_get(IF_IDE, 0, 0);
 282     dev = qdev_create(NULL, "mmio-ide");
 283     busdev = SYS_BUS_DEVICE(dev);
 284     sysbus_connect_irq(busdev, 0, irq[CF_IDE]);
 285     qdev_prop_set_uint32(dev, "shift", 1);
 286     qdev_init_nofail(dev);
 287     sysbus_mmio_map(busdev, 0, 0x14001000);
 288     sysbus_mmio_map(busdev, 1, 0x1400080c);
 289     mmio_ide_init_drives(dev, dinfo, NULL);
 290
 291     /* onboard flash memory */
 292     dinfo = drive_get(IF_PFLASH, 0, 0);
 293     pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE,
 294                           dinfo ? blk_bs(blk_by_legacy_dinfo(dinfo)) : NULL,
 295                           (16 * 1024), FLASH_SIZE >> 16,
 296                           1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
 297                           0x555, 0x2aa, 0);
 298
 299     /* NIC: rtl8139 on-board, and 2 slots. */
 300     for (i = 0; i < nb_nics; i++)
 301         pci_nic_init_nofail(&nd_table[i], pci_bus,
 302                             "rtl8139", i==0 ? "2" : NULL);
 303
 304     /* USB keyboard */
 305     usbdevice_create("keyboard");
 306
 307     /* Todo: register on board registers */
 308     memset(&boot_params, 0, sizeof(boot_params));
 309
 310     if (kernel_filename) {
 311         int kernel_size;
 312
 313         kernel_size = load_image_targphys(kernel_filename,
 314                                           SDRAM_BASE + LINUX_LOAD_OFFSET,
 315                                           INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
 316         if (kernel_size < 0) {
 317           fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
 318           exit(1);
 319         }
 320
 321         /* initialization which should be done by firmware */
 322         stl_phys(&address_space_memory, SH7750_BCR1, 1<<3); /* cs3 SDRAM */
 323         stw_phys(&address_space_memory, SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
 324         reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
 325     }
 326
 327     if (initrd_filename) {
 328         int initrd_size;
 329
 330         initrd_size = load_image_targphys(initrd_filename,
 331                                           SDRAM_BASE + INITRD_LOAD_OFFSET,
 332                                           SDRAM_SIZE - INITRD_LOAD_OFFSET);
 333
 334         if (initrd_size < 0) {
 335           fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
 336           exit(1);
 337         }
 338
 339         /* initialization which should be done by firmware */
 340         boot_params.loader_type = 1;
 341         boot_params.initrd_start = INITRD_LOAD_OFFSET;
 342         boot_params.initrd_size = initrd_size;
 343     }
 344
 345     if (kernel_cmdline) {
 346         /* I see no evidence that this .kernel_cmdline buffer requires
 347            NUL-termination, so using strncpy should be ok. */
 348         strncpy(boot_params.kernel_cmdline, kernel_cmdline,
 349                 sizeof(boot_params.kernel_cmdline));
 350     }
 351
 352     rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
 353                        SDRAM_BASE + BOOT_PARAMS_OFFSET);
 354 }
 355
 356 static QEMUMachine r2d_machine = {
 357     .name = "r2d",
 358     .desc = "r2d-plus board",
 359     .init = r2d_init,
 360 };
 361
 362 static void r2d_machine_init(void)
 363 {
 364     qemu_register_machine(&r2d_machine);
 365 }
 366
 367 machine_init(r2d_machine_init);