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git.proxmox.com Git - mirror_qemu.git/blob - hw/sh_serial.c
2 * QEMU SCI/SCIF serial port emulation
4 * Copyright (c) 2007 Magnus Damm
6 * Based on serial.c - QEMU 16450 UART emulation
7 * Copyright (c) 2003-2004 Fabrice Bellard
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "qemu-char.h"
32 //#define DEBUG_SERIAL
34 #define SH_SERIAL_FLAG_TEND (1 << 0)
35 #define SH_SERIAL_FLAG_TDE (1 << 1)
36 #define SH_SERIAL_FLAG_RDF (1 << 2)
37 #define SH_SERIAL_FLAG_BRK (1 << 3)
38 #define SH_SERIAL_FLAG_DR (1 << 4)
44 uint8_t dr
; /* ftdr / tdr */
45 uint8_t sr
; /* fsr / ssr */
49 uint8_t rx_fifo
[16]; /* frdr / rdr */
52 target_phys_addr_t base
;
60 static void sh_serial_ioport_write(void *opaque
, uint32_t offs
, uint32_t val
)
62 sh_serial_state
*s
= opaque
;
66 printf("sh_serial: write base=0x%08lx offs=0x%02x val=0x%02x\n",
67 (unsigned long) s
->base
, offs
, val
);
71 s
->smr
= val
& ((s
->feat
& SH_SERIAL_FEAT_SCIF
) ? 0x7b : 0xff);
77 s
->scr
= val
& ((s
->feat
& SH_SERIAL_FEAT_SCIF
) ? 0xfb : 0xff);
78 if (!(val
& (1 << 5)))
79 s
->flags
|= SH_SERIAL_FLAG_TEND
;
81 case 0x0c: /* FTDR / TDR */
84 qemu_chr_write(s
->chr
, &ch
, 1);
87 s
->flags
&= ~SH_SERIAL_FLAG_TDE
;
90 case 0x14: /* FRDR / RDR */
95 if (s
->feat
& SH_SERIAL_FEAT_SCIF
) {
98 if (!(val
& (1 << 6)))
99 s
->flags
&= ~SH_SERIAL_FLAG_TEND
;
100 if (!(val
& (1 << 5)))
101 s
->flags
&= ~SH_SERIAL_FLAG_TDE
;
102 if (!(val
& (1 << 4)))
103 s
->flags
&= ~SH_SERIAL_FLAG_BRK
;
104 if (!(val
& (1 << 1)))
105 s
->flags
&= ~SH_SERIAL_FLAG_RDF
;
106 if (!(val
& (1 << 0)))
107 s
->flags
&= ~SH_SERIAL_FLAG_DR
;
112 case 0x20: /* SPTR */
135 fprintf(stderr
, "sh_serial: unsupported write to 0x%02x\n", offs
);
139 static uint32_t sh_serial_ioport_read(void *opaque
, uint32_t offs
)
141 sh_serial_state
*s
= opaque
;
160 if (s
->feat
& SH_SERIAL_FEAT_SCIF
) {
164 if (s
->flags
& SH_SERIAL_FLAG_TEND
)
166 if (s
->flags
& SH_SERIAL_FLAG_TDE
)
168 if (s
->flags
& SH_SERIAL_FLAG_BRK
)
170 if (s
->flags
& SH_SERIAL_FLAG_RDF
)
172 if (s
->flags
& SH_SERIAL_FLAG_DR
)
175 if (s
->scr
& (1 << 5))
176 s
->flags
|= SH_SERIAL_FLAG_TDE
| SH_SERIAL_FLAG_TEND
;
211 printf("sh_serial: read base=0x%08lx offs=0x%02x val=0x%x\n",
212 (unsigned long) s
->base
, offs
, ret
);
215 if (ret
& ~((1 << 16) - 1)) {
216 fprintf(stderr
, "sh_serial: unsupported read from 0x%02x\n", offs
);
223 static int sh_serial_can_receive(sh_serial_state
*s
)
228 static void sh_serial_receive_byte(sh_serial_state
*s
, int ch
)
232 static void sh_serial_receive_break(sh_serial_state
*s
)
236 static int sh_serial_can_receive1(void *opaque
)
238 sh_serial_state
*s
= opaque
;
239 return sh_serial_can_receive(s
);
242 static void sh_serial_receive1(void *opaque
, const uint8_t *buf
, int size
)
244 sh_serial_state
*s
= opaque
;
245 sh_serial_receive_byte(s
, buf
[0]);
248 static void sh_serial_event(void *opaque
, int event
)
250 sh_serial_state
*s
= opaque
;
251 if (event
== CHR_EVENT_BREAK
)
252 sh_serial_receive_break(s
);
255 static uint32_t sh_serial_read (void *opaque
, target_phys_addr_t addr
)
257 sh_serial_state
*s
= opaque
;
258 return sh_serial_ioport_read(s
, addr
- s
->base
);
261 static void sh_serial_write (void *opaque
,
262 target_phys_addr_t addr
, uint32_t value
)
264 sh_serial_state
*s
= opaque
;
265 sh_serial_ioport_write(s
, addr
- s
->base
, value
);
268 static CPUReadMemoryFunc
*sh_serial_readfn
[] = {
274 static CPUWriteMemoryFunc
*sh_serial_writefn
[] = {
280 void sh_serial_init (target_phys_addr_t base
, int feat
,
281 uint32_t freq
, CharDriverState
*chr
)
286 s
= qemu_mallocz(sizeof(sh_serial_state
));
292 s
->flags
= SH_SERIAL_FLAG_TEND
| SH_SERIAL_FLAG_TDE
;
296 s
->scr
= 1 << 5; /* pretend that TX is enabled so early printk works */
299 if (feat
& SH_SERIAL_FEAT_SCIF
) {
308 s_io_memory
= cpu_register_io_memory(0, sh_serial_readfn
,
309 sh_serial_writefn
, s
);
310 cpu_register_physical_memory(base
, 0x28, s_io_memory
);
315 qemu_chr_add_handlers(chr
, sh_serial_can_receive1
, sh_serial_receive1
,