2 * QEMU Sparc SLAVIO interrupt controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 //#define DEBUG_IRQ_COUNT
29 #define DPRINTF(fmt, args...) \
30 do { printf("IRQ: " fmt , ##args); } while (0)
32 #define DPRINTF(fmt, args...)
36 * Registers of interrupt controller in sun4m.
38 * This is the interrupt controller part of chip STP2001 (Slave I/O), also
39 * produced as NCR89C105. See
40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
42 * There is a system master controller and one for each cpu.
49 typedef struct SLAVIO_INTCTLState
{
50 uint32_t intreg_pending
[MAX_CPUS
];
51 uint32_t intregm_pending
;
52 uint32_t intregm_disabled
;
54 #ifdef DEBUG_IRQ_COUNT
55 uint64_t irq_count
[32];
57 qemu_irq
*cpu_irqs
[MAX_CPUS
];
58 const uint32_t *intbit_to_level
;
59 uint32_t cputimer_bit
;
60 uint32_t pil_out
[MAX_CPUS
];
63 #define INTCTL_MAXADDR 0xf
64 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
65 #define INTCTLM_MAXADDR 0x13
66 #define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
67 #define INTCTLM_MASK 0x1f
68 static void slavio_check_interrupts(void *opaque
);
70 // per-cpu interrupt controller
71 static uint32_t slavio_intctl_mem_readl(void *opaque
, target_phys_addr_t addr
)
73 SLAVIO_INTCTLState
*s
= opaque
;
77 cpu
= (addr
& (MAX_CPUS
- 1) * TARGET_PAGE_SIZE
) >> 12;
78 saddr
= (addr
& INTCTL_MAXADDR
) >> 2;
81 ret
= s
->intreg_pending
[cpu
];
87 DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx
" = %x\n", cpu
, addr
, ret
);
92 static void slavio_intctl_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
94 SLAVIO_INTCTLState
*s
= opaque
;
98 cpu
= (addr
& (MAX_CPUS
- 1) * TARGET_PAGE_SIZE
) >> 12;
99 saddr
= (addr
& INTCTL_MAXADDR
) >> 2;
100 DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx
" = %x\n", cpu
, addr
, val
);
102 case 1: // clear pending softints
106 s
->intreg_pending
[cpu
] &= ~val
;
107 slavio_check_interrupts(s
);
108 DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu
, val
, s
->intreg_pending
[cpu
]);
110 case 2: // set softint
112 s
->intreg_pending
[cpu
] |= val
;
113 slavio_check_interrupts(s
);
114 DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu
, val
, s
->intreg_pending
[cpu
]);
121 static CPUReadMemoryFunc
*slavio_intctl_mem_read
[3] = {
122 slavio_intctl_mem_readl
,
123 slavio_intctl_mem_readl
,
124 slavio_intctl_mem_readl
,
127 static CPUWriteMemoryFunc
*slavio_intctl_mem_write
[3] = {
128 slavio_intctl_mem_writel
,
129 slavio_intctl_mem_writel
,
130 slavio_intctl_mem_writel
,
133 // master system interrupt controller
134 static uint32_t slavio_intctlm_mem_readl(void *opaque
, target_phys_addr_t addr
)
136 SLAVIO_INTCTLState
*s
= opaque
;
139 saddr
= (addr
& INTCTLM_MAXADDR
) >> 2;
142 ret
= s
->intregm_pending
& 0x7fffffff;
145 ret
= s
->intregm_disabled
;
154 DPRINTF("read system reg 0x" TARGET_FMT_plx
" = %x\n", addr
, ret
);
159 static void slavio_intctlm_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
161 SLAVIO_INTCTLState
*s
= opaque
;
164 saddr
= (addr
& INTCTLM_MASK
) >> 2;
165 DPRINTF("write system reg 0x" TARGET_FMT_plx
" = %x\n", addr
, val
);
167 case 2: // clear (enable)
168 // Force clear unused bits
170 s
->intregm_disabled
&= ~val
;
171 DPRINTF("Enabled master irq mask %x, curmask %x\n", val
, s
->intregm_disabled
);
172 slavio_check_interrupts(s
);
174 case 3: // set (disable, clear pending)
175 // Force clear unused bits
177 s
->intregm_disabled
|= val
;
178 s
->intregm_pending
&= ~val
;
179 slavio_check_interrupts(s
);
180 DPRINTF("Disabled master irq mask %x, curmask %x\n", val
, s
->intregm_disabled
);
183 s
->target_cpu
= val
& (MAX_CPUS
- 1);
184 slavio_check_interrupts(s
);
185 DPRINTF("Set master irq cpu %d\n", s
->target_cpu
);
192 static CPUReadMemoryFunc
*slavio_intctlm_mem_read
[3] = {
193 slavio_intctlm_mem_readl
,
194 slavio_intctlm_mem_readl
,
195 slavio_intctlm_mem_readl
,
198 static CPUWriteMemoryFunc
*slavio_intctlm_mem_write
[3] = {
199 slavio_intctlm_mem_writel
,
200 slavio_intctlm_mem_writel
,
201 slavio_intctlm_mem_writel
,
204 void slavio_pic_info(void *opaque
)
206 SLAVIO_INTCTLState
*s
= opaque
;
209 for (i
= 0; i
< MAX_CPUS
; i
++) {
210 term_printf("per-cpu %d: pending 0x%08x\n", i
, s
->intreg_pending
[i
]);
212 term_printf("master: pending 0x%08x, disabled 0x%08x\n", s
->intregm_pending
, s
->intregm_disabled
);
215 void slavio_irq_info(void *opaque
)
217 #ifndef DEBUG_IRQ_COUNT
218 term_printf("irq statistic code not compiled.\n");
220 SLAVIO_INTCTLState
*s
= opaque
;
224 term_printf("IRQ statistics:\n");
225 for (i
= 0; i
< 32; i
++) {
226 count
= s
->irq_count
[i
];
228 term_printf("%2d: %" PRId64
"\n", i
, count
);
233 static void slavio_check_interrupts(void *opaque
)
235 SLAVIO_INTCTLState
*s
= opaque
;
236 uint32_t pending
= s
->intregm_pending
, pil_pending
;
239 pending
&= ~s
->intregm_disabled
;
241 DPRINTF("pending %x disabled %x\n", pending
, s
->intregm_disabled
);
242 for (i
= 0; i
< MAX_CPUS
; i
++) {
244 if (pending
&& !(s
->intregm_disabled
& 0x80000000) &&
245 (i
== s
->target_cpu
)) {
246 for (j
= 0; j
< 32; j
++) {
247 if (pending
& (1 << j
))
248 pil_pending
|= 1 << s
->intbit_to_level
[j
];
251 pil_pending
|= (s
->intreg_pending
[i
] >> 16) & 0xfffe;
253 for (j
= 0; j
< MAX_PILS
; j
++) {
254 if (pil_pending
& (1 << j
)) {
255 if (!(s
->pil_out
[i
] & (1 << j
)))
256 qemu_irq_raise(s
->cpu_irqs
[i
][j
]);
258 if (s
->pil_out
[i
] & (1 << j
))
259 qemu_irq_lower(s
->cpu_irqs
[i
][j
]);
262 s
->pil_out
[i
] = pil_pending
;
267 * "irq" here is the bit number in the system interrupt register to
268 * separate serial and keyboard interrupts sharing a level.
270 static void slavio_set_irq(void *opaque
, int irq
, int level
)
272 SLAVIO_INTCTLState
*s
= opaque
;
273 uint32_t mask
= 1 << irq
;
274 uint32_t pil
= s
->intbit_to_level
[irq
];
276 DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s
->target_cpu
, irq
, pil
,
280 #ifdef DEBUG_IRQ_COUNT
283 s
->intregm_pending
|= mask
;
284 s
->intreg_pending
[s
->target_cpu
] |= 1 << pil
;
286 s
->intregm_pending
&= ~mask
;
287 s
->intreg_pending
[s
->target_cpu
] &= ~(1 << pil
);
289 slavio_check_interrupts(s
);
293 static void slavio_set_timer_irq_cpu(void *opaque
, int cpu
, int level
)
295 SLAVIO_INTCTLState
*s
= opaque
;
297 DPRINTF("Set cpu %d local timer level %d\n", cpu
, level
);
300 s
->intreg_pending
[cpu
] |= s
->cputimer_bit
;
302 s
->intreg_pending
[cpu
] &= ~s
->cputimer_bit
;
304 slavio_check_interrupts(s
);
307 static void slavio_intctl_save(QEMUFile
*f
, void *opaque
)
309 SLAVIO_INTCTLState
*s
= opaque
;
312 for (i
= 0; i
< MAX_CPUS
; i
++) {
313 qemu_put_be32s(f
, &s
->intreg_pending
[i
]);
315 qemu_put_be32s(f
, &s
->intregm_pending
);
316 qemu_put_be32s(f
, &s
->intregm_disabled
);
317 qemu_put_be32s(f
, &s
->target_cpu
);
320 static int slavio_intctl_load(QEMUFile
*f
, void *opaque
, int version_id
)
322 SLAVIO_INTCTLState
*s
= opaque
;
328 for (i
= 0; i
< MAX_CPUS
; i
++) {
329 qemu_get_be32s(f
, &s
->intreg_pending
[i
]);
331 qemu_get_be32s(f
, &s
->intregm_pending
);
332 qemu_get_be32s(f
, &s
->intregm_disabled
);
333 qemu_get_be32s(f
, &s
->target_cpu
);
334 slavio_check_interrupts(s
);
338 static void slavio_intctl_reset(void *opaque
)
340 SLAVIO_INTCTLState
*s
= opaque
;
343 for (i
= 0; i
< MAX_CPUS
; i
++) {
344 s
->intreg_pending
[i
] = 0;
346 s
->intregm_disabled
= ~0xffb2007f;
347 s
->intregm_pending
= 0;
349 slavio_check_interrupts(s
);
352 void *slavio_intctl_init(target_phys_addr_t addr
, target_phys_addr_t addrg
,
353 const uint32_t *intbit_to_level
,
354 qemu_irq
**irq
, qemu_irq
**cpu_irq
,
355 qemu_irq
**parent_irq
, unsigned int cputimer
)
357 int slavio_intctl_io_memory
, slavio_intctlm_io_memory
, i
;
358 SLAVIO_INTCTLState
*s
;
360 s
= qemu_mallocz(sizeof(SLAVIO_INTCTLState
));
364 s
->intbit_to_level
= intbit_to_level
;
365 for (i
= 0; i
< MAX_CPUS
; i
++) {
366 slavio_intctl_io_memory
= cpu_register_io_memory(0, slavio_intctl_mem_read
, slavio_intctl_mem_write
, s
);
367 cpu_register_physical_memory(addr
+ i
* TARGET_PAGE_SIZE
, INTCTL_SIZE
,
368 slavio_intctl_io_memory
);
369 s
->cpu_irqs
[i
] = parent_irq
[i
];
372 slavio_intctlm_io_memory
= cpu_register_io_memory(0, slavio_intctlm_mem_read
, slavio_intctlm_mem_write
, s
);
373 cpu_register_physical_memory(addrg
, INTCTLM_SIZE
, slavio_intctlm_io_memory
);
375 register_savevm("slavio_intctl", addr
, 1, slavio_intctl_save
, slavio_intctl_load
, s
);
376 qemu_register_reset(slavio_intctl_reset
, s
);
377 *irq
= qemu_allocate_irqs(slavio_set_irq
, s
, 32);
379 *cpu_irq
= qemu_allocate_irqs(slavio_set_timer_irq_cpu
, s
, MAX_CPUS
);
380 s
->cputimer_bit
= 1 << s
->intbit_to_level
[cputimer
];
381 slavio_intctl_reset(s
);