hw/slavio_intctl.c

   1 /*
   2  * QEMU Sparc SLAVIO interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "console.h"
  27
  28 //#define DEBUG_IRQ_COUNT
  29 //#define DEBUG_IRQ
  30
  31 #ifdef DEBUG_IRQ
  32 #define DPRINTF(fmt, args...) \
  33 do { printf("IRQ: " fmt , ##args); } while (0)
  34 #else
  35 #define DPRINTF(fmt, args...)
  36 #endif
  37
  38 /*
  39  * Registers of interrupt controller in sun4m.
  40  *
  41  * This is the interrupt controller part of chip STP2001 (Slave I/O), also
  42  * produced as NCR89C105. See
  43  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  44  *
  45  * There is a system master controller and one for each cpu.
  46  *
  47  */
  48
  49 #define MAX_CPUS 16
  50 #define MAX_PILS 16
  51
  52 typedef struct SLAVIO_INTCTLState {
  53     uint32_t intreg_pending[MAX_CPUS];
  54     uint32_t intregm_pending;
  55     uint32_t intregm_disabled;
  56     uint32_t target_cpu;
  57 #ifdef DEBUG_IRQ_COUNT
  58     uint64_t irq_count[32];
  59 #endif
  60     qemu_irq *cpu_irqs[MAX_CPUS];
  61     const uint32_t *intbit_to_level;
  62     uint32_t cputimer_bit;
  63     uint32_t pil_out[MAX_CPUS];
  64 } SLAVIO_INTCTLState;
  65
  66 #define INTCTL_MAXADDR 0xf
  67 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  68 #define INTCTLM_MAXADDR 0x13
  69 #define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
  70 #define INTCTLM_MASK 0x1f
  71 #define MASTER_IRQ_MASK ~0x0fa2007f
  72 #define MASTER_DISABLE 0x80000000
  73 #define CPU_SOFTIRQ_MASK 0xfffe0000
  74 #define CPU_HARDIRQ_MASK 0x0000fffe
  75 #define CPU_IRQ_INT15_IN 0x0004000
  76 #define CPU_IRQ_INT15_MASK 0x80000000
  77
  78 static void slavio_check_interrupts(void *opaque);
  79
  80 // per-cpu interrupt controller
  81 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
  82 {
  83     SLAVIO_INTCTLState *s = opaque;
  84     uint32_t saddr, ret;
  85     int cpu;
  86
  87     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
  88     saddr = (addr & INTCTL_MAXADDR) >> 2;
  89     switch (saddr) {
  90     case 0:
  91         ret = s->intreg_pending[cpu];
  92         break;
  93     default:
  94         ret = 0;
  95         break;
  96     }
  97     DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, ret);
  98
  99     return ret;
 100 }
 101
 102 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 103 {
 104     SLAVIO_INTCTLState *s = opaque;
 105     uint32_t saddr;
 106     int cpu;
 107
 108     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
 109     saddr = (addr & INTCTL_MAXADDR) >> 2;
 110     DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
 111     switch (saddr) {
 112     case 1: // clear pending softints
 113         if (val & CPU_IRQ_INT15_IN)
 114             val |= CPU_IRQ_INT15_MASK;
 115         val &= CPU_SOFTIRQ_MASK;
 116         s->intreg_pending[cpu] &= ~val;
 117         slavio_check_interrupts(s);
 118         DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
 119         break;
 120     case 2: // set softint
 121         val &= CPU_SOFTIRQ_MASK;
 122         s->intreg_pending[cpu] |= val;
 123         slavio_check_interrupts(s);
 124         DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
 125         break;
 126     default:
 127         break;
 128     }
 129 }
 130
 131 static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
 132     NULL,
 133     NULL,
 134     slavio_intctl_mem_readl,
 135 };
 136
 137 static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
 138     NULL,
 139     NULL,
 140     slavio_intctl_mem_writel,
 141 };
 142
 143 // master system interrupt controller
 144 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
 145 {
 146     SLAVIO_INTCTLState *s = opaque;
 147     uint32_t saddr, ret;
 148
 149     saddr = (addr & INTCTLM_MASK) >> 2;
 150     switch (saddr) {
 151     case 0:
 152         ret = s->intregm_pending & ~MASTER_DISABLE;
 153         break;
 154     case 1:
 155         ret = s->intregm_disabled & MASTER_IRQ_MASK;
 156         break;
 157     case 4:
 158         ret = s->target_cpu;
 159         break;
 160     default:
 161         ret = 0;
 162         break;
 163     }
 164     DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
 165
 166     return ret;
 167 }
 168
 169 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 170 {
 171     SLAVIO_INTCTLState *s = opaque;
 172     uint32_t saddr;
 173
 174     saddr = (addr & INTCTLM_MASK) >> 2;
 175     DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
 176     switch (saddr) {
 177     case 2: // clear (enable)
 178         // Force clear unused bits
 179         val &= MASTER_IRQ_MASK;
 180         s->intregm_disabled &= ~val;
 181         DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
 182         slavio_check_interrupts(s);
 183         break;
 184     case 3: // set (disable, clear pending)
 185         // Force clear unused bits
 186         val &= MASTER_IRQ_MASK;
 187         s->intregm_disabled |= val;
 188         s->intregm_pending &= ~val;
 189         slavio_check_interrupts(s);
 190         DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
 191         break;
 192     case 4:
 193         s->target_cpu = val & (MAX_CPUS - 1);
 194         slavio_check_interrupts(s);
 195         DPRINTF("Set master irq cpu %d\n", s->target_cpu);
 196         break;
 197     default:
 198         break;
 199     }
 200 }
 201
 202 static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
 203     NULL,
 204     NULL,
 205     slavio_intctlm_mem_readl,
 206 };
 207
 208 static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
 209     NULL,
 210     NULL,
 211     slavio_intctlm_mem_writel,
 212 };
 213
 214 void slavio_pic_info(void *opaque)
 215 {
 216     SLAVIO_INTCTLState *s = opaque;
 217     int i;
 218
 219     for (i = 0; i < MAX_CPUS; i++) {
 220         term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
 221     }
 222     term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
 223 }
 224
 225 void slavio_irq_info(void *opaque)
 226 {
 227 #ifndef DEBUG_IRQ_COUNT
 228     term_printf("irq statistic code not compiled.\n");
 229 #else
 230     SLAVIO_INTCTLState *s = opaque;
 231     int i;
 232     int64_t count;
 233
 234     term_printf("IRQ statistics:\n");
 235     for (i = 0; i < 32; i++) {
 236         count = s->irq_count[i];
 237         if (count > 0)
 238             term_printf("%2d: %" PRId64 "\n", i, count);
 239     }
 240 #endif
 241 }
 242
 243 static void slavio_check_interrupts(void *opaque)
 244 {
 245     SLAVIO_INTCTLState *s = opaque;
 246     uint32_t pending = s->intregm_pending, pil_pending;
 247     unsigned int i, j;
 248
 249     pending &= ~s->intregm_disabled;
 250
 251     DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
 252     for (i = 0; i < MAX_CPUS; i++) {
 253         pil_pending = 0;
 254         if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
 255             (i == s->target_cpu)) {
 256             for (j = 0; j < 32; j++) {
 257                 if (pending & (1 << j))
 258                     pil_pending |= 1 << s->intbit_to_level[j];
 259             }
 260             pil_pending |= s->intreg_pending[i] & CPU_HARDIRQ_MASK;
 261         }
 262         pil_pending |= (s->intreg_pending[i] & CPU_SOFTIRQ_MASK) >> 16;
 263
 264         for (j = 0; j < MAX_PILS; j++) {
 265             if (pil_pending & (1 << j)) {
 266                 if (!(s->pil_out[i] & (1 << j)))
 267                     qemu_irq_raise(s->cpu_irqs[i][j]);
 268             } else {
 269                 if (s->pil_out[i] & (1 << j))
 270                     qemu_irq_lower(s->cpu_irqs[i][j]);
 271             }
 272         }
 273         s->pil_out[i] = pil_pending;
 274     }
 275 }
 276
 277 /*
 278  * "irq" here is the bit number in the system interrupt register to
 279  * separate serial and keyboard interrupts sharing a level.
 280  */
 281 static void slavio_set_irq(void *opaque, int irq, int level)
 282 {
 283     SLAVIO_INTCTLState *s = opaque;
 284     uint32_t mask = 1 << irq;
 285     uint32_t pil = s->intbit_to_level[irq];
 286
 287     DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
 288             level);
 289     if (pil > 0) {
 290         if (level) {
 291 #ifdef DEBUG_IRQ_COUNT
 292             s->irq_count[pil]++;
 293 #endif
 294             s->intregm_pending |= mask;
 295             s->intreg_pending[s->target_cpu] |= 1 << pil;
 296         } else {
 297             s->intregm_pending &= ~mask;
 298             s->intreg_pending[s->target_cpu] &= ~(1 << pil);
 299         }
 300         slavio_check_interrupts(s);
 301     }
 302 }
 303
 304 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
 305 {
 306     SLAVIO_INTCTLState *s = opaque;
 307
 308     DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
 309
 310     if (level)
 311         s->intreg_pending[cpu] |= s->cputimer_bit;
 312     else
 313         s->intreg_pending[cpu] &= ~s->cputimer_bit;
 314
 315     slavio_check_interrupts(s);
 316 }
 317
 318 static void slavio_intctl_save(QEMUFile *f, void *opaque)
 319 {
 320     SLAVIO_INTCTLState *s = opaque;
 321     int i;
 322
 323     for (i = 0; i < MAX_CPUS; i++) {
 324         qemu_put_be32s(f, &s->intreg_pending[i]);
 325     }
 326     qemu_put_be32s(f, &s->intregm_pending);
 327     qemu_put_be32s(f, &s->intregm_disabled);
 328     qemu_put_be32s(f, &s->target_cpu);
 329 }
 330
 331 static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
 332 {
 333     SLAVIO_INTCTLState *s = opaque;
 334     int i;
 335
 336     if (version_id != 1)
 337         return -EINVAL;
 338
 339     for (i = 0; i < MAX_CPUS; i++) {
 340         qemu_get_be32s(f, &s->intreg_pending[i]);
 341     }
 342     qemu_get_be32s(f, &s->intregm_pending);
 343     qemu_get_be32s(f, &s->intregm_disabled);
 344     qemu_get_be32s(f, &s->target_cpu);
 345     slavio_check_interrupts(s);
 346     return 0;
 347 }
 348
 349 static void slavio_intctl_reset(void *opaque)
 350 {
 351     SLAVIO_INTCTLState *s = opaque;
 352     int i;
 353
 354     for (i = 0; i < MAX_CPUS; i++) {
 355         s->intreg_pending[i] = 0;
 356     }
 357     s->intregm_disabled = ~MASTER_IRQ_MASK;
 358     s->intregm_pending = 0;
 359     s->target_cpu = 0;
 360     slavio_check_interrupts(s);
 361 }
 362
 363 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
 364                          const uint32_t *intbit_to_level,
 365                          qemu_irq **irq, qemu_irq **cpu_irq,
 366                          qemu_irq **parent_irq, unsigned int cputimer)
 367 {
 368     int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
 369     SLAVIO_INTCTLState *s;
 370
 371     s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
 372     if (!s)
 373         return NULL;
 374
 375     s->intbit_to_level = intbit_to_level;
 376     for (i = 0; i < MAX_CPUS; i++) {
 377         slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
 378         cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
 379                                      slavio_intctl_io_memory);
 380         s->cpu_irqs[i] = parent_irq[i];
 381     }
 382
 383     slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
 384     cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
 385
 386     register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
 387     qemu_register_reset(slavio_intctl_reset, s);
 388     *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
 389
 390     *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
 391     s->cputimer_bit = 1 << cputimer;
 392     slavio_intctl_reset(s);
 393     return s;
 394 }
 395