hw/slavio_timer.c

   1 /*
   2  * QEMU Sparc SLAVIO timer controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "qemu-timer.h"
  27
  28 //#define DEBUG_TIMER
  29
  30 #ifdef DEBUG_TIMER
  31 #define DPRINTF(fmt, args...) \
  32 do { printf("TIMER: " fmt , ##args); } while (0)
  33 #else
  34 #define DPRINTF(fmt, args...)
  35 #endif
  36
  37 /*
  38  * Registers of hardware timer in sun4m.
  39  *
  40  * This is the timer/counter part of chip STP2001 (Slave I/O), also
  41  * produced as NCR89C105. See
  42  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  43  *
  44  * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
  45  * are zero. Bit 31 is 1 when count has been reached.
  46  *
  47  * Per-CPU timers interrupt local CPU, system timer uses normal
  48  * interrupt routing.
  49  *
  50  */
  51
  52 #define MAX_CPUS 16
  53
  54 typedef struct SLAVIO_TIMERState {
  55     qemu_irq irq;
  56     ptimer_state *timer;
  57     uint32_t count, counthigh, reached;
  58     uint64_t limit;
  59     // processor only
  60     int running;
  61     struct SLAVIO_TIMERState *master;
  62     int slave_index;
  63     // system only
  64     unsigned int num_slaves;
  65     struct SLAVIO_TIMERState *slave[MAX_CPUS];
  66     uint32_t slave_mode;
  67 } SLAVIO_TIMERState;
  68
  69 #define TIMER_MAXADDR 0x1f
  70 #define SYS_TIMER_SIZE 0x14
  71 #define CPU_TIMER_SIZE 0x10
  72
  73 #define SYS_TIMER_OFFSET      0x10000ULL
  74 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
  75
  76 #define TIMER_LIMIT         0
  77 #define TIMER_COUNTER       1
  78 #define TIMER_COUNTER_NORST 2
  79 #define TIMER_STATUS        3
  80 #define TIMER_MODE          4
  81
  82 #define TIMER_COUNT_MASK32 0xfffffe00
  83 #define TIMER_LIMIT_MASK32 0x7fffffff
  84 #define TIMER_MAX_COUNT64  0x7ffffffffffffe00ULL
  85 #define TIMER_MAX_COUNT32  0x7ffffe00ULL
  86 #define TIMER_REACHED      0x80000000
  87 #define TIMER_PERIOD       500ULL // 500ns
  88 #define LIMIT_TO_PERIODS(l) ((l) >> 9)
  89 #define PERIODS_TO_LIMIT(l) ((l) << 9)
  90
  91 static int slavio_timer_is_user(SLAVIO_TIMERState *s)
  92 {
  93     return s->master && (s->master->slave_mode & (1 << s->slave_index));
  94 }
  95
  96 // Update count, set irq, update expire_time
  97 // Convert from ptimer countdown units
  98 static void slavio_timer_get_out(SLAVIO_TIMERState *s)
  99 {
 100     uint64_t count, limit;
 101
 102     if (s->limit == 0) /* free-run processor or system counter */
 103         limit = TIMER_MAX_COUNT32;
 104     else
 105         limit = s->limit;
 106
 107     if (s->timer)
 108         count = limit - PERIODS_TO_LIMIT(ptimer_get_count(s->timer));
 109     else
 110         count = 0;
 111
 112     DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit,
 113             s->counthigh, s->count);
 114     s->count = count & TIMER_COUNT_MASK32;
 115     s->counthigh = count >> 32;
 116 }
 117
 118 // timer callback
 119 static void slavio_timer_irq(void *opaque)
 120 {
 121     SLAVIO_TIMERState *s = opaque;
 122
 123     slavio_timer_get_out(s);
 124     DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
 125     s->reached = TIMER_REACHED;
 126     if (!slavio_timer_is_user(s))
 127         qemu_irq_raise(s->irq);
 128 }
 129
 130 static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
 131 {
 132     SLAVIO_TIMERState *s = opaque;
 133     uint32_t saddr, ret;
 134
 135     saddr = (addr & TIMER_MAXADDR) >> 2;
 136     switch (saddr) {
 137     case TIMER_LIMIT:
 138         // read limit (system counter mode) or read most signifying
 139         // part of counter (user mode)
 140         if (slavio_timer_is_user(s)) {
 141             // read user timer MSW
 142             slavio_timer_get_out(s);
 143             ret = s->counthigh | s->reached;
 144         } else {
 145             // read limit
 146             // clear irq
 147             qemu_irq_lower(s->irq);
 148             s->reached = 0;
 149             ret = s->limit & TIMER_LIMIT_MASK32;
 150         }
 151         break;
 152     case TIMER_COUNTER:
 153         // read counter and reached bit (system mode) or read lsbits
 154         // of counter (user mode)
 155         slavio_timer_get_out(s);
 156         if (slavio_timer_is_user(s)) // read user timer LSW
 157             ret = s->count & TIMER_MAX_COUNT64;
 158         else // read limit
 159             ret = (s->count & TIMER_MAX_COUNT32) | s->reached;
 160         break;
 161     case TIMER_STATUS:
 162         // only available in processor counter/timer
 163         // read start/stop status
 164         ret = s->running;
 165         break;
 166     case TIMER_MODE:
 167         // only available in system counter
 168         // read user/system mode
 169         ret = s->slave_mode;
 170         break;
 171     default:
 172         DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
 173         ret = 0;
 174         break;
 175     }
 176     DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
 177
 178     return ret;
 179 }
 180
 181 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
 182                                     uint32_t val)
 183 {
 184     SLAVIO_TIMERState *s = opaque;
 185     uint32_t saddr;
 186
 187     DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
 188     saddr = (addr & TIMER_MAXADDR) >> 2;
 189     switch (saddr) {
 190     case TIMER_LIMIT:
 191         if (slavio_timer_is_user(s)) {
 192             uint64_t count;
 193
 194             // set user counter MSW, reset counter
 195             qemu_irq_lower(s->irq);
 196             s->limit = TIMER_MAX_COUNT64;
 197             s->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
 198             s->reached = 0;
 199             count = ((uint64_t)s->counthigh << 32) | s->count;
 200             DPRINTF("processor %d user timer set to %016llx\n", s->slave_index,
 201                     count);
 202             if (s->timer) {
 203                 ptimer_set_count(s->timer, LIMIT_TO_PERIODS(s->limit - count));
 204                 ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 0);
 205             }
 206         } else {
 207             // set limit, reset counter
 208             qemu_irq_lower(s->irq);
 209             s->limit = val & TIMER_MAX_COUNT32;
 210             if (s->timer) {
 211                 if (s->limit == 0) /* free-run */
 212                     ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
 213                 else
 214                     ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
 215             }
 216         }
 217         break;
 218     case TIMER_COUNTER:
 219         if (slavio_timer_is_user(s)) {
 220             uint64_t count;
 221
 222             // set user counter LSW, reset counter
 223             qemu_irq_lower(s->irq);
 224             s->limit = TIMER_MAX_COUNT64;
 225             s->count = val & TIMER_MAX_COUNT64;
 226             s->reached = 0;
 227             count = ((uint64_t)s->counthigh) << 32 | s->count;
 228             DPRINTF("processor %d user timer set to %016llx\n", s->slave_index,
 229                     count);
 230             if (s->timer) {
 231                 ptimer_set_count(s->timer, LIMIT_TO_PERIODS(s->limit - count));
 232                 ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 0);
 233             }
 234         } else
 235             DPRINTF("not user timer\n");
 236         break;
 237     case TIMER_COUNTER_NORST:
 238         // set limit without resetting counter
 239         s->limit = val & TIMER_MAX_COUNT32;
 240         if (s->timer) {
 241             if (s->limit == 0)  /* free-run */
 242                 ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
 243             else
 244                 ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 0);
 245         }
 246         break;
 247     case TIMER_STATUS:
 248         if (slavio_timer_is_user(s)) {
 249             // start/stop user counter
 250             if ((val & 1) && !s->running) {
 251                 DPRINTF("processor %d user timer started\n", s->slave_index);
 252                 if (s->timer)
 253                     ptimer_run(s->timer, 0);
 254                 s->running = 1;
 255             } else if (!(val & 1) && s->running) {
 256                 DPRINTF("processor %d user timer stopped\n", s->slave_index);
 257                 if (s->timer)
 258                     ptimer_stop(s->timer);
 259                 s->running = 0;
 260             }
 261         }
 262         break;
 263     case TIMER_MODE:
 264         if (s->master == NULL) {
 265             unsigned int i;
 266
 267             for (i = 0; i < s->num_slaves; i++) {
 268                 if (val & (1 << i)) {
 269                     qemu_irq_lower(s->slave[i]->irq);
 270                     s->slave[i]->limit = -1ULL;
 271                 } else {
 272                     ptimer_stop(s->slave[i]->timer);
 273                 }
 274                 if ((val & (1 << i)) != (s->slave_mode & (1 << i))) {
 275                     ptimer_stop(s->slave[i]->timer);
 276                     ptimer_set_limit(s->slave[i]->timer,
 277                                      LIMIT_TO_PERIODS(s->slave[i]->limit), 1);
 278                     DPRINTF("processor %d timer changed\n",
 279                             s->slave[i]->slave_index);
 280                     ptimer_run(s->slave[i]->timer, 0);
 281                 }
 282             }
 283             s->slave_mode = val & ((1 << s->num_slaves) - 1);
 284         } else
 285             DPRINTF("not system timer\n");
 286         break;
 287     default:
 288         DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
 289         break;
 290     }
 291 }
 292
 293 static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
 294     NULL,
 295     NULL,
 296     slavio_timer_mem_readl,
 297 };
 298
 299 static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
 300     NULL,
 301     NULL,
 302     slavio_timer_mem_writel,
 303 };
 304
 305 static void slavio_timer_save(QEMUFile *f, void *opaque)
 306 {
 307     SLAVIO_TIMERState *s = opaque;
 308
 309     qemu_put_be64s(f, &s->limit);
 310     qemu_put_be32s(f, &s->count);
 311     qemu_put_be32s(f, &s->counthigh);
 312     qemu_put_be32s(f, &s->reached);
 313     qemu_put_be32s(f, &s->running);
 314     if (s->timer)
 315         qemu_put_ptimer(f, s->timer);
 316 }
 317
 318 static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
 319 {
 320     SLAVIO_TIMERState *s = opaque;
 321
 322     if (version_id != 3)
 323         return -EINVAL;
 324
 325     qemu_get_be64s(f, &s->limit);
 326     qemu_get_be32s(f, &s->count);
 327     qemu_get_be32s(f, &s->counthigh);
 328     qemu_get_be32s(f, &s->reached);
 329     qemu_get_be32s(f, &s->running);
 330     if (s->timer)
 331         qemu_get_ptimer(f, s->timer);
 332
 333     return 0;
 334 }
 335
 336 static void slavio_timer_reset(void *opaque)
 337 {
 338     SLAVIO_TIMERState *s = opaque;
 339
 340     s->limit = 0;
 341     s->count = 0;
 342     s->reached = 0;
 343     s->slave_mode = 0;
 344     if (!s->master || s->slave_index < s->master->num_slaves) {
 345         ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
 346         ptimer_run(s->timer, 0);
 347     }
 348     s->running = 1;
 349     qemu_irq_lower(s->irq);
 350 }
 351
 352 static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
 353                                             qemu_irq irq,
 354                                             SLAVIO_TIMERState *master,
 355                                             int slave_index)
 356 {
 357     int slavio_timer_io_memory;
 358     SLAVIO_TIMERState *s;
 359     QEMUBH *bh;
 360
 361     s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
 362     if (!s)
 363         return s;
 364     s->irq = irq;
 365     s->master = master;
 366     s->slave_index = slave_index;
 367     if (!master || slave_index < master->num_slaves) {
 368         bh = qemu_bh_new(slavio_timer_irq, s);
 369         s->timer = ptimer_init(bh);
 370         ptimer_set_period(s->timer, TIMER_PERIOD);
 371     }
 372
 373     slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
 374                                                     slavio_timer_mem_write, s);
 375     if (master)
 376         cpu_register_physical_memory(addr, CPU_TIMER_SIZE,
 377                                      slavio_timer_io_memory);
 378     else
 379         cpu_register_physical_memory(addr, SYS_TIMER_SIZE,
 380                                      slavio_timer_io_memory);
 381     register_savevm("slavio_timer", addr, 3, slavio_timer_save,
 382                     slavio_timer_load, s);
 383     qemu_register_reset(slavio_timer_reset, s);
 384     slavio_timer_reset(s);
 385
 386     return s;
 387 }
 388
 389 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
 390                            qemu_irq *cpu_irqs, unsigned int num_cpus)
 391 {
 392     SLAVIO_TIMERState *master;
 393     unsigned int i;
 394
 395     master = slavio_timer_init(base + SYS_TIMER_OFFSET, master_irq, NULL, 0);
 396
 397     master->num_slaves = num_cpus;
 398
 399     for (i = 0; i < MAX_CPUS; i++) {
 400         master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
 401                                              CPU_TIMER_OFFSET(i),
 402                                              cpu_irqs[i], master, i);
 403     }
 404 }