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2 * QEMU Sparc SLAVIO timer controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu-timer.h"
31 #define DPRINTF(fmt, args...) \
32 do { printf("TIMER: " fmt , ##args); } while (0)
34 #define DPRINTF(fmt, args...)
38 * Registers of hardware timer in sun4m.
40 * This is the timer/counter part of chip STP2001 (Slave I/O), also
41 * produced as NCR89C105. See
42 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
44 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
45 * are zero. Bit 31 is 1 when count has been reached.
47 * Per-CPU timers interrupt local CPU, system timer uses normal
54 typedef struct SLAVIO_TIMERState
{
57 uint32_t count
, counthigh
, reached
;
61 struct SLAVIO_TIMERState
*master
;
64 unsigned int num_slaves
;
65 struct SLAVIO_TIMERState
*slave
[MAX_CPUS
];
69 #define TIMER_MAXADDR 0x1f
70 #define SYS_TIMER_SIZE 0x14
71 #define CPU_TIMER_SIZE 0x10
73 #define SYS_TIMER_OFFSET 0x10000ULL
74 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
77 #define TIMER_COUNTER 1
78 #define TIMER_COUNTER_NORST 2
79 #define TIMER_STATUS 3
82 #define TIMER_COUNT_MASK32 0xfffffe00
83 #define TIMER_LIMIT_MASK32 0x7fffffff
84 #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
85 #define TIMER_MAX_COUNT32 0x7ffffe00ULL
86 #define TIMER_REACHED 0x80000000
87 #define TIMER_PERIOD 500ULL // 500ns
88 #define LIMIT_TO_PERIODS(l) ((l) >> 9)
89 #define PERIODS_TO_LIMIT(l) ((l) << 9)
91 static int slavio_timer_is_user(SLAVIO_TIMERState
*s
)
93 return s
->master
&& (s
->master
->slave_mode
& (1 << s
->slave_index
));
96 // Update count, set irq, update expire_time
97 // Convert from ptimer countdown units
98 static void slavio_timer_get_out(SLAVIO_TIMERState
*s
)
100 uint64_t count
, limit
;
102 if (s
->limit
== 0) /* free-run processor or system counter */
103 limit
= TIMER_MAX_COUNT32
;
108 count
= limit
- PERIODS_TO_LIMIT(ptimer_get_count(s
->timer
));
112 DPRINTF("get_out: limit %" PRIx64
" count %x%08x\n", s
->limit
,
113 s
->counthigh
, s
->count
);
114 s
->count
= count
& TIMER_COUNT_MASK32
;
115 s
->counthigh
= count
>> 32;
119 static void slavio_timer_irq(void *opaque
)
121 SLAVIO_TIMERState
*s
= opaque
;
123 slavio_timer_get_out(s
);
124 DPRINTF("callback: count %x%08x\n", s
->counthigh
, s
->count
);
125 s
->reached
= TIMER_REACHED
;
126 if (!slavio_timer_is_user(s
))
127 qemu_irq_raise(s
->irq
);
130 static uint32_t slavio_timer_mem_readl(void *opaque
, target_phys_addr_t addr
)
132 SLAVIO_TIMERState
*s
= opaque
;
135 saddr
= (addr
& TIMER_MAXADDR
) >> 2;
138 // read limit (system counter mode) or read most signifying
139 // part of counter (user mode)
140 if (slavio_timer_is_user(s
)) {
141 // read user timer MSW
142 slavio_timer_get_out(s
);
143 ret
= s
->counthigh
| s
->reached
;
147 qemu_irq_lower(s
->irq
);
149 ret
= s
->limit
& TIMER_LIMIT_MASK32
;
153 // read counter and reached bit (system mode) or read lsbits
154 // of counter (user mode)
155 slavio_timer_get_out(s
);
156 if (slavio_timer_is_user(s
)) // read user timer LSW
157 ret
= s
->count
& TIMER_MAX_COUNT64
;
159 ret
= (s
->count
& TIMER_MAX_COUNT32
) | s
->reached
;
162 // only available in processor counter/timer
163 // read start/stop status
167 // only available in system counter
168 // read user/system mode
172 DPRINTF("invalid read address " TARGET_FMT_plx
"\n", addr
);
176 DPRINTF("read " TARGET_FMT_plx
" = %08x\n", addr
, ret
);
181 static void slavio_timer_mem_writel(void *opaque
, target_phys_addr_t addr
,
184 SLAVIO_TIMERState
*s
= opaque
;
187 DPRINTF("write " TARGET_FMT_plx
" %08x\n", addr
, val
);
188 saddr
= (addr
& TIMER_MAXADDR
) >> 2;
191 if (slavio_timer_is_user(s
)) {
194 // set user counter MSW, reset counter
195 s
->limit
= TIMER_MAX_COUNT64
;
196 s
->counthigh
= val
& (TIMER_MAX_COUNT64
>> 32);
198 count
= ((uint64_t)s
->counthigh
<< 32) | s
->count
;
199 DPRINTF("processor %d user timer set to %016llx\n", s
->slave_index
,
202 ptimer_set_count(s
->timer
, LIMIT_TO_PERIODS(s
->limit
- count
));
204 // set limit, reset counter
205 qemu_irq_lower(s
->irq
);
206 s
->limit
= val
& TIMER_MAX_COUNT32
;
208 if (s
->limit
== 0) /* free-run */
209 ptimer_set_limit(s
->timer
, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32
), 1);
211 ptimer_set_limit(s
->timer
, LIMIT_TO_PERIODS(s
->limit
), 1);
216 if (slavio_timer_is_user(s
)) {
219 // set user counter LSW, reset counter
220 s
->limit
= TIMER_MAX_COUNT64
;
221 s
->count
= val
& TIMER_MAX_COUNT64
;
223 count
= ((uint64_t)s
->counthigh
) << 32 | s
->count
;
224 DPRINTF("processor %d user timer set to %016llx\n", s
->slave_index
,
227 ptimer_set_count(s
->timer
, LIMIT_TO_PERIODS(s
->limit
- count
));
229 DPRINTF("not user timer\n");
231 case TIMER_COUNTER_NORST
:
232 // set limit without resetting counter
233 s
->limit
= val
& TIMER_MAX_COUNT32
;
235 if (s
->limit
== 0) /* free-run */
236 ptimer_set_limit(s
->timer
, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32
), 0);
238 ptimer_set_limit(s
->timer
, LIMIT_TO_PERIODS(s
->limit
), 0);
242 if (slavio_timer_is_user(s
)) {
243 // start/stop user counter
244 if ((val
& 1) && !s
->running
) {
245 DPRINTF("processor %d user timer started\n", s
->slave_index
);
247 ptimer_run(s
->timer
, 0);
249 } else if (!(val
& 1) && s
->running
) {
250 DPRINTF("processor %d user timer stopped\n", s
->slave_index
);
252 ptimer_stop(s
->timer
);
258 if (s
->master
== NULL
) {
261 for (i
= 0; i
< s
->num_slaves
; i
++) {
262 unsigned int processor
= 1 << i
;
264 // check for a change in timer mode for this processor
265 if ((val
& processor
) != (s
->slave_mode
& processor
)) {
266 if (val
& processor
) { // counter -> user timer
267 qemu_irq_lower(s
->slave
[i
]->irq
);
268 // counters are always running
269 ptimer_stop(s
->slave
[i
]->timer
);
270 s
->slave
[i
]->running
= 0;
271 // user timer limit is always the same
272 s
->slave
[i
]->limit
= TIMER_MAX_COUNT64
;
273 ptimer_set_limit(s
->slave
[i
]->timer
,
274 LIMIT_TO_PERIODS(s
->slave
[i
]->limit
), 1);
275 // set this processors user timer bit in config
277 s
->slave_mode
|= processor
;
278 DPRINTF("processor %d changed from counter to user "
279 "timer\n", s
->slave
[i
]->slave_index
);
280 } else { // user timer -> counter
281 // stop the user timer if it is running
282 if (s
->slave
[i
]->running
)
283 ptimer_stop(s
->slave
[i
]->timer
);
285 ptimer_run(s
->slave
[i
]->timer
, 0);
286 s
->slave
[i
]->running
= 1;
287 // clear this processors user timer bit in config
289 s
->slave_mode
&= ~processor
;
290 DPRINTF("processor %d changed from user timer to "
291 "counter\n", s
->slave
[i
]->slave_index
);
296 DPRINTF("not system timer\n");
299 DPRINTF("invalid write address " TARGET_FMT_plx
"\n", addr
);
304 static CPUReadMemoryFunc
*slavio_timer_mem_read
[3] = {
307 slavio_timer_mem_readl
,
310 static CPUWriteMemoryFunc
*slavio_timer_mem_write
[3] = {
313 slavio_timer_mem_writel
,
316 static void slavio_timer_save(QEMUFile
*f
, void *opaque
)
318 SLAVIO_TIMERState
*s
= opaque
;
320 qemu_put_be64s(f
, &s
->limit
);
321 qemu_put_be32s(f
, &s
->count
);
322 qemu_put_be32s(f
, &s
->counthigh
);
323 qemu_put_be32s(f
, &s
->reached
);
324 qemu_put_be32s(f
, &s
->running
);
326 qemu_put_ptimer(f
, s
->timer
);
329 static int slavio_timer_load(QEMUFile
*f
, void *opaque
, int version_id
)
331 SLAVIO_TIMERState
*s
= opaque
;
336 qemu_get_be64s(f
, &s
->limit
);
337 qemu_get_be32s(f
, &s
->count
);
338 qemu_get_be32s(f
, &s
->counthigh
);
339 qemu_get_be32s(f
, &s
->reached
);
340 qemu_get_be32s(f
, &s
->running
);
342 qemu_get_ptimer(f
, s
->timer
);
347 static void slavio_timer_reset(void *opaque
)
349 SLAVIO_TIMERState
*s
= opaque
;
355 if (!s
->master
|| s
->slave_index
< s
->master
->num_slaves
) {
356 ptimer_set_limit(s
->timer
, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32
), 1);
357 ptimer_run(s
->timer
, 0);
360 qemu_irq_lower(s
->irq
);
363 static SLAVIO_TIMERState
*slavio_timer_init(target_phys_addr_t addr
,
365 SLAVIO_TIMERState
*master
,
368 int slavio_timer_io_memory
;
369 SLAVIO_TIMERState
*s
;
372 s
= qemu_mallocz(sizeof(SLAVIO_TIMERState
));
377 s
->slave_index
= slave_index
;
378 if (!master
|| slave_index
< master
->num_slaves
) {
379 bh
= qemu_bh_new(slavio_timer_irq
, s
);
380 s
->timer
= ptimer_init(bh
);
381 ptimer_set_period(s
->timer
, TIMER_PERIOD
);
384 slavio_timer_io_memory
= cpu_register_io_memory(0, slavio_timer_mem_read
,
385 slavio_timer_mem_write
, s
);
387 cpu_register_physical_memory(addr
, CPU_TIMER_SIZE
,
388 slavio_timer_io_memory
);
390 cpu_register_physical_memory(addr
, SYS_TIMER_SIZE
,
391 slavio_timer_io_memory
);
392 register_savevm("slavio_timer", addr
, 3, slavio_timer_save
,
393 slavio_timer_load
, s
);
394 qemu_register_reset(slavio_timer_reset
, s
);
395 slavio_timer_reset(s
);
400 void slavio_timer_init_all(target_phys_addr_t base
, qemu_irq master_irq
,
401 qemu_irq
*cpu_irqs
, unsigned int num_cpus
)
403 SLAVIO_TIMERState
*master
;
406 master
= slavio_timer_init(base
+ SYS_TIMER_OFFSET
, master_irq
, NULL
, 0);
408 master
->num_slaves
= num_cpus
;
410 for (i
= 0; i
< MAX_CPUS
; i
++) {
411 master
->slave
[i
] = slavio_timer_init(base
+ (target_phys_addr_t
)
413 cpu_irqs
[i
], master
, i
);