hw/smc91c111.c

   1 /*
   2  * SMSC 91C111 Ethernet interface emulation
   3  *
   4  * Copyright (c) 2005 CodeSourcery, LLC.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL
   8  */
   9
  10 #include "sysbus.h"
  11 #include "net.h"
  12 #include "devices.h"
  13 /* For crc32 */
  14 #include <zlib.h>
  15
  16 /* Number of 2k memory pages available.  */
  17 #define NUM_PACKETS 4
  18
  19 typedef struct {
  20     SysBusDevice busdev;
  21     NICState *nic;
  22     NICConf conf;
  23     uint16_t tcr;
  24     uint16_t rcr;
  25     uint16_t cr;
  26     uint16_t ctr;
  27     uint16_t gpr;
  28     uint16_t ptr;
  29     uint16_t ercv;
  30     qemu_irq irq;
  31     int bank;
  32     int packet_num;
  33     int tx_alloc;
  34     /* Bitmask of allocated packets.  */
  35     int allocated;
  36     int tx_fifo_len;
  37     int tx_fifo[NUM_PACKETS];
  38     int rx_fifo_len;
  39     int rx_fifo[NUM_PACKETS];
  40     int tx_fifo_done_len;
  41     int tx_fifo_done[NUM_PACKETS];
  42     /* Packet buffer memory.  */
  43     uint8_t data[NUM_PACKETS][2048];
  44     uint8_t int_level;
  45     uint8_t int_mask;
  46     int mmio_index;
  47 } smc91c111_state;
  48
  49 #define RCR_SOFT_RST  0x8000
  50 #define RCR_STRIP_CRC 0x0200
  51 #define RCR_RXEN      0x0100
  52
  53 #define TCR_EPH_LOOP  0x2000
  54 #define TCR_NOCRC     0x0100
  55 #define TCR_PAD_EN    0x0080
  56 #define TCR_FORCOL    0x0004
  57 #define TCR_LOOP      0x0002
  58 #define TCR_TXEN      0x0001
  59
  60 #define INT_MD        0x80
  61 #define INT_ERCV      0x40
  62 #define INT_EPH       0x20
  63 #define INT_RX_OVRN   0x10
  64 #define INT_ALLOC     0x08
  65 #define INT_TX_EMPTY  0x04
  66 #define INT_TX        0x02
  67 #define INT_RCV       0x01
  68
  69 #define CTR_AUTO_RELEASE  0x0800
  70 #define CTR_RELOAD        0x0002
  71 #define CTR_STORE         0x0001
  72
  73 #define RS_ALGNERR      0x8000
  74 #define RS_BRODCAST     0x4000
  75 #define RS_BADCRC       0x2000
  76 #define RS_ODDFRAME     0x1000
  77 #define RS_TOOLONG      0x0800
  78 #define RS_TOOSHORT     0x0400
  79 #define RS_MULTICAST    0x0001
  80
  81 /* Update interrupt status.  */
  82 static void smc91c111_update(smc91c111_state *s)
  83 {
  84     int level;
  85
  86     if (s->tx_fifo_len == 0)
  87         s->int_level |= INT_TX_EMPTY;
  88     if (s->tx_fifo_done_len != 0)
  89         s->int_level |= INT_TX;
  90     level = (s->int_level & s->int_mask) != 0;
  91     qemu_set_irq(s->irq, level);
  92 }
  93
  94 /* Try to allocate a packet.  Returns 0x80 on failure.  */
  95 static int smc91c111_allocate_packet(smc91c111_state *s)
  96 {
  97     int i;
  98     if (s->allocated == (1 << NUM_PACKETS) - 1) {
  99         return 0x80;
 100     }
 101
 102     for (i = 0; i < NUM_PACKETS; i++) {
 103         if ((s->allocated & (1 << i)) == 0)
 104             break;
 105     }
 106     s->allocated |= 1 << i;
 107     return i;
 108 }
 109
 110
 111 /* Process a pending TX allocate.  */
 112 static void smc91c111_tx_alloc(smc91c111_state *s)
 113 {
 114     s->tx_alloc = smc91c111_allocate_packet(s);
 115     if (s->tx_alloc == 0x80)
 116         return;
 117     s->int_level |= INT_ALLOC;
 118     smc91c111_update(s);
 119 }
 120
 121 /* Remove and item from the RX FIFO.  */
 122 static void smc91c111_pop_rx_fifo(smc91c111_state *s)
 123 {
 124     int i;
 125
 126     s->rx_fifo_len--;
 127     if (s->rx_fifo_len) {
 128         for (i = 0; i < s->rx_fifo_len; i++)
 129             s->rx_fifo[i] = s->rx_fifo[i + 1];
 130         s->int_level |= INT_RCV;
 131     } else {
 132         s->int_level &= ~INT_RCV;
 133     }
 134     smc91c111_update(s);
 135 }
 136
 137 /* Remove an item from the TX completion FIFO.  */
 138 static void smc91c111_pop_tx_fifo_done(smc91c111_state *s)
 139 {
 140     int i;
 141
 142     if (s->tx_fifo_done_len == 0)
 143         return;
 144     s->tx_fifo_done_len--;
 145     for (i = 0; i < s->tx_fifo_done_len; i++)
 146         s->tx_fifo_done[i] = s->tx_fifo_done[i + 1];
 147 }
 148
 149 /* Release the memory allocated to a packet.  */
 150 static void smc91c111_release_packet(smc91c111_state *s, int packet)
 151 {
 152     s->allocated &= ~(1 << packet);
 153     if (s->tx_alloc == 0x80)
 154         smc91c111_tx_alloc(s);
 155 }
 156
 157 /* Flush the TX FIFO.  */
 158 static void smc91c111_do_tx(smc91c111_state *s)
 159 {
 160     int i;
 161     int len;
 162     int control;
 163     int add_crc;
 164     int packetnum;
 165     uint8_t *p;
 166
 167     if ((s->tcr & TCR_TXEN) == 0)
 168         return;
 169     if (s->tx_fifo_len == 0)
 170         return;
 171     for (i = 0; i < s->tx_fifo_len; i++) {
 172         packetnum = s->tx_fifo[i];
 173         p = &s->data[packetnum][0];
 174         /* Set status word.  */
 175         *(p++) = 0x01;
 176         *(p++) = 0x40;
 177         len = *(p++);
 178         len |= ((int)*(p++)) << 8;
 179         len -= 6;
 180         control = p[len + 1];
 181         if (control & 0x20)
 182             len++;
 183         /* ??? This overwrites the data following the buffer.
 184            Don't know what real hardware does.  */
 185         if (len < 64 && (s->tcr & TCR_PAD_EN)) {
 186             memset(p + len, 0, 64 - len);
 187             len = 64;
 188         }
 189 #if 0
 190         /* The card is supposed to append the CRC to the frame.  However
 191            none of the other network traffic has the CRC appended.
 192            Suspect this is low level ethernet detail we don't need to worry
 193            about.  */
 194         add_crc = (control & 0x10) || (s->tcr & TCR_NOCRC) == 0;
 195         if (add_crc) {
 196             uint32_t crc;
 197
 198             crc = crc32(~0, p, len);
 199             memcpy(p + len, &crc, 4);
 200             len += 4;
 201         }
 202 #else
 203         add_crc = 0;
 204 #endif
 205         if (s->ctr & CTR_AUTO_RELEASE)
 206             /* Race?  */
 207             smc91c111_release_packet(s, packetnum);
 208         else if (s->tx_fifo_done_len < NUM_PACKETS)
 209             s->tx_fifo_done[s->tx_fifo_done_len++] = packetnum;
 210         qemu_send_packet(&s->nic->nc, p, len);
 211     }
 212     s->tx_fifo_len = 0;
 213     smc91c111_update(s);
 214 }
 215
 216 /* Add a packet to the TX FIFO.  */
 217 static void smc91c111_queue_tx(smc91c111_state *s, int packet)
 218 {
 219     if (s->tx_fifo_len == NUM_PACKETS)
 220         return;
 221     s->tx_fifo[s->tx_fifo_len++] = packet;
 222     smc91c111_do_tx(s);
 223 }
 224
 225 static void smc91c111_reset(smc91c111_state *s)
 226 {
 227     s->bank = 0;
 228     s->tx_fifo_len = 0;
 229     s->tx_fifo_done_len = 0;
 230     s->rx_fifo_len = 0;
 231     s->allocated = 0;
 232     s->packet_num = 0;
 233     s->tx_alloc = 0;
 234     s->tcr = 0;
 235     s->rcr = 0;
 236     s->cr = 0xa0b1;
 237     s->ctr = 0x1210;
 238     s->ptr = 0;
 239     s->ercv = 0x1f;
 240     s->int_level = INT_TX_EMPTY;
 241     s->int_mask = 0;
 242     smc91c111_update(s);
 243 }
 244
 245 #define SET_LOW(name, val) s->name = (s->name & 0xff00) | val
 246 #define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8)
 247
 248 static void smc91c111_writeb(void *opaque, target_phys_addr_t offset,
 249                              uint32_t value)
 250 {
 251     smc91c111_state *s = (smc91c111_state *)opaque;
 252
 253     offset = offset & 0xf;
 254     if (offset == 14) {
 255         s->bank = value;
 256         return;
 257     }
 258     if (offset == 15)
 259         return;
 260     switch (s->bank) {
 261     case 0:
 262         switch (offset) {
 263         case 0: /* TCR */
 264             SET_LOW(tcr, value);
 265             return;
 266         case 1:
 267             SET_HIGH(tcr, value);
 268             return;
 269         case 4: /* RCR */
 270             SET_LOW(rcr, value);
 271             return;
 272         case 5:
 273             SET_HIGH(rcr, value);
 274             if (s->rcr & RCR_SOFT_RST)
 275                 smc91c111_reset(s);
 276             return;
 277         case 10: case 11: /* RPCR */
 278             /* Ignored */
 279             return;
 280         }
 281         break;
 282
 283     case 1:
 284         switch (offset) {
 285         case 0: /* CONFIG */
 286             SET_LOW(cr, value);
 287             return;
 288         case 1:
 289             SET_HIGH(cr,value);
 290             return;
 291         case 2: case 3: /* BASE */
 292         case 4: case 5: case 6: case 7: case 8: case 9: /* IA */
 293             /* Not implemented.  */
 294             return;
 295         case 10: /* Genral Purpose */
 296             SET_LOW(gpr, value);
 297             return;
 298         case 11:
 299             SET_HIGH(gpr, value);
 300             return;
 301         case 12: /* Control */
 302             if (value & 1)
 303                 fprintf(stderr, "smc91c111:EEPROM store not implemented\n");
 304             if (value & 2)
 305                 fprintf(stderr, "smc91c111:EEPROM reload not implemented\n");
 306             value &= ~3;
 307             SET_LOW(ctr, value);
 308             return;
 309         case 13:
 310             SET_HIGH(ctr, value);
 311             return;
 312         }
 313         break;
 314
 315     case 2:
 316         switch (offset) {
 317         case 0: /* MMU Command */
 318             switch (value >> 5) {
 319             case 0: /* no-op */
 320                 break;
 321             case 1: /* Allocate for TX.  */
 322                 s->tx_alloc = 0x80;
 323                 s->int_level &= ~INT_ALLOC;
 324                 smc91c111_update(s);
 325                 smc91c111_tx_alloc(s);
 326                 break;
 327             case 2: /* Reset MMU.  */
 328                 s->allocated = 0;
 329                 s->tx_fifo_len = 0;
 330                 s->tx_fifo_done_len = 0;
 331                 s->rx_fifo_len = 0;
 332                 s->tx_alloc = 0;
 333                 break;
 334             case 3: /* Remove from RX FIFO.  */
 335                 smc91c111_pop_rx_fifo(s);
 336                 break;
 337             case 4: /* Remove from RX FIFO and release.  */
 338                 if (s->rx_fifo_len > 0) {
 339                     smc91c111_release_packet(s, s->rx_fifo[0]);
 340                 }
 341                 smc91c111_pop_rx_fifo(s);
 342                 break;
 343             case 5: /* Release.  */
 344                 smc91c111_release_packet(s, s->packet_num);
 345                 break;
 346             case 6: /* Add to TX FIFO.  */
 347                 smc91c111_queue_tx(s, s->packet_num);
 348                 break;
 349             case 7: /* Reset TX FIFO.  */
 350                 s->tx_fifo_len = 0;
 351                 s->tx_fifo_done_len = 0;
 352                 break;
 353             }
 354             return;
 355         case 1:
 356             /* Ignore.  */
 357             return;
 358         case 2: /* Packet Number Register */
 359             s->packet_num = value;
 360             return;
 361         case 3: case 4: case 5:
 362             /* Should be readonly, but linux writes to them anyway. Ignore.  */
 363             return;
 364         case 6: /* Pointer */
 365             SET_LOW(ptr, value);
 366             return;
 367         case 7:
 368             SET_HIGH(ptr, value);
 369             return;
 370         case 8: case 9: case 10: case 11: /* Data */
 371             {
 372                 int p;
 373                 int n;
 374
 375                 if (s->ptr & 0x8000)
 376                     n = s->rx_fifo[0];
 377                 else
 378                     n = s->packet_num;
 379                 p = s->ptr & 0x07ff;
 380                 if (s->ptr & 0x4000) {
 381                     s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x7ff);
 382                 } else {
 383                     p += (offset & 3);
 384                 }
 385                 s->data[n][p] = value;
 386             }
 387             return;
 388         case 12: /* Interrupt ACK.  */
 389             s->int_level &= ~(value & 0xd6);
 390             if (value & INT_TX)
 391                 smc91c111_pop_tx_fifo_done(s);
 392             smc91c111_update(s);
 393             return;
 394         case 13: /* Interrupt mask.  */
 395             s->int_mask = value;
 396             smc91c111_update(s);
 397             return;
 398         }
 399         break;;
 400
 401     case 3:
 402         switch (offset) {
 403         case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
 404             /* Multicast table.  */
 405             /* Not implemented.  */
 406             return;
 407         case 8: case 9: /* Management Interface.  */
 408             /* Not implemented.  */
 409             return;
 410         case 12: /* Early receive.  */
 411             s->ercv = value & 0x1f;
 412         case 13:
 413             /* Ignore.  */
 414             return;
 415         }
 416         break;
 417     }
 418     hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset);
 419 }
 420
 421 static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
 422 {
 423     smc91c111_state *s = (smc91c111_state *)opaque;
 424
 425     offset = offset & 0xf;
 426     if (offset == 14) {
 427         return s->bank;
 428     }
 429     if (offset == 15)
 430         return 0x33;
 431     switch (s->bank) {
 432     case 0:
 433         switch (offset) {
 434         case 0: /* TCR */
 435             return s->tcr & 0xff;
 436         case 1:
 437             return s->tcr >> 8;
 438         case 2: /* EPH Status */
 439             return 0;
 440         case 3:
 441             return 0x40;
 442         case 4: /* RCR */
 443             return s->rcr & 0xff;
 444         case 5:
 445             return s->rcr >> 8;
 446         case 6: /* Counter */
 447         case 7:
 448             /* Not implemented.  */
 449             return 0;
 450         case 8: /* Memory size.  */
 451             return NUM_PACKETS;
 452         case 9: /* Free memory available.  */
 453             {
 454                 int i;
 455                 int n;
 456                 n = 0;
 457                 for (i = 0; i < NUM_PACKETS; i++) {
 458                     if (s->allocated & (1 << i))
 459                         n++;
 460                 }
 461                 return n;
 462             }
 463         case 10: case 11: /* RPCR */
 464             /* Not implemented.  */
 465             return 0;
 466         }
 467         break;
 468
 469     case 1:
 470         switch (offset) {
 471         case 0: /* CONFIG */
 472             return s->cr & 0xff;
 473         case 1:
 474             return s->cr >> 8;
 475         case 2: case 3: /* BASE */
 476             /* Not implemented.  */
 477             return 0;
 478         case 4: case 5: case 6: case 7: case 8: case 9: /* IA */
 479             return s->conf.macaddr.a[offset - 4];
 480         case 10: /* General Purpose */
 481             return s->gpr & 0xff;
 482         case 11:
 483             return s->gpr >> 8;
 484         case 12: /* Control */
 485             return s->ctr & 0xff;
 486         case 13:
 487             return s->ctr >> 8;
 488         }
 489         break;
 490
 491     case 2:
 492         switch (offset) {
 493         case 0: case 1: /* MMUCR Busy bit.  */
 494             return 0;
 495         case 2: /* Packet Number.  */
 496             return s->packet_num;
 497         case 3: /* Allocation Result.  */
 498             return s->tx_alloc;
 499         case 4: /* TX FIFO */
 500             if (s->tx_fifo_done_len == 0)
 501                 return 0x80;
 502             else
 503                 return s->tx_fifo_done[0];
 504         case 5: /* RX FIFO */
 505             if (s->rx_fifo_len == 0)
 506                 return 0x80;
 507             else
 508                 return s->rx_fifo[0];
 509         case 6: /* Pointer */
 510             return s->ptr & 0xff;
 511         case 7:
 512             return (s->ptr >> 8) & 0xf7;
 513         case 8: case 9: case 10: case 11: /* Data */
 514             {
 515                 int p;
 516                 int n;
 517
 518                 if (s->ptr & 0x8000)
 519                     n = s->rx_fifo[0];
 520                 else
 521                     n = s->packet_num;
 522                 p = s->ptr & 0x07ff;
 523                 if (s->ptr & 0x4000) {
 524                     s->ptr = (s->ptr & 0xf800) | ((s->ptr + 1) & 0x07ff);
 525                 } else {
 526                     p += (offset & 3);
 527                 }
 528                 return s->data[n][p];
 529             }
 530         case 12: /* Interrupt status.  */
 531             return s->int_level;
 532         case 13: /* Interrupt mask.  */
 533             return s->int_mask;
 534         }
 535         break;
 536
 537     case 3:
 538         switch (offset) {
 539         case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
 540             /* Multicast table.  */
 541             /* Not implemented.  */
 542             return 0;
 543         case 8: /* Management Interface.  */
 544             /* Not implemented.  */
 545             return 0x30;
 546         case 9:
 547             return 0x33;
 548         case 10: /* Revision.  */
 549             return 0x91;
 550         case 11:
 551             return 0x33;
 552         case 12:
 553             return s->ercv;
 554         case 13:
 555             return 0;
 556         }
 557         break;
 558     }
 559     hw_error("smc91c111_read: Bad reg %d:%x\n", s->bank, (int)offset);
 560     return 0;
 561 }
 562
 563 static void smc91c111_writew(void *opaque, target_phys_addr_t offset,
 564                              uint32_t value)
 565 {
 566     smc91c111_writeb(opaque, offset, value & 0xff);
 567     smc91c111_writeb(opaque, offset + 1, value >> 8);
 568 }
 569
 570 static void smc91c111_writel(void *opaque, target_phys_addr_t offset,
 571                              uint32_t value)
 572 {
 573     /* 32-bit writes to offset 0xc only actually write to the bank select
 574        register (offset 0xe)  */
 575     if (offset != 0xc)
 576         smc91c111_writew(opaque, offset, value & 0xffff);
 577     smc91c111_writew(opaque, offset + 2, value >> 16);
 578 }
 579
 580 static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset)
 581 {
 582     uint32_t val;
 583     val = smc91c111_readb(opaque, offset);
 584     val |= smc91c111_readb(opaque, offset + 1) << 8;
 585     return val;
 586 }
 587
 588 static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset)
 589 {
 590     uint32_t val;
 591     val = smc91c111_readw(opaque, offset);
 592     val |= smc91c111_readw(opaque, offset + 2) << 16;
 593     return val;
 594 }
 595
 596 static int smc91c111_can_receive(VLANClientState *nc)
 597 {
 598     smc91c111_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 599
 600     if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST))
 601         return 1;
 602     if (s->allocated == (1 << NUM_PACKETS) - 1)
 603         return 0;
 604     return 1;
 605 }
 606
 607 static ssize_t smc91c111_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
 608 {
 609     smc91c111_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 610     int status;
 611     int packetsize;
 612     uint32_t crc;
 613     int packetnum;
 614     uint8_t *p;
 615
 616     if ((s->rcr & RCR_RXEN) == 0 || (s->rcr & RCR_SOFT_RST))
 617         return -1;
 618     /* Short packets are padded with zeros.  Receiving a packet
 619        < 64 bytes long is considered an error condition.  */
 620     if (size < 64)
 621         packetsize = 64;
 622     else
 623         packetsize = (size & ~1);
 624     packetsize += 6;
 625     crc = (s->rcr & RCR_STRIP_CRC) == 0;
 626     if (crc)
 627         packetsize += 4;
 628     /* TODO: Flag overrun and receive errors.  */
 629     if (packetsize > 2048)
 630         return -1;
 631     packetnum = smc91c111_allocate_packet(s);
 632     if (packetnum == 0x80)
 633         return -1;
 634     s->rx_fifo[s->rx_fifo_len++] = packetnum;
 635
 636     p = &s->data[packetnum][0];
 637     /* ??? Multicast packets?  */
 638     status = 0;
 639     if (size > 1518)
 640         status |= RS_TOOLONG;
 641     if (size & 1)
 642         status |= RS_ODDFRAME;
 643     *(p++) = status & 0xff;
 644     *(p++) = status >> 8;
 645     *(p++) = packetsize & 0xff;
 646     *(p++) = packetsize >> 8;
 647     memcpy(p, buf, size & ~1);
 648     p += (size & ~1);
 649     /* Pad short packets.  */
 650     if (size < 64) {
 651         int pad;
 652
 653         if (size & 1)
 654             *(p++) = buf[size - 1];
 655         pad = 64 - size;
 656         memset(p, 0, pad);
 657         p += pad;
 658         size = 64;
 659     }
 660     /* It's not clear if the CRC should go before or after the last byte in
 661        odd sized packets.  Linux disables the CRC, so that's no help.
 662        The pictures in the documentation show the CRC aligned on a 16-bit
 663        boundary before the last odd byte, so that's what we do.  */
 664     if (crc) {
 665         crc = crc32(~0, buf, size);
 666         *(p++) = crc & 0xff; crc >>= 8;
 667         *(p++) = crc & 0xff; crc >>= 8;
 668         *(p++) = crc & 0xff; crc >>= 8;
 669         *(p++) = crc & 0xff; crc >>= 8;
 670     }
 671     if (size & 1) {
 672         *(p++) = buf[size - 1];
 673         *(p++) = 0x60;
 674     } else {
 675         *(p++) = 0;
 676         *(p++) = 0x40;
 677     }
 678     /* TODO: Raise early RX interrupt?  */
 679     s->int_level |= INT_RCV;
 680     smc91c111_update(s);
 681
 682     return size;
 683 }
 684
 685 static CPUReadMemoryFunc * const smc91c111_readfn[] = {
 686     smc91c111_readb,
 687     smc91c111_readw,
 688     smc91c111_readl
 689 };
 690
 691 static CPUWriteMemoryFunc * const smc91c111_writefn[] = {
 692     smc91c111_writeb,
 693     smc91c111_writew,
 694     smc91c111_writel
 695 };
 696
 697 static void smc91c111_cleanup(VLANClientState *nc)
 698 {
 699     smc91c111_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 700
 701     s->nic = NULL;
 702 }
 703
 704 static NetClientInfo net_smc91c111_info = {
 705     .type = NET_CLIENT_TYPE_NIC,
 706     .size = sizeof(NICState),
 707     .can_receive = smc91c111_can_receive,
 708     .receive = smc91c111_receive,
 709     .cleanup = smc91c111_cleanup,
 710 };
 711
 712 static int smc91c111_init1(SysBusDevice *dev)
 713 {
 714     smc91c111_state *s = FROM_SYSBUS(smc91c111_state, dev);
 715
 716     s->mmio_index = cpu_register_io_memory(smc91c111_readfn,
 717                                            smc91c111_writefn, s);
 718     sysbus_init_mmio(dev, 16, s->mmio_index);
 719     sysbus_init_irq(dev, &s->irq);
 720     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 721
 722     smc91c111_reset(s);
 723
 724     s->nic = qemu_new_nic(&net_smc91c111_info, &s->conf,
 725                           dev->qdev.info->name, dev->qdev.id, s);
 726     qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
 727     /* ??? Save/restore.  */
 728     return 0;
 729 }
 730
 731 static SysBusDeviceInfo smc91c111_info = {
 732     .init = smc91c111_init1,
 733     .qdev.name  = "smc91c111",
 734     .qdev.size  = sizeof(smc91c111_state),
 735     .qdev.props = (Property[]) {
 736         DEFINE_NIC_PROPERTIES(smc91c111_state, conf),
 737         DEFINE_PROP_END_OF_LIST(),
 738     }
 739 };
 740
 741 static void smc91c111_register_devices(void)
 742 {
 743     sysbus_register_withprop(&smc91c111_info);
 744 }
 745
 746 /* Legacy helper function.  Should go away when machine config files are
 747    implemented.  */
 748 void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq)
 749 {
 750     DeviceState *dev;
 751     SysBusDevice *s;
 752
 753     qemu_check_nic_model(nd, "smc91c111");
 754     dev = qdev_create(NULL, "smc91c111");
 755     qdev_set_nic_properties(dev, nd);
 756     qdev_init_nofail(dev);
 757     s = sysbus_from_qdev(dev);
 758     sysbus_mmio_map(s, 0, base);
 759     sysbus_connect_irq(s, 0, irq);
 760 }
 761
 762 device_init(smc91c111_register_devices)