hw/spapr_pci.c

   1 /*
   2  * QEMU sPAPR PCI host originated from Uninorth PCI host
   3  *
   4  * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
   5  * Copyright (C) 2011 David Gibson, IBM Corporation.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28 #include "hw/spapr.h"
  29 #include "hw/spapr_pci.h"
  30 #include "exec-memory.h"
  31 #include <libfdt.h>
  32
  33 #include "hw/pci_internals.h"
  34
  35 static const uint32_t bars[] = {
  36     PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1,
  37     PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_3,
  38     PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5
  39     /*, PCI_ROM_ADDRESS*/
  40 };
  41
  42 static PCIDevice *find_dev(sPAPREnvironment *spapr,
  43                            uint64_t buid, uint32_t config_addr)
  44 {
  45     DeviceState *qdev;
  46     int devfn = (config_addr >> 8) & 0xFF;
  47     sPAPRPHBState *phb;
  48
  49     QLIST_FOREACH(phb, &spapr->phbs, list) {
  50         if (phb->buid != buid) {
  51             continue;
  52         }
  53
  54         QTAILQ_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) {
  55             PCIDevice *dev = (PCIDevice *)qdev;
  56             if (dev->devfn == devfn) {
  57                 return dev;
  58             }
  59         }
  60     }
  61
  62     return NULL;
  63 }
  64
  65 static uint32_t rtas_pci_cfgaddr(uint32_t arg)
  66 {
  67     return ((arg >> 20) & 0xf00) | (arg & 0xff);
  68 }
  69
  70 static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr,
  71                                      uint32_t token, uint32_t nargs,
  72                                      target_ulong args,
  73                                      uint32_t nret, target_ulong rets)
  74 {
  75     uint32_t val, size, addr;
  76     uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
  77     PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
  78
  79     if (!dev) {
  80         rtas_st(rets, 0, -1);
  81         return;
  82     }
  83     size = rtas_ld(args, 3);
  84     addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
  85     val = pci_default_read_config(dev, addr, size);
  86     rtas_st(rets, 0, 0);
  87     rtas_st(rets, 1, val);
  88 }
  89
  90 static void rtas_read_pci_config(sPAPREnvironment *spapr,
  91                                  uint32_t token, uint32_t nargs,
  92                                  target_ulong args,
  93                                  uint32_t nret, target_ulong rets)
  94 {
  95     uint32_t val, size, addr;
  96     PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
  97
  98     if (!dev) {
  99         rtas_st(rets, 0, -1);
 100         return;
 101     }
 102     size = rtas_ld(args, 1);
 103     addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
 104     val = pci_default_read_config(dev, addr, size);
 105     rtas_st(rets, 0, 0);
 106     rtas_st(rets, 1, val);
 107 }
 108
 109 static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr,
 110                                       uint32_t token, uint32_t nargs,
 111                                       target_ulong args,
 112                                       uint32_t nret, target_ulong rets)
 113 {
 114     uint32_t val, size, addr;
 115     uint64_t buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2);
 116     PCIDevice *dev = find_dev(spapr, buid, rtas_ld(args, 0));
 117
 118     if (!dev) {
 119         rtas_st(rets, 0, -1);
 120         return;
 121     }
 122     val = rtas_ld(args, 4);
 123     size = rtas_ld(args, 3);
 124     addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
 125     pci_default_write_config(dev, addr, val, size);
 126     rtas_st(rets, 0, 0);
 127 }
 128
 129 static void rtas_write_pci_config(sPAPREnvironment *spapr,
 130                                   uint32_t token, uint32_t nargs,
 131                                   target_ulong args,
 132                                   uint32_t nret, target_ulong rets)
 133 {
 134     uint32_t val, size, addr;
 135     PCIDevice *dev = find_dev(spapr, 0, rtas_ld(args, 0));
 136
 137     if (!dev) {
 138         rtas_st(rets, 0, -1);
 139         return;
 140     }
 141     val = rtas_ld(args, 2);
 142     size = rtas_ld(args, 1);
 143     addr = rtas_pci_cfgaddr(rtas_ld(args, 0));
 144     pci_default_write_config(dev, addr, val, size);
 145     rtas_st(rets, 0, 0);
 146 }
 147
 148 static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
 149 {
 150     /*
 151      * Here we need to convert pci_dev + irq_num to some unique value
 152      * which is less than number of IRQs on the specific bus (now it
 153      * is 16).  At the moment irq_num == device_id (number of the
 154      * slot?)
 155      * FIXME: we should swizzle in fn and irq_num
 156      */
 157     return (pci_dev->devfn >> 3) % SPAPR_PCI_NUM_LSI;
 158 }
 159
 160 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
 161 {
 162     /*
 163      * Here we use the number returned by pci_spapr_map_irq to find a
 164      * corresponding qemu_irq.
 165      */
 166     sPAPRPHBState *phb = opaque;
 167
 168     qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
 169 }
 170
 171 static int spapr_phb_init(SysBusDevice *s)
 172 {
 173     sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
 174     int i;
 175
 176     /* Initialize the LSI table */
 177     for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) {
 178         qemu_irq qirq;
 179         uint32_t num;
 180
 181         qirq = spapr_allocate_irq(0, &num);
 182         if (!qirq) {
 183             return -1;
 184         }
 185
 186         phb->lsi_table[i].dt_irq = num;
 187         phb->lsi_table[i].qirq = qirq;
 188     }
 189
 190     return 0;
 191 }
 192
 193 static int spapr_main_pci_host_init(PCIDevice *d)
 194 {
 195     return 0;
 196 }
 197
 198 static PCIDeviceInfo spapr_main_pci_host_info = {
 199     .qdev.name = "spapr-pci-host-bridge",
 200     .qdev.size = sizeof(PCIDevice),
 201     .init      = spapr_main_pci_host_init,
 202 };
 203
 204 static void spapr_register_devices(void)
 205 {
 206     sysbus_register_dev("spapr-pci-host-bridge", sizeof(sPAPRPHBState),
 207                         spapr_phb_init);
 208     pci_qdev_register(&spapr_main_pci_host_info);
 209 }
 210
 211 device_init(spapr_register_devices)
 212
 213 static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
 214                               unsigned size)
 215 {
 216     switch (size) {
 217     case 1:
 218         return cpu_inb(addr);
 219     case 2:
 220         return cpu_inw(addr);
 221     case 4:
 222         return cpu_inl(addr);
 223     }
 224     assert(0);
 225 }
 226
 227 static void spapr_io_write(void *opaque, target_phys_addr_t addr,
 228                            uint64_t data, unsigned size)
 229 {
 230     switch (size) {
 231     case 1:
 232         cpu_outb(addr, data);
 233         return;
 234     case 2:
 235         cpu_outw(addr, data);
 236         return;
 237     case 4:
 238         cpu_outl(addr, data);
 239         return;
 240     }
 241     assert(0);
 242 }
 243
 244 static MemoryRegionOps spapr_io_ops = {
 245     .endianness = DEVICE_LITTLE_ENDIAN,
 246     .read = spapr_io_read,
 247     .write = spapr_io_write
 248 };
 249
 250 void spapr_create_phb(sPAPREnvironment *spapr,
 251                       const char *busname, uint64_t buid,
 252                       uint64_t mem_win_addr, uint64_t mem_win_size,
 253                       uint64_t io_win_addr)
 254 {
 255     DeviceState *dev;
 256     SysBusDevice *s;
 257     sPAPRPHBState *phb;
 258     PCIBus *bus;
 259     char namebuf[strlen(busname)+11];
 260
 261     dev = qdev_create(NULL, "spapr-pci-host-bridge");
 262     qdev_init_nofail(dev);
 263     s = sysbus_from_qdev(dev);
 264     phb = FROM_SYSBUS(sPAPRPHBState, s);
 265
 266     phb->mem_win_addr = mem_win_addr;
 267
 268     sprintf(namebuf, "%s-mem", busname);
 269     memory_region_init(&phb->memspace, namebuf, INT64_MAX);
 270
 271     sprintf(namebuf, "%s-memwindow", busname);
 272     memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace,
 273                              SPAPR_PCI_MEM_WIN_BUS_OFFSET, mem_win_size);
 274     memory_region_add_subregion(get_system_memory(), mem_win_addr,
 275                                 &phb->memwindow);
 276
 277     phb->io_win_addr = io_win_addr;
 278
 279     /* On ppc, we only have MMIO no specific IO space from the CPU
 280      * perspective.  In theory we ought to be able to embed the PCI IO
 281      * memory region direction in the system memory space.  However,
 282      * if any of the IO BAR subregions use the old_portio mechanism,
 283      * that won't be processed properly unless accessed from the
 284      * system io address space.  This hack to bounce things via
 285      * system_io works around the problem until all the users of
 286      * old_portion are updated */
 287     sprintf(namebuf, "%s-io", busname);
 288     memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE);
 289     /* FIXME: fix to support multiple PHBs */
 290     memory_region_add_subregion(get_system_io(), 0, &phb->iospace);
 291
 292     sprintf(namebuf, "%s-iowindow", busname);
 293     memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb,
 294                           namebuf, SPAPR_PCI_IO_WIN_SIZE);
 295     memory_region_add_subregion(get_system_memory(), io_win_addr,
 296                                 &phb->iowindow);
 297
 298     phb->host_state.bus = bus = pci_register_bus(&phb->busdev.qdev, busname,
 299                                                  pci_spapr_set_irq,
 300                                                  pci_spapr_map_irq,
 301                                                  phb,
 302                                                  &phb->memspace, &phb->iospace,
 303                                                  PCI_DEVFN(0, 0),
 304                                                  SPAPR_PCI_NUM_LSI);
 305
 306     spapr_rtas_register("read-pci-config", rtas_read_pci_config);
 307     spapr_rtas_register("write-pci-config", rtas_write_pci_config);
 308     spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config);
 309     spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config);
 310
 311     QLIST_INSERT_HEAD(&spapr->phbs, phb, list);
 312
 313     /* pci_bus_set_mem_base(bus, mem_va_start - SPAPR_PCI_MEM_BAR_START); */
 314 }
 315
 316 /* Macros to operate with address in OF binding to PCI */
 317 #define b_x(x, p, l)    (((x) & ((1<<(l))-1)) << (p))
 318 #define b_n(x)          b_x((x), 31, 1) /* 0 if relocatable */
 319 #define b_p(x)          b_x((x), 30, 1) /* 1 if prefetchable */
 320 #define b_t(x)          b_x((x), 29, 1) /* 1 if the address is aliased */
 321 #define b_ss(x)         b_x((x), 24, 2) /* the space code */
 322 #define b_bbbbbbbb(x)   b_x((x), 16, 8) /* bus number */
 323 #define b_ddddd(x)      b_x((x), 11, 5) /* device number */
 324 #define b_fff(x)        b_x((x), 8, 3)  /* function number */
 325 #define b_rrrrrrrr(x)   b_x((x), 0, 8)  /* register number */
 326
 327 static uint32_t regtype_to_ss(uint8_t type)
 328 {
 329     if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 330         return 3;
 331     }
 332     if (type == PCI_BASE_ADDRESS_SPACE_IO) {
 333         return 1;
 334     }
 335     return 2;
 336 }
 337
 338 int spapr_populate_pci_devices(sPAPRPHBState *phb,
 339                                uint32_t xics_phandle,
 340                                void *fdt)
 341 {
 342     PCIBus *bus = phb->host_state.bus;
 343     int bus_off, node_off = 0, devid, fn, i, n, devices;
 344     DeviceState *qdev;
 345     char nodename[256];
 346     struct {
 347         uint32_t hi;
 348         uint64_t addr;
 349         uint64_t size;
 350     } __attribute__((packed)) reg[PCI_NUM_REGIONS + 1],
 351           assigned_addresses[PCI_NUM_REGIONS];
 352     uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
 353     struct {
 354         uint32_t hi;
 355         uint64_t child;
 356         uint64_t parent;
 357         uint64_t size;
 358     } __attribute__((packed)) ranges[] = {
 359         {
 360             cpu_to_be32(b_ss(1)), cpu_to_be64(0),
 361             cpu_to_be64(phb->io_win_addr),
 362             cpu_to_be64(memory_region_size(&phb->iospace)),
 363         },
 364         {
 365             cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
 366             cpu_to_be64(phb->mem_win_addr),
 367             cpu_to_be64(memory_region_size(&phb->memwindow)),
 368         },
 369     };
 370     uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
 371     uint32_t interrupt_map_mask[] = {
 372         cpu_to_be32(b_ddddd(-1)|b_fff(-1)), 0x0, 0x0, 0x0};
 373     uint32_t interrupt_map[bus->nirq][7];
 374
 375     /* Start populating the FDT */
 376     sprintf(nodename, "pci@%" PRIx64, phb->buid);
 377     bus_off = fdt_add_subnode(fdt, 0, nodename);
 378     if (bus_off < 0) {
 379         return bus_off;
 380     }
 381
 382 #define _FDT(exp) \
 383     do { \
 384         int ret = (exp);                                           \
 385         if (ret < 0) {                                             \
 386             return ret;                                            \
 387         }                                                          \
 388     } while (0)
 389
 390     /* Write PHB properties */
 391     _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
 392     _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
 393     _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
 394     _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
 395     _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
 396     _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
 397     _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
 398     _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges)));
 399     _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
 400     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
 401                      &interrupt_map_mask, sizeof(interrupt_map_mask)));
 402     _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
 403
 404     /* Populate PCI devices and allocate IRQs */
 405     devices = 0;
 406     QTAILQ_FOREACH(qdev, &bus->qbus.children, sibling) {
 407         PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
 408         int irq_index = pci_spapr_map_irq(dev, 0);
 409         uint32_t *irqmap = interrupt_map[devices];
 410         uint8_t *config = dev->config;
 411
 412         devid = dev->devfn >> 3;
 413         fn = dev->devfn & 7;
 414
 415         sprintf(nodename, "pci@%u,%u", devid, fn);
 416
 417         /* Allocate interrupt from the map */
 418         if (devid > bus->nirq)  {
 419             printf("Unexpected behaviour in spapr_populate_pci_devices,"
 420                     "wrong devid %u\n", devid);
 421             exit(-1);
 422         }
 423         irqmap[0] = cpu_to_be32(b_ddddd(devid)|b_fff(fn));
 424         irqmap[1] = 0;
 425         irqmap[2] = 0;
 426         irqmap[3] = 0;
 427         irqmap[4] = cpu_to_be32(xics_phandle);
 428         irqmap[5] = cpu_to_be32(phb->lsi_table[irq_index].dt_irq);
 429         irqmap[6] = cpu_to_be32(0x8);
 430
 431         /* Add node to FDT */
 432         node_off = fdt_add_subnode(fdt, bus_off, nodename);
 433         if (node_off < 0) {
 434             return node_off;
 435         }
 436
 437         _FDT(fdt_setprop_cell(fdt, node_off, "vendor-id",
 438                               pci_get_word(&config[PCI_VENDOR_ID])));
 439         _FDT(fdt_setprop_cell(fdt, node_off, "device-id",
 440                               pci_get_word(&config[PCI_DEVICE_ID])));
 441         _FDT(fdt_setprop_cell(fdt, node_off, "revision-id",
 442                               pci_get_byte(&config[PCI_REVISION_ID])));
 443         _FDT(fdt_setprop_cell(fdt, node_off, "class-code",
 444                               pci_get_long(&config[PCI_CLASS_REVISION]) >> 8));
 445         _FDT(fdt_setprop_cell(fdt, node_off, "subsystem-id",
 446                               pci_get_word(&config[PCI_SUBSYSTEM_ID])));
 447         _FDT(fdt_setprop_cell(fdt, node_off, "subsystem-vendor-id",
 448                               pci_get_word(&config[PCI_SUBSYSTEM_VENDOR_ID])));
 449
 450         /* Config space region comes first */
 451         reg[0].hi = cpu_to_be32(
 452             b_n(0) |
 453             b_p(0) |
 454             b_t(0) |
 455             b_ss(0/*config*/) |
 456             b_bbbbbbbb(0) |
 457             b_ddddd(devid) |
 458             b_fff(fn));
 459         reg[0].addr = 0;
 460         reg[0].size = 0;
 461
 462         n = 0;
 463         for (i = 0; i < ARRAY_SIZE(bars); ++i) {
 464             if (0 == dev->io_regions[i].size) {
 465                 continue;
 466             }
 467
 468             reg[n+1].hi = cpu_to_be32(
 469                 b_n(0) |
 470                 b_p(0) |
 471                 b_t(0) |
 472                 b_ss(regtype_to_ss(dev->io_regions[i].type)) |
 473                 b_bbbbbbbb(0) |
 474                 b_ddddd(devid) |
 475                 b_fff(fn) |
 476                 b_rrrrrrrr(bars[i]));
 477             reg[n+1].addr = 0;
 478             reg[n+1].size = cpu_to_be64(dev->io_regions[i].size);
 479
 480             assigned_addresses[n].hi = cpu_to_be32(
 481                 b_n(1) |
 482                 b_p(0) |
 483                 b_t(0) |
 484                 b_ss(regtype_to_ss(dev->io_regions[i].type)) |
 485                 b_bbbbbbbb(0) |
 486                 b_ddddd(devid) |
 487                 b_fff(fn) |
 488                 b_rrrrrrrr(bars[i]));
 489
 490             /*
 491              * Writing zeroes to assigned_addresses causes the guest kernel to
 492              * reassign BARs
 493              */
 494             assigned_addresses[n].addr = cpu_to_be64(dev->io_regions[i].addr);
 495             assigned_addresses[n].size = reg[n+1].size;
 496
 497             ++n;
 498         }
 499         _FDT(fdt_setprop(fdt, node_off, "reg", reg, sizeof(reg[0])*(n+1)));
 500         _FDT(fdt_setprop(fdt, node_off, "assigned-addresses",
 501                          assigned_addresses,
 502                          sizeof(assigned_addresses[0])*(n)));
 503         _FDT(fdt_setprop_cell(fdt, node_off, "interrupts",
 504                               pci_get_byte(&config[PCI_INTERRUPT_PIN])));
 505
 506         ++devices;
 507     }
 508
 509     /* Write interrupt map */
 510     _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
 511                      devices * sizeof(interrupt_map[0])));
 512
 513     return 0;
 514 }