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intc: make HMP 'info irq' and 'info pic' commands use InterruptStatsProvider interface
[mirror_qemu.git] / hw / sparc / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "hw/sparc/sun4m.h"
32 #include "hw/timer/m48t59.h"
33 #include "hw/sparc/sparc32_dma.h"
34 #include "hw/block/fdc.h"
35 #include "sysemu/sysemu.h"
36 #include "net/net.h"
37 #include "hw/boards.h"
38 #include "hw/nvram/openbios_firmware_abi.h"
39 #include "hw/scsi/esp.h"
40 #include "hw/i386/pc.h"
41 #include "hw/isa/isa.h"
42 #include "hw/nvram/fw_cfg.h"
43 #include "hw/char/escc.h"
44 #include "hw/empty_slot.h"
45 #include "hw/loader.h"
46 #include "elf.h"
47 #include "sysemu/block-backend.h"
48 #include "trace.h"
49 #include "qemu/cutils.h"
50
51 /*
52 * Sun4m architecture was used in the following machines:
53 *
54 * SPARCserver 6xxMP/xx
55 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
56 * SPARCclassic X (4/10)
57 * SPARCstation LX/ZX (4/30)
58 * SPARCstation Voyager
59 * SPARCstation 10/xx, SPARCserver 10/xx
60 * SPARCstation 5, SPARCserver 5
61 * SPARCstation 20/xx, SPARCserver 20
62 * SPARCstation 4
63 *
64 * See for example: http://www.sunhelp.org/faq/sunref1.html
65 */
66
67 #define KERNEL_LOAD_ADDR 0x00004000
68 #define CMDLINE_ADDR 0x007ff000
69 #define INITRD_LOAD_ADDR 0x00800000
70 #define PROM_SIZE_MAX (1024 * 1024)
71 #define PROM_VADDR 0xffd00000
72 #define PROM_FILENAME "openbios-sparc32"
73 #define CFG_ADDR 0xd00000510ULL
74 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
75 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
76 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
77
78 #define MAX_CPUS 16
79 #define MAX_PILS 16
80 #define MAX_VSIMMS 4
81
82 #define ESCC_CLOCK 4915200
83
84 struct sun4m_hwdef {
85 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
86 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
87 hwaddr serial_base, fd_base;
88 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
89 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
90 hwaddr bpp_base, dbri_base, sx_base;
91 struct {
92 hwaddr reg_base, vram_base;
93 } vsimm[MAX_VSIMMS];
94 hwaddr ecc_base;
95 uint64_t max_mem;
96 const char * const default_cpu_model;
97 uint32_t ecc_version;
98 uint32_t iommu_version;
99 uint16_t machine_id;
100 uint8_t nvram_machine_id;
101 };
102
103 void DMA_init(ISABus *bus, int high_page_enable)
104 {
105 }
106
107 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
108 Error **errp)
109 {
110 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
111 }
112
113 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
114 const char *cmdline, const char *boot_devices,
115 ram_addr_t RAM_size, uint32_t kernel_size,
116 int width, int height, int depth,
117 int nvram_machine_id, const char *arch)
118 {
119 unsigned int i;
120 uint32_t start, end;
121 uint8_t image[0x1ff0];
122 struct OpenBIOS_nvpart_v1 *part_header;
123 NvramClass *k = NVRAM_GET_CLASS(nvram);
124
125 memset(image, '\0', sizeof(image));
126
127 start = 0;
128
129 // OpenBIOS nvram variables
130 // Variable partition
131 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
132 part_header->signature = OPENBIOS_PART_SYSTEM;
133 pstrcpy(part_header->name, sizeof(part_header->name), "system");
134
135 end = start + sizeof(struct OpenBIOS_nvpart_v1);
136 for (i = 0; i < nb_prom_envs; i++)
137 end = OpenBIOS_set_var(image, end, prom_envs[i]);
138
139 // End marker
140 image[end++] = '\0';
141
142 end = start + ((end - start + 15) & ~15);
143 OpenBIOS_finish_partition(part_header, end - start);
144
145 // free partition
146 start = end;
147 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
148 part_header->signature = OPENBIOS_PART_FREE;
149 pstrcpy(part_header->name, sizeof(part_header->name), "free");
150
151 end = 0x1fd0;
152 OpenBIOS_finish_partition(part_header, end - start);
153
154 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
155 nvram_machine_id);
156
157 for (i = 0; i < sizeof(image); i++) {
158 (k->write)(nvram, i, image[i]);
159 }
160 }
161
162 void cpu_check_irqs(CPUSPARCState *env)
163 {
164 CPUState *cs;
165
166 if (env->pil_in && (env->interrupt_index == 0 ||
167 (env->interrupt_index & ~15) == TT_EXTINT)) {
168 unsigned int i;
169
170 for (i = 15; i > 0; i--) {
171 if (env->pil_in & (1 << i)) {
172 int old_interrupt = env->interrupt_index;
173
174 env->interrupt_index = TT_EXTINT | i;
175 if (old_interrupt != env->interrupt_index) {
176 cs = CPU(sparc_env_get_cpu(env));
177 trace_sun4m_cpu_interrupt(i);
178 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
179 }
180 break;
181 }
182 }
183 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
184 cs = CPU(sparc_env_get_cpu(env));
185 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
186 env->interrupt_index = 0;
187 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
188 }
189 }
190
191 static void cpu_kick_irq(SPARCCPU *cpu)
192 {
193 CPUSPARCState *env = &cpu->env;
194 CPUState *cs = CPU(cpu);
195
196 cs->halted = 0;
197 cpu_check_irqs(env);
198 qemu_cpu_kick(cs);
199 }
200
201 static void cpu_set_irq(void *opaque, int irq, int level)
202 {
203 SPARCCPU *cpu = opaque;
204 CPUSPARCState *env = &cpu->env;
205
206 if (level) {
207 trace_sun4m_cpu_set_irq_raise(irq);
208 env->pil_in |= 1 << irq;
209 cpu_kick_irq(cpu);
210 } else {
211 trace_sun4m_cpu_set_irq_lower(irq);
212 env->pil_in &= ~(1 << irq);
213 cpu_check_irqs(env);
214 }
215 }
216
217 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
218 {
219 }
220
221 static void main_cpu_reset(void *opaque)
222 {
223 SPARCCPU *cpu = opaque;
224 CPUState *cs = CPU(cpu);
225
226 cpu_reset(cs);
227 cs->halted = 0;
228 }
229
230 static void secondary_cpu_reset(void *opaque)
231 {
232 SPARCCPU *cpu = opaque;
233 CPUState *cs = CPU(cpu);
234
235 cpu_reset(cs);
236 cs->halted = 1;
237 }
238
239 static void cpu_halt_signal(void *opaque, int irq, int level)
240 {
241 if (level && current_cpu) {
242 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
243 }
244 }
245
246 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
247 {
248 return addr - 0xf0000000ULL;
249 }
250
251 static unsigned long sun4m_load_kernel(const char *kernel_filename,
252 const char *initrd_filename,
253 ram_addr_t RAM_size)
254 {
255 int linux_boot;
256 unsigned int i;
257 long initrd_size, kernel_size;
258 uint8_t *ptr;
259
260 linux_boot = (kernel_filename != NULL);
261
262 kernel_size = 0;
263 if (linux_boot) {
264 int bswap_needed;
265
266 #ifdef BSWAP_NEEDED
267 bswap_needed = 1;
268 #else
269 bswap_needed = 0;
270 #endif
271 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
272 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
273 if (kernel_size < 0)
274 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
275 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
276 TARGET_PAGE_SIZE);
277 if (kernel_size < 0)
278 kernel_size = load_image_targphys(kernel_filename,
279 KERNEL_LOAD_ADDR,
280 RAM_size - KERNEL_LOAD_ADDR);
281 if (kernel_size < 0) {
282 fprintf(stderr, "qemu: could not load kernel '%s'\n",
283 kernel_filename);
284 exit(1);
285 }
286
287 /* load initrd */
288 initrd_size = 0;
289 if (initrd_filename) {
290 initrd_size = load_image_targphys(initrd_filename,
291 INITRD_LOAD_ADDR,
292 RAM_size - INITRD_LOAD_ADDR);
293 if (initrd_size < 0) {
294 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
295 initrd_filename);
296 exit(1);
297 }
298 }
299 if (initrd_size > 0) {
300 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
301 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
302 if (ldl_p(ptr) == 0x48647253) { // HdrS
303 stl_p(ptr + 16, INITRD_LOAD_ADDR);
304 stl_p(ptr + 20, initrd_size);
305 break;
306 }
307 }
308 }
309 }
310 return kernel_size;
311 }
312
313 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
314 {
315 DeviceState *dev;
316 SysBusDevice *s;
317
318 dev = qdev_create(NULL, "iommu");
319 qdev_prop_set_uint32(dev, "version", version);
320 qdev_init_nofail(dev);
321 s = SYS_BUS_DEVICE(dev);
322 sysbus_connect_irq(s, 0, irq);
323 sysbus_mmio_map(s, 0, addr);
324
325 return s;
326 }
327
328 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
329 void *iommu, qemu_irq *dev_irq, int is_ledma)
330 {
331 DeviceState *dev;
332 SysBusDevice *s;
333
334 dev = qdev_create(NULL, "sparc32_dma");
335 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
336 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
337 qdev_init_nofail(dev);
338 s = SYS_BUS_DEVICE(dev);
339 sysbus_connect_irq(s, 0, parent_irq);
340 *dev_irq = qdev_get_gpio_in(dev, 0);
341 sysbus_mmio_map(s, 0, daddr);
342
343 return s;
344 }
345
346 static void lance_init(NICInfo *nd, hwaddr leaddr,
347 void *dma_opaque, qemu_irq irq)
348 {
349 DeviceState *dev;
350 SysBusDevice *s;
351 qemu_irq reset;
352
353 qemu_check_nic_model(&nd_table[0], "lance");
354
355 dev = qdev_create(NULL, "lance");
356 qdev_set_nic_properties(dev, nd);
357 qdev_prop_set_ptr(dev, "dma", dma_opaque);
358 qdev_init_nofail(dev);
359 s = SYS_BUS_DEVICE(dev);
360 sysbus_mmio_map(s, 0, leaddr);
361 sysbus_connect_irq(s, 0, irq);
362 reset = qdev_get_gpio_in(dev, 0);
363 qdev_connect_gpio_out(dma_opaque, 0, reset);
364 }
365
366 static DeviceState *slavio_intctl_init(hwaddr addr,
367 hwaddr addrg,
368 qemu_irq **parent_irq)
369 {
370 DeviceState *dev;
371 SysBusDevice *s;
372 unsigned int i, j;
373
374 dev = qdev_create(NULL, "slavio_intctl");
375 qdev_init_nofail(dev);
376
377 s = SYS_BUS_DEVICE(dev);
378
379 for (i = 0; i < MAX_CPUS; i++) {
380 for (j = 0; j < MAX_PILS; j++) {
381 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
382 }
383 }
384 sysbus_mmio_map(s, 0, addrg);
385 for (i = 0; i < MAX_CPUS; i++) {
386 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
387 }
388
389 return dev;
390 }
391
392 #define SYS_TIMER_OFFSET 0x10000ULL
393 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
394
395 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
396 qemu_irq *cpu_irqs, unsigned int num_cpus)
397 {
398 DeviceState *dev;
399 SysBusDevice *s;
400 unsigned int i;
401
402 dev = qdev_create(NULL, "slavio_timer");
403 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
404 qdev_init_nofail(dev);
405 s = SYS_BUS_DEVICE(dev);
406 sysbus_connect_irq(s, 0, master_irq);
407 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
408
409 for (i = 0; i < MAX_CPUS; i++) {
410 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
411 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
412 }
413 }
414
415 static qemu_irq slavio_system_powerdown;
416
417 static void slavio_powerdown_req(Notifier *n, void *opaque)
418 {
419 qemu_irq_raise(slavio_system_powerdown);
420 }
421
422 static Notifier slavio_system_powerdown_notifier = {
423 .notify = slavio_powerdown_req
424 };
425
426 #define MISC_LEDS 0x01600000
427 #define MISC_CFG 0x01800000
428 #define MISC_DIAG 0x01a00000
429 #define MISC_MDM 0x01b00000
430 #define MISC_SYS 0x01f00000
431
432 static void slavio_misc_init(hwaddr base,
433 hwaddr aux1_base,
434 hwaddr aux2_base, qemu_irq irq,
435 qemu_irq fdc_tc)
436 {
437 DeviceState *dev;
438 SysBusDevice *s;
439
440 dev = qdev_create(NULL, "slavio_misc");
441 qdev_init_nofail(dev);
442 s = SYS_BUS_DEVICE(dev);
443 if (base) {
444 /* 8 bit registers */
445 /* Slavio control */
446 sysbus_mmio_map(s, 0, base + MISC_CFG);
447 /* Diagnostics */
448 sysbus_mmio_map(s, 1, base + MISC_DIAG);
449 /* Modem control */
450 sysbus_mmio_map(s, 2, base + MISC_MDM);
451 /* 16 bit registers */
452 /* ss600mp diag LEDs */
453 sysbus_mmio_map(s, 3, base + MISC_LEDS);
454 /* 32 bit registers */
455 /* System control */
456 sysbus_mmio_map(s, 4, base + MISC_SYS);
457 }
458 if (aux1_base) {
459 /* AUX 1 (Misc System Functions) */
460 sysbus_mmio_map(s, 5, aux1_base);
461 }
462 if (aux2_base) {
463 /* AUX 2 (Software Powerdown Control) */
464 sysbus_mmio_map(s, 6, aux2_base);
465 }
466 sysbus_connect_irq(s, 0, irq);
467 sysbus_connect_irq(s, 1, fdc_tc);
468 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
469 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
470 }
471
472 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
473 {
474 DeviceState *dev;
475 SysBusDevice *s;
476
477 dev = qdev_create(NULL, "eccmemctl");
478 qdev_prop_set_uint32(dev, "version", version);
479 qdev_init_nofail(dev);
480 s = SYS_BUS_DEVICE(dev);
481 sysbus_connect_irq(s, 0, irq);
482 sysbus_mmio_map(s, 0, base);
483 if (version == 0) { // SS-600MP only
484 sysbus_mmio_map(s, 1, base + 0x1000);
485 }
486 }
487
488 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
489 {
490 DeviceState *dev;
491 SysBusDevice *s;
492
493 dev = qdev_create(NULL, "apc");
494 qdev_init_nofail(dev);
495 s = SYS_BUS_DEVICE(dev);
496 /* Power management (APC) XXX: not a Slavio device */
497 sysbus_mmio_map(s, 0, power_base);
498 sysbus_connect_irq(s, 0, cpu_halt);
499 }
500
501 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
502 int height, int depth)
503 {
504 DeviceState *dev;
505 SysBusDevice *s;
506
507 dev = qdev_create(NULL, "SUNW,tcx");
508 qdev_prop_set_uint32(dev, "vram_size", vram_size);
509 qdev_prop_set_uint16(dev, "width", width);
510 qdev_prop_set_uint16(dev, "height", height);
511 qdev_prop_set_uint16(dev, "depth", depth);
512 qdev_prop_set_uint64(dev, "prom_addr", addr);
513 qdev_init_nofail(dev);
514 s = SYS_BUS_DEVICE(dev);
515
516 /* 10/ROM : FCode ROM */
517 sysbus_mmio_map(s, 0, addr);
518 /* 2/STIP : Stipple */
519 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
520 /* 3/BLIT : Blitter */
521 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
522 /* 5/RSTIP : Raw Stipple */
523 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
524 /* 6/RBLIT : Raw Blitter */
525 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
526 /* 7/TEC : Transform Engine */
527 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
528 /* 8/CMAP : DAC */
529 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
530 /* 9/THC : */
531 if (depth == 8) {
532 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
533 } else {
534 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
535 }
536 /* 11/DHC : */
537 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
538 /* 12/ALT : */
539 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
540 /* 0/DFB8 : 8-bit plane */
541 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
542 /* 1/DFB24 : 24bit plane */
543 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
544 /* 4/RDFB32: Raw framebuffer. Control plane */
545 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
546 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
547 if (depth == 8) {
548 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
549 }
550
551 sysbus_connect_irq(s, 0, irq);
552 }
553
554 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
555 int height, int depth)
556 {
557 DeviceState *dev;
558 SysBusDevice *s;
559
560 dev = qdev_create(NULL, "cgthree");
561 qdev_prop_set_uint32(dev, "vram-size", vram_size);
562 qdev_prop_set_uint16(dev, "width", width);
563 qdev_prop_set_uint16(dev, "height", height);
564 qdev_prop_set_uint16(dev, "depth", depth);
565 qdev_prop_set_uint64(dev, "prom-addr", addr);
566 qdev_init_nofail(dev);
567 s = SYS_BUS_DEVICE(dev);
568
569 /* FCode ROM */
570 sysbus_mmio_map(s, 0, addr);
571 /* DAC */
572 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
573 /* 8-bit plane */
574 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
575
576 sysbus_connect_irq(s, 0, irq);
577 }
578
579 /* NCR89C100/MACIO Internal ID register */
580
581 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
582
583 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
584
585 static void idreg_init(hwaddr addr)
586 {
587 DeviceState *dev;
588 SysBusDevice *s;
589
590 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
591 qdev_init_nofail(dev);
592 s = SYS_BUS_DEVICE(dev);
593
594 sysbus_mmio_map(s, 0, addr);
595 cpu_physical_memory_write_rom(&address_space_memory,
596 addr, idreg_data, sizeof(idreg_data));
597 }
598
599 #define MACIO_ID_REGISTER(obj) \
600 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
601
602 typedef struct IDRegState {
603 SysBusDevice parent_obj;
604
605 MemoryRegion mem;
606 } IDRegState;
607
608 static int idreg_init1(SysBusDevice *dev)
609 {
610 IDRegState *s = MACIO_ID_REGISTER(dev);
611
612 memory_region_init_ram(&s->mem, OBJECT(s),
613 "sun4m.idreg", sizeof(idreg_data), &error_fatal);
614 vmstate_register_ram_global(&s->mem);
615 memory_region_set_readonly(&s->mem, true);
616 sysbus_init_mmio(dev, &s->mem);
617 return 0;
618 }
619
620 static void idreg_class_init(ObjectClass *klass, void *data)
621 {
622 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
623
624 k->init = idreg_init1;
625 }
626
627 static const TypeInfo idreg_info = {
628 .name = TYPE_MACIO_ID_REGISTER,
629 .parent = TYPE_SYS_BUS_DEVICE,
630 .instance_size = sizeof(IDRegState),
631 .class_init = idreg_class_init,
632 };
633
634 #define TYPE_TCX_AFX "tcx_afx"
635 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
636
637 typedef struct AFXState {
638 SysBusDevice parent_obj;
639
640 MemoryRegion mem;
641 } AFXState;
642
643 /* SS-5 TCX AFX register */
644 static void afx_init(hwaddr addr)
645 {
646 DeviceState *dev;
647 SysBusDevice *s;
648
649 dev = qdev_create(NULL, TYPE_TCX_AFX);
650 qdev_init_nofail(dev);
651 s = SYS_BUS_DEVICE(dev);
652
653 sysbus_mmio_map(s, 0, addr);
654 }
655
656 static int afx_init1(SysBusDevice *dev)
657 {
658 AFXState *s = TCX_AFX(dev);
659
660 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_fatal);
661 vmstate_register_ram_global(&s->mem);
662 sysbus_init_mmio(dev, &s->mem);
663 return 0;
664 }
665
666 static void afx_class_init(ObjectClass *klass, void *data)
667 {
668 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
669
670 k->init = afx_init1;
671 }
672
673 static const TypeInfo afx_info = {
674 .name = TYPE_TCX_AFX,
675 .parent = TYPE_SYS_BUS_DEVICE,
676 .instance_size = sizeof(AFXState),
677 .class_init = afx_class_init,
678 };
679
680 #define TYPE_OPENPROM "openprom"
681 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
682
683 typedef struct PROMState {
684 SysBusDevice parent_obj;
685
686 MemoryRegion prom;
687 } PROMState;
688
689 /* Boot PROM (OpenBIOS) */
690 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
691 {
692 hwaddr *base_addr = (hwaddr *)opaque;
693 return addr + *base_addr - PROM_VADDR;
694 }
695
696 static void prom_init(hwaddr addr, const char *bios_name)
697 {
698 DeviceState *dev;
699 SysBusDevice *s;
700 char *filename;
701 int ret;
702
703 dev = qdev_create(NULL, TYPE_OPENPROM);
704 qdev_init_nofail(dev);
705 s = SYS_BUS_DEVICE(dev);
706
707 sysbus_mmio_map(s, 0, addr);
708
709 /* load boot prom */
710 if (bios_name == NULL) {
711 bios_name = PROM_FILENAME;
712 }
713 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
714 if (filename) {
715 ret = load_elf(filename, translate_prom_address, &addr, NULL,
716 NULL, NULL, 1, EM_SPARC, 0, 0);
717 if (ret < 0 || ret > PROM_SIZE_MAX) {
718 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
719 }
720 g_free(filename);
721 } else {
722 ret = -1;
723 }
724 if (ret < 0 || ret > PROM_SIZE_MAX) {
725 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
726 exit(1);
727 }
728 }
729
730 static int prom_init1(SysBusDevice *dev)
731 {
732 PROMState *s = OPENPROM(dev);
733
734 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX,
735 &error_fatal);
736 vmstate_register_ram_global(&s->prom);
737 memory_region_set_readonly(&s->prom, true);
738 sysbus_init_mmio(dev, &s->prom);
739 return 0;
740 }
741
742 static Property prom_properties[] = {
743 {/* end of property list */},
744 };
745
746 static void prom_class_init(ObjectClass *klass, void *data)
747 {
748 DeviceClass *dc = DEVICE_CLASS(klass);
749 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
750
751 k->init = prom_init1;
752 dc->props = prom_properties;
753 }
754
755 static const TypeInfo prom_info = {
756 .name = TYPE_OPENPROM,
757 .parent = TYPE_SYS_BUS_DEVICE,
758 .instance_size = sizeof(PROMState),
759 .class_init = prom_class_init,
760 };
761
762 #define TYPE_SUN4M_MEMORY "memory"
763 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
764
765 typedef struct RamDevice {
766 SysBusDevice parent_obj;
767
768 MemoryRegion ram;
769 uint64_t size;
770 } RamDevice;
771
772 /* System RAM */
773 static int ram_init1(SysBusDevice *dev)
774 {
775 RamDevice *d = SUN4M_RAM(dev);
776
777 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
778 d->size);
779 sysbus_init_mmio(dev, &d->ram);
780 return 0;
781 }
782
783 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
784 uint64_t max_mem)
785 {
786 DeviceState *dev;
787 SysBusDevice *s;
788 RamDevice *d;
789
790 /* allocate RAM */
791 if ((uint64_t)RAM_size > max_mem) {
792 fprintf(stderr,
793 "qemu: Too much memory for this machine: %d, maximum %d\n",
794 (unsigned int)(RAM_size / (1024 * 1024)),
795 (unsigned int)(max_mem / (1024 * 1024)));
796 exit(1);
797 }
798 dev = qdev_create(NULL, "memory");
799 s = SYS_BUS_DEVICE(dev);
800
801 d = SUN4M_RAM(dev);
802 d->size = RAM_size;
803 qdev_init_nofail(dev);
804
805 sysbus_mmio_map(s, 0, addr);
806 }
807
808 static Property ram_properties[] = {
809 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
810 DEFINE_PROP_END_OF_LIST(),
811 };
812
813 static void ram_class_init(ObjectClass *klass, void *data)
814 {
815 DeviceClass *dc = DEVICE_CLASS(klass);
816 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
817
818 k->init = ram_init1;
819 dc->props = ram_properties;
820 }
821
822 static const TypeInfo ram_info = {
823 .name = TYPE_SUN4M_MEMORY,
824 .parent = TYPE_SYS_BUS_DEVICE,
825 .instance_size = sizeof(RamDevice),
826 .class_init = ram_class_init,
827 };
828
829 static void cpu_devinit(const char *cpu_model, unsigned int id,
830 uint64_t prom_addr, qemu_irq **cpu_irqs)
831 {
832 CPUState *cs;
833 SPARCCPU *cpu;
834 CPUSPARCState *env;
835
836 cpu = cpu_sparc_init(cpu_model);
837 if (cpu == NULL) {
838 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
839 exit(1);
840 }
841 env = &cpu->env;
842
843 cpu_sparc_set_id(env, id);
844 if (id == 0) {
845 qemu_register_reset(main_cpu_reset, cpu);
846 } else {
847 qemu_register_reset(secondary_cpu_reset, cpu);
848 cs = CPU(cpu);
849 cs->halted = 1;
850 }
851 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
852 env->prom_addr = prom_addr;
853 }
854
855 static void dummy_fdc_tc(void *opaque, int irq, int level)
856 {
857 }
858
859 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
860 MachineState *machine)
861 {
862 DeviceState *slavio_intctl;
863 const char *cpu_model = machine->cpu_model;
864 unsigned int i;
865 void *iommu, *espdma, *ledma, *nvram;
866 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
867 espdma_irq, ledma_irq;
868 qemu_irq esp_reset, dma_enable;
869 qemu_irq fdc_tc;
870 unsigned long kernel_size;
871 DriveInfo *fd[MAX_FD];
872 FWCfgState *fw_cfg;
873 unsigned int num_vsimms;
874
875 /* init CPUs */
876 if (!cpu_model)
877 cpu_model = hwdef->default_cpu_model;
878
879 for(i = 0; i < smp_cpus; i++) {
880 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
881 }
882
883 for (i = smp_cpus; i < MAX_CPUS; i++)
884 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
885
886
887 /* set up devices */
888 ram_init(0, machine->ram_size, hwdef->max_mem);
889 /* models without ECC don't trap when missing ram is accessed */
890 if (!hwdef->ecc_base) {
891 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
892 }
893
894 prom_init(hwdef->slavio_base, bios_name);
895
896 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
897 hwdef->intctl_base + 0x10000ULL,
898 cpu_irqs);
899
900 for (i = 0; i < 32; i++) {
901 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
902 }
903 for (i = 0; i < MAX_CPUS; i++) {
904 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
905 }
906
907 if (hwdef->idreg_base) {
908 idreg_init(hwdef->idreg_base);
909 }
910
911 if (hwdef->afx_base) {
912 afx_init(hwdef->afx_base);
913 }
914
915 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
916 slavio_irq[30]);
917
918 if (hwdef->iommu_pad_base) {
919 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
920 Software shouldn't use aliased addresses, neither should it crash
921 when does. Using empty_slot instead of aliasing can help with
922 debugging such accesses */
923 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
924 }
925
926 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
927 iommu, &espdma_irq, 0);
928
929 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
930 slavio_irq[16], iommu, &ledma_irq, 1);
931
932 if (graphic_depth != 8 && graphic_depth != 24) {
933 error_report("Unsupported depth: %d", graphic_depth);
934 exit (1);
935 }
936 num_vsimms = 0;
937 if (num_vsimms == 0) {
938 if (vga_interface_type == VGA_CG3) {
939 if (graphic_depth != 8) {
940 error_report("Unsupported depth: %d", graphic_depth);
941 exit(1);
942 }
943
944 if (!(graphic_width == 1024 && graphic_height == 768) &&
945 !(graphic_width == 1152 && graphic_height == 900)) {
946 error_report("Unsupported resolution: %d x %d", graphic_width,
947 graphic_height);
948 exit(1);
949 }
950
951 /* sbus irq 5 */
952 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
953 graphic_width, graphic_height, graphic_depth);
954 } else {
955 /* If no display specified, default to TCX */
956 if (graphic_depth != 8 && graphic_depth != 24) {
957 error_report("Unsupported depth: %d", graphic_depth);
958 exit(1);
959 }
960
961 if (!(graphic_width == 1024 && graphic_height == 768)) {
962 error_report("Unsupported resolution: %d x %d",
963 graphic_width, graphic_height);
964 exit(1);
965 }
966
967 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
968 graphic_width, graphic_height, graphic_depth);
969 }
970 }
971
972 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
973 /* vsimm registers probed by OBP */
974 if (hwdef->vsimm[i].reg_base) {
975 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
976 }
977 }
978
979 if (hwdef->sx_base) {
980 empty_slot_init(hwdef->sx_base, 0x2000);
981 }
982
983 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
984
985 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
986
987 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
988
989 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
990 !machine->enable_graphics, ESCC_CLOCK, 1);
991 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
992 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
993 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
994 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
995
996 if (hwdef->apc_base) {
997 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
998 }
999
1000 if (hwdef->fd_base) {
1001 /* there is zero or one floppy drive */
1002 memset(fd, 0, sizeof(fd));
1003 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1004 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1005 &fdc_tc);
1006 } else {
1007 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1008 }
1009
1010 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1011 slavio_irq[30], fdc_tc);
1012
1013 if (drive_get_max_bus(IF_SCSI) > 0) {
1014 fprintf(stderr, "qemu: too many SCSI bus\n");
1015 exit(1);
1016 }
1017
1018 esp_init(hwdef->esp_base, 2,
1019 espdma_memory_read, espdma_memory_write,
1020 espdma, espdma_irq, &esp_reset, &dma_enable);
1021
1022 qdev_connect_gpio_out(espdma, 0, esp_reset);
1023 qdev_connect_gpio_out(espdma, 1, dma_enable);
1024
1025 if (hwdef->cs_base) {
1026 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1027 slavio_irq[5]);
1028 }
1029
1030 if (hwdef->dbri_base) {
1031 /* ISDN chip with attached CS4215 audio codec */
1032 /* prom space */
1033 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1034 /* reg space */
1035 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1036 }
1037
1038 if (hwdef->bpp_base) {
1039 /* parallel port */
1040 empty_slot_init(hwdef->bpp_base, 0x20);
1041 }
1042
1043 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1044 machine->initrd_filename,
1045 machine->ram_size);
1046
1047 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1048 machine->boot_order, machine->ram_size, kernel_size,
1049 graphic_width, graphic_height, graphic_depth,
1050 hwdef->nvram_machine_id, "Sun4m");
1051
1052 if (hwdef->ecc_base)
1053 ecc_init(hwdef->ecc_base, slavio_irq[28],
1054 hwdef->ecc_version);
1055
1056 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
1057 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1058 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1059 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1060 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1061 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1062 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1063 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1064 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1065 if (machine->kernel_cmdline) {
1066 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1067 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1068 machine->kernel_cmdline);
1069 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1070 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1071 strlen(machine->kernel_cmdline) + 1);
1072 } else {
1073 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1074 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1075 }
1076 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1077 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1078 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1079 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1080 }
1081
1082 enum {
1083 ss5_id = 32,
1084 vger_id,
1085 lx_id,
1086 ss4_id,
1087 scls_id,
1088 sbook_id,
1089 ss10_id = 64,
1090 ss20_id,
1091 ss600mp_id,
1092 };
1093
1094 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1095 /* SS-5 */
1096 {
1097 .iommu_base = 0x10000000,
1098 .iommu_pad_base = 0x10004000,
1099 .iommu_pad_len = 0x0fffb000,
1100 .tcx_base = 0x50000000,
1101 .cs_base = 0x6c000000,
1102 .slavio_base = 0x70000000,
1103 .ms_kb_base = 0x71000000,
1104 .serial_base = 0x71100000,
1105 .nvram_base = 0x71200000,
1106 .fd_base = 0x71400000,
1107 .counter_base = 0x71d00000,
1108 .intctl_base = 0x71e00000,
1109 .idreg_base = 0x78000000,
1110 .dma_base = 0x78400000,
1111 .esp_base = 0x78800000,
1112 .le_base = 0x78c00000,
1113 .apc_base = 0x6a000000,
1114 .afx_base = 0x6e000000,
1115 .aux1_base = 0x71900000,
1116 .aux2_base = 0x71910000,
1117 .nvram_machine_id = 0x80,
1118 .machine_id = ss5_id,
1119 .iommu_version = 0x05000000,
1120 .max_mem = 0x10000000,
1121 .default_cpu_model = "Fujitsu MB86904",
1122 },
1123 /* SS-10 */
1124 {
1125 .iommu_base = 0xfe0000000ULL,
1126 .tcx_base = 0xe20000000ULL,
1127 .slavio_base = 0xff0000000ULL,
1128 .ms_kb_base = 0xff1000000ULL,
1129 .serial_base = 0xff1100000ULL,
1130 .nvram_base = 0xff1200000ULL,
1131 .fd_base = 0xff1700000ULL,
1132 .counter_base = 0xff1300000ULL,
1133 .intctl_base = 0xff1400000ULL,
1134 .idreg_base = 0xef0000000ULL,
1135 .dma_base = 0xef0400000ULL,
1136 .esp_base = 0xef0800000ULL,
1137 .le_base = 0xef0c00000ULL,
1138 .apc_base = 0xefa000000ULL, // XXX should not exist
1139 .aux1_base = 0xff1800000ULL,
1140 .aux2_base = 0xff1a01000ULL,
1141 .ecc_base = 0xf00000000ULL,
1142 .ecc_version = 0x10000000, // version 0, implementation 1
1143 .nvram_machine_id = 0x72,
1144 .machine_id = ss10_id,
1145 .iommu_version = 0x03000000,
1146 .max_mem = 0xf00000000ULL,
1147 .default_cpu_model = "TI SuperSparc II",
1148 },
1149 /* SS-600MP */
1150 {
1151 .iommu_base = 0xfe0000000ULL,
1152 .tcx_base = 0xe20000000ULL,
1153 .slavio_base = 0xff0000000ULL,
1154 .ms_kb_base = 0xff1000000ULL,
1155 .serial_base = 0xff1100000ULL,
1156 .nvram_base = 0xff1200000ULL,
1157 .counter_base = 0xff1300000ULL,
1158 .intctl_base = 0xff1400000ULL,
1159 .dma_base = 0xef0081000ULL,
1160 .esp_base = 0xef0080000ULL,
1161 .le_base = 0xef0060000ULL,
1162 .apc_base = 0xefa000000ULL, // XXX should not exist
1163 .aux1_base = 0xff1800000ULL,
1164 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1165 .ecc_base = 0xf00000000ULL,
1166 .ecc_version = 0x00000000, // version 0, implementation 0
1167 .nvram_machine_id = 0x71,
1168 .machine_id = ss600mp_id,
1169 .iommu_version = 0x01000000,
1170 .max_mem = 0xf00000000ULL,
1171 .default_cpu_model = "TI SuperSparc II",
1172 },
1173 /* SS-20 */
1174 {
1175 .iommu_base = 0xfe0000000ULL,
1176 .tcx_base = 0xe20000000ULL,
1177 .slavio_base = 0xff0000000ULL,
1178 .ms_kb_base = 0xff1000000ULL,
1179 .serial_base = 0xff1100000ULL,
1180 .nvram_base = 0xff1200000ULL,
1181 .fd_base = 0xff1700000ULL,
1182 .counter_base = 0xff1300000ULL,
1183 .intctl_base = 0xff1400000ULL,
1184 .idreg_base = 0xef0000000ULL,
1185 .dma_base = 0xef0400000ULL,
1186 .esp_base = 0xef0800000ULL,
1187 .le_base = 0xef0c00000ULL,
1188 .bpp_base = 0xef4800000ULL,
1189 .apc_base = 0xefa000000ULL, // XXX should not exist
1190 .aux1_base = 0xff1800000ULL,
1191 .aux2_base = 0xff1a01000ULL,
1192 .dbri_base = 0xee0000000ULL,
1193 .sx_base = 0xf80000000ULL,
1194 .vsimm = {
1195 {
1196 .reg_base = 0x9c000000ULL,
1197 .vram_base = 0xfc000000ULL
1198 }, {
1199 .reg_base = 0x90000000ULL,
1200 .vram_base = 0xf0000000ULL
1201 }, {
1202 .reg_base = 0x94000000ULL
1203 }, {
1204 .reg_base = 0x98000000ULL
1205 }
1206 },
1207 .ecc_base = 0xf00000000ULL,
1208 .ecc_version = 0x20000000, // version 0, implementation 2
1209 .nvram_machine_id = 0x72,
1210 .machine_id = ss20_id,
1211 .iommu_version = 0x13000000,
1212 .max_mem = 0xf00000000ULL,
1213 .default_cpu_model = "TI SuperSparc II",
1214 },
1215 /* Voyager */
1216 {
1217 .iommu_base = 0x10000000,
1218 .tcx_base = 0x50000000,
1219 .slavio_base = 0x70000000,
1220 .ms_kb_base = 0x71000000,
1221 .serial_base = 0x71100000,
1222 .nvram_base = 0x71200000,
1223 .fd_base = 0x71400000,
1224 .counter_base = 0x71d00000,
1225 .intctl_base = 0x71e00000,
1226 .idreg_base = 0x78000000,
1227 .dma_base = 0x78400000,
1228 .esp_base = 0x78800000,
1229 .le_base = 0x78c00000,
1230 .apc_base = 0x71300000, // pmc
1231 .aux1_base = 0x71900000,
1232 .aux2_base = 0x71910000,
1233 .nvram_machine_id = 0x80,
1234 .machine_id = vger_id,
1235 .iommu_version = 0x05000000,
1236 .max_mem = 0x10000000,
1237 .default_cpu_model = "Fujitsu MB86904",
1238 },
1239 /* LX */
1240 {
1241 .iommu_base = 0x10000000,
1242 .iommu_pad_base = 0x10004000,
1243 .iommu_pad_len = 0x0fffb000,
1244 .tcx_base = 0x50000000,
1245 .slavio_base = 0x70000000,
1246 .ms_kb_base = 0x71000000,
1247 .serial_base = 0x71100000,
1248 .nvram_base = 0x71200000,
1249 .fd_base = 0x71400000,
1250 .counter_base = 0x71d00000,
1251 .intctl_base = 0x71e00000,
1252 .idreg_base = 0x78000000,
1253 .dma_base = 0x78400000,
1254 .esp_base = 0x78800000,
1255 .le_base = 0x78c00000,
1256 .aux1_base = 0x71900000,
1257 .aux2_base = 0x71910000,
1258 .nvram_machine_id = 0x80,
1259 .machine_id = lx_id,
1260 .iommu_version = 0x04000000,
1261 .max_mem = 0x10000000,
1262 .default_cpu_model = "TI MicroSparc I",
1263 },
1264 /* SS-4 */
1265 {
1266 .iommu_base = 0x10000000,
1267 .tcx_base = 0x50000000,
1268 .cs_base = 0x6c000000,
1269 .slavio_base = 0x70000000,
1270 .ms_kb_base = 0x71000000,
1271 .serial_base = 0x71100000,
1272 .nvram_base = 0x71200000,
1273 .fd_base = 0x71400000,
1274 .counter_base = 0x71d00000,
1275 .intctl_base = 0x71e00000,
1276 .idreg_base = 0x78000000,
1277 .dma_base = 0x78400000,
1278 .esp_base = 0x78800000,
1279 .le_base = 0x78c00000,
1280 .apc_base = 0x6a000000,
1281 .aux1_base = 0x71900000,
1282 .aux2_base = 0x71910000,
1283 .nvram_machine_id = 0x80,
1284 .machine_id = ss4_id,
1285 .iommu_version = 0x05000000,
1286 .max_mem = 0x10000000,
1287 .default_cpu_model = "Fujitsu MB86904",
1288 },
1289 /* SPARCClassic */
1290 {
1291 .iommu_base = 0x10000000,
1292 .tcx_base = 0x50000000,
1293 .slavio_base = 0x70000000,
1294 .ms_kb_base = 0x71000000,
1295 .serial_base = 0x71100000,
1296 .nvram_base = 0x71200000,
1297 .fd_base = 0x71400000,
1298 .counter_base = 0x71d00000,
1299 .intctl_base = 0x71e00000,
1300 .idreg_base = 0x78000000,
1301 .dma_base = 0x78400000,
1302 .esp_base = 0x78800000,
1303 .le_base = 0x78c00000,
1304 .apc_base = 0x6a000000,
1305 .aux1_base = 0x71900000,
1306 .aux2_base = 0x71910000,
1307 .nvram_machine_id = 0x80,
1308 .machine_id = scls_id,
1309 .iommu_version = 0x05000000,
1310 .max_mem = 0x10000000,
1311 .default_cpu_model = "TI MicroSparc I",
1312 },
1313 /* SPARCbook */
1314 {
1315 .iommu_base = 0x10000000,
1316 .tcx_base = 0x50000000, // XXX
1317 .slavio_base = 0x70000000,
1318 .ms_kb_base = 0x71000000,
1319 .serial_base = 0x71100000,
1320 .nvram_base = 0x71200000,
1321 .fd_base = 0x71400000,
1322 .counter_base = 0x71d00000,
1323 .intctl_base = 0x71e00000,
1324 .idreg_base = 0x78000000,
1325 .dma_base = 0x78400000,
1326 .esp_base = 0x78800000,
1327 .le_base = 0x78c00000,
1328 .apc_base = 0x6a000000,
1329 .aux1_base = 0x71900000,
1330 .aux2_base = 0x71910000,
1331 .nvram_machine_id = 0x80,
1332 .machine_id = sbook_id,
1333 .iommu_version = 0x05000000,
1334 .max_mem = 0x10000000,
1335 .default_cpu_model = "TI MicroSparc I",
1336 },
1337 };
1338
1339 /* SPARCstation 5 hardware initialisation */
1340 static void ss5_init(MachineState *machine)
1341 {
1342 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1343 }
1344
1345 /* SPARCstation 10 hardware initialisation */
1346 static void ss10_init(MachineState *machine)
1347 {
1348 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1349 }
1350
1351 /* SPARCserver 600MP hardware initialisation */
1352 static void ss600mp_init(MachineState *machine)
1353 {
1354 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1355 }
1356
1357 /* SPARCstation 20 hardware initialisation */
1358 static void ss20_init(MachineState *machine)
1359 {
1360 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1361 }
1362
1363 /* SPARCstation Voyager hardware initialisation */
1364 static void vger_init(MachineState *machine)
1365 {
1366 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1367 }
1368
1369 /* SPARCstation LX hardware initialisation */
1370 static void ss_lx_init(MachineState *machine)
1371 {
1372 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1373 }
1374
1375 /* SPARCstation 4 hardware initialisation */
1376 static void ss4_init(MachineState *machine)
1377 {
1378 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1379 }
1380
1381 /* SPARCClassic hardware initialisation */
1382 static void scls_init(MachineState *machine)
1383 {
1384 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1385 }
1386
1387 /* SPARCbook hardware initialisation */
1388 static void sbook_init(MachineState *machine)
1389 {
1390 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1391 }
1392
1393 static void ss5_class_init(ObjectClass *oc, void *data)
1394 {
1395 MachineClass *mc = MACHINE_CLASS(oc);
1396
1397 mc->desc = "Sun4m platform, SPARCstation 5";
1398 mc->init = ss5_init;
1399 mc->block_default_type = IF_SCSI;
1400 mc->is_default = 1;
1401 mc->default_boot_order = "c";
1402 }
1403
1404 static const TypeInfo ss5_type = {
1405 .name = MACHINE_TYPE_NAME("SS-5"),
1406 .parent = TYPE_MACHINE,
1407 .class_init = ss5_class_init,
1408 };
1409
1410 static void ss10_class_init(ObjectClass *oc, void *data)
1411 {
1412 MachineClass *mc = MACHINE_CLASS(oc);
1413
1414 mc->desc = "Sun4m platform, SPARCstation 10";
1415 mc->init = ss10_init;
1416 mc->block_default_type = IF_SCSI;
1417 mc->max_cpus = 4;
1418 mc->default_boot_order = "c";
1419 }
1420
1421 static const TypeInfo ss10_type = {
1422 .name = MACHINE_TYPE_NAME("SS-10"),
1423 .parent = TYPE_MACHINE,
1424 .class_init = ss10_class_init,
1425 };
1426
1427 static void ss600mp_class_init(ObjectClass *oc, void *data)
1428 {
1429 MachineClass *mc = MACHINE_CLASS(oc);
1430
1431 mc->desc = "Sun4m platform, SPARCserver 600MP";
1432 mc->init = ss600mp_init;
1433 mc->block_default_type = IF_SCSI;
1434 mc->max_cpus = 4;
1435 mc->default_boot_order = "c";
1436 }
1437
1438 static const TypeInfo ss600mp_type = {
1439 .name = MACHINE_TYPE_NAME("SS-600MP"),
1440 .parent = TYPE_MACHINE,
1441 .class_init = ss600mp_class_init,
1442 };
1443
1444 static void ss20_class_init(ObjectClass *oc, void *data)
1445 {
1446 MachineClass *mc = MACHINE_CLASS(oc);
1447
1448 mc->desc = "Sun4m platform, SPARCstation 20";
1449 mc->init = ss20_init;
1450 mc->block_default_type = IF_SCSI;
1451 mc->max_cpus = 4;
1452 mc->default_boot_order = "c";
1453 }
1454
1455 static const TypeInfo ss20_type = {
1456 .name = MACHINE_TYPE_NAME("SS-20"),
1457 .parent = TYPE_MACHINE,
1458 .class_init = ss20_class_init,
1459 };
1460
1461 static void voyager_class_init(ObjectClass *oc, void *data)
1462 {
1463 MachineClass *mc = MACHINE_CLASS(oc);
1464
1465 mc->desc = "Sun4m platform, SPARCstation Voyager";
1466 mc->init = vger_init;
1467 mc->block_default_type = IF_SCSI;
1468 mc->default_boot_order = "c";
1469 }
1470
1471 static const TypeInfo voyager_type = {
1472 .name = MACHINE_TYPE_NAME("Voyager"),
1473 .parent = TYPE_MACHINE,
1474 .class_init = voyager_class_init,
1475 };
1476
1477 static void ss_lx_class_init(ObjectClass *oc, void *data)
1478 {
1479 MachineClass *mc = MACHINE_CLASS(oc);
1480
1481 mc->desc = "Sun4m platform, SPARCstation LX";
1482 mc->init = ss_lx_init;
1483 mc->block_default_type = IF_SCSI;
1484 mc->default_boot_order = "c";
1485 }
1486
1487 static const TypeInfo ss_lx_type = {
1488 .name = MACHINE_TYPE_NAME("LX"),
1489 .parent = TYPE_MACHINE,
1490 .class_init = ss_lx_class_init,
1491 };
1492
1493 static void ss4_class_init(ObjectClass *oc, void *data)
1494 {
1495 MachineClass *mc = MACHINE_CLASS(oc);
1496
1497 mc->desc = "Sun4m platform, SPARCstation 4";
1498 mc->init = ss4_init;
1499 mc->block_default_type = IF_SCSI;
1500 mc->default_boot_order = "c";
1501 }
1502
1503 static const TypeInfo ss4_type = {
1504 .name = MACHINE_TYPE_NAME("SS-4"),
1505 .parent = TYPE_MACHINE,
1506 .class_init = ss4_class_init,
1507 };
1508
1509 static void scls_class_init(ObjectClass *oc, void *data)
1510 {
1511 MachineClass *mc = MACHINE_CLASS(oc);
1512
1513 mc->desc = "Sun4m platform, SPARCClassic";
1514 mc->init = scls_init;
1515 mc->block_default_type = IF_SCSI;
1516 mc->default_boot_order = "c";
1517 }
1518
1519 static const TypeInfo scls_type = {
1520 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1521 .parent = TYPE_MACHINE,
1522 .class_init = scls_class_init,
1523 };
1524
1525 static void sbook_class_init(ObjectClass *oc, void *data)
1526 {
1527 MachineClass *mc = MACHINE_CLASS(oc);
1528
1529 mc->desc = "Sun4m platform, SPARCbook";
1530 mc->init = sbook_init;
1531 mc->block_default_type = IF_SCSI;
1532 mc->default_boot_order = "c";
1533 }
1534
1535 static const TypeInfo sbook_type = {
1536 .name = MACHINE_TYPE_NAME("SPARCbook"),
1537 .parent = TYPE_MACHINE,
1538 .class_init = sbook_class_init,
1539 };
1540
1541 static void sun4m_register_types(void)
1542 {
1543 type_register_static(&idreg_info);
1544 type_register_static(&afx_info);
1545 type_register_static(&prom_info);
1546 type_register_static(&ram_info);
1547
1548 type_register_static(&ss5_type);
1549 type_register_static(&ss10_type);
1550 type_register_static(&ss600mp_type);
1551 type_register_static(&ss20_type);
1552 type_register_static(&voyager_type);
1553 type_register_static(&ss_lx_type);
1554 type_register_static(&ss4_type);
1555 type_register_static(&scls_type);
1556 type_register_static(&sbook_type);
1557 }
1558
1559 type_init(sun4m_register_types)
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