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cpu: make cpu_generic_init() abort QEMU on error
[mirror_qemu.git] / hw / sparc / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "hw/sparc/sun4m.h"
32 #include "hw/timer/m48t59.h"
33 #include "hw/sparc/sparc32_dma.h"
34 #include "hw/block/fdc.h"
35 #include "sysemu/sysemu.h"
36 #include "net/net.h"
37 #include "hw/boards.h"
38 #include "hw/scsi/esp.h"
39 #include "hw/i386/pc.h"
40 #include "hw/isa/isa.h"
41 #include "hw/nvram/sun_nvram.h"
42 #include "hw/nvram/chrp_nvram.h"
43 #include "hw/nvram/fw_cfg.h"
44 #include "hw/char/escc.h"
45 #include "hw/empty_slot.h"
46 #include "hw/loader.h"
47 #include "elf.h"
48 #include "sysemu/block-backend.h"
49 #include "trace.h"
50 #include "qemu/cutils.h"
51
52 /*
53 * Sun4m architecture was used in the following machines:
54 *
55 * SPARCserver 6xxMP/xx
56 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
57 * SPARCclassic X (4/10)
58 * SPARCstation LX/ZX (4/30)
59 * SPARCstation Voyager
60 * SPARCstation 10/xx, SPARCserver 10/xx
61 * SPARCstation 5, SPARCserver 5
62 * SPARCstation 20/xx, SPARCserver 20
63 * SPARCstation 4
64 *
65 * See for example: http://www.sunhelp.org/faq/sunref1.html
66 */
67
68 #define KERNEL_LOAD_ADDR 0x00004000
69 #define CMDLINE_ADDR 0x007ff000
70 #define INITRD_LOAD_ADDR 0x00800000
71 #define PROM_SIZE_MAX (1024 * 1024)
72 #define PROM_VADDR 0xffd00000
73 #define PROM_FILENAME "openbios-sparc32"
74 #define CFG_ADDR 0xd00000510ULL
75 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
76 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
77 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
78
79 #define MAX_CPUS 16
80 #define MAX_PILS 16
81 #define MAX_VSIMMS 4
82
83 #define ESCC_CLOCK 4915200
84
85 struct sun4m_hwdef {
86 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
87 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
88 hwaddr serial_base, fd_base;
89 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
90 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
91 hwaddr bpp_base, dbri_base, sx_base;
92 struct {
93 hwaddr reg_base, vram_base;
94 } vsimm[MAX_VSIMMS];
95 hwaddr ecc_base;
96 uint64_t max_mem;
97 const char * const default_cpu_model;
98 uint32_t ecc_version;
99 uint32_t iommu_version;
100 uint16_t machine_id;
101 uint8_t nvram_machine_id;
102 };
103
104 void DMA_init(ISABus *bus, int high_page_enable)
105 {
106 }
107
108 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
109 Error **errp)
110 {
111 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
112 }
113
114 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
115 const char *cmdline, const char *boot_devices,
116 ram_addr_t RAM_size, uint32_t kernel_size,
117 int width, int height, int depth,
118 int nvram_machine_id, const char *arch)
119 {
120 unsigned int i;
121 int sysp_end;
122 uint8_t image[0x1ff0];
123 NvramClass *k = NVRAM_GET_CLASS(nvram);
124
125 memset(image, '\0', sizeof(image));
126
127 /* OpenBIOS nvram variables partition */
128 sysp_end = chrp_nvram_create_system_partition(image, 0);
129
130 /* Free space partition */
131 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
132
133 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
134 nvram_machine_id);
135
136 for (i = 0; i < sizeof(image); i++) {
137 (k->write)(nvram, i, image[i]);
138 }
139 }
140
141 void cpu_check_irqs(CPUSPARCState *env)
142 {
143 CPUState *cs;
144
145 /* We should be holding the BQL before we mess with IRQs */
146 g_assert(qemu_mutex_iothread_locked());
147
148 if (env->pil_in && (env->interrupt_index == 0 ||
149 (env->interrupt_index & ~15) == TT_EXTINT)) {
150 unsigned int i;
151
152 for (i = 15; i > 0; i--) {
153 if (env->pil_in & (1 << i)) {
154 int old_interrupt = env->interrupt_index;
155
156 env->interrupt_index = TT_EXTINT | i;
157 if (old_interrupt != env->interrupt_index) {
158 cs = CPU(sparc_env_get_cpu(env));
159 trace_sun4m_cpu_interrupt(i);
160 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
161 }
162 break;
163 }
164 }
165 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
166 cs = CPU(sparc_env_get_cpu(env));
167 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
168 env->interrupt_index = 0;
169 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
170 }
171 }
172
173 static void cpu_kick_irq(SPARCCPU *cpu)
174 {
175 CPUSPARCState *env = &cpu->env;
176 CPUState *cs = CPU(cpu);
177
178 cs->halted = 0;
179 cpu_check_irqs(env);
180 qemu_cpu_kick(cs);
181 }
182
183 static void cpu_set_irq(void *opaque, int irq, int level)
184 {
185 SPARCCPU *cpu = opaque;
186 CPUSPARCState *env = &cpu->env;
187
188 if (level) {
189 trace_sun4m_cpu_set_irq_raise(irq);
190 env->pil_in |= 1 << irq;
191 cpu_kick_irq(cpu);
192 } else {
193 trace_sun4m_cpu_set_irq_lower(irq);
194 env->pil_in &= ~(1 << irq);
195 cpu_check_irqs(env);
196 }
197 }
198
199 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
200 {
201 }
202
203 static void main_cpu_reset(void *opaque)
204 {
205 SPARCCPU *cpu = opaque;
206 CPUState *cs = CPU(cpu);
207
208 cpu_reset(cs);
209 cs->halted = 0;
210 }
211
212 static void secondary_cpu_reset(void *opaque)
213 {
214 SPARCCPU *cpu = opaque;
215 CPUState *cs = CPU(cpu);
216
217 cpu_reset(cs);
218 cs->halted = 1;
219 }
220
221 static void cpu_halt_signal(void *opaque, int irq, int level)
222 {
223 if (level && current_cpu) {
224 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
225 }
226 }
227
228 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
229 {
230 return addr - 0xf0000000ULL;
231 }
232
233 static unsigned long sun4m_load_kernel(const char *kernel_filename,
234 const char *initrd_filename,
235 ram_addr_t RAM_size)
236 {
237 int linux_boot;
238 unsigned int i;
239 long initrd_size, kernel_size;
240 uint8_t *ptr;
241
242 linux_boot = (kernel_filename != NULL);
243
244 kernel_size = 0;
245 if (linux_boot) {
246 int bswap_needed;
247
248 #ifdef BSWAP_NEEDED
249 bswap_needed = 1;
250 #else
251 bswap_needed = 0;
252 #endif
253 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
254 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
255 if (kernel_size < 0)
256 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
257 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
258 TARGET_PAGE_SIZE);
259 if (kernel_size < 0)
260 kernel_size = load_image_targphys(kernel_filename,
261 KERNEL_LOAD_ADDR,
262 RAM_size - KERNEL_LOAD_ADDR);
263 if (kernel_size < 0) {
264 fprintf(stderr, "qemu: could not load kernel '%s'\n",
265 kernel_filename);
266 exit(1);
267 }
268
269 /* load initrd */
270 initrd_size = 0;
271 if (initrd_filename) {
272 initrd_size = load_image_targphys(initrd_filename,
273 INITRD_LOAD_ADDR,
274 RAM_size - INITRD_LOAD_ADDR);
275 if (initrd_size < 0) {
276 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
277 initrd_filename);
278 exit(1);
279 }
280 }
281 if (initrd_size > 0) {
282 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
283 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
284 if (ldl_p(ptr) == 0x48647253) { // HdrS
285 stl_p(ptr + 16, INITRD_LOAD_ADDR);
286 stl_p(ptr + 20, initrd_size);
287 break;
288 }
289 }
290 }
291 }
292 return kernel_size;
293 }
294
295 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
296 {
297 DeviceState *dev;
298 SysBusDevice *s;
299
300 dev = qdev_create(NULL, "iommu");
301 qdev_prop_set_uint32(dev, "version", version);
302 qdev_init_nofail(dev);
303 s = SYS_BUS_DEVICE(dev);
304 sysbus_connect_irq(s, 0, irq);
305 sysbus_mmio_map(s, 0, addr);
306
307 return s;
308 }
309
310 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
311 void *iommu, qemu_irq *dev_irq, int is_ledma)
312 {
313 DeviceState *dev;
314 SysBusDevice *s;
315
316 dev = qdev_create(NULL, "sparc32_dma");
317 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
318 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
319 qdev_init_nofail(dev);
320 s = SYS_BUS_DEVICE(dev);
321 sysbus_connect_irq(s, 0, parent_irq);
322 *dev_irq = qdev_get_gpio_in(dev, 0);
323 sysbus_mmio_map(s, 0, daddr);
324
325 return s;
326 }
327
328 static void lance_init(NICInfo *nd, hwaddr leaddr,
329 void *dma_opaque, qemu_irq irq)
330 {
331 DeviceState *dev;
332 SysBusDevice *s;
333 qemu_irq reset;
334
335 qemu_check_nic_model(&nd_table[0], "lance");
336
337 dev = qdev_create(NULL, "lance");
338 qdev_set_nic_properties(dev, nd);
339 qdev_prop_set_ptr(dev, "dma", dma_opaque);
340 qdev_init_nofail(dev);
341 s = SYS_BUS_DEVICE(dev);
342 sysbus_mmio_map(s, 0, leaddr);
343 sysbus_connect_irq(s, 0, irq);
344 reset = qdev_get_gpio_in(dev, 0);
345 qdev_connect_gpio_out(dma_opaque, 0, reset);
346 }
347
348 static DeviceState *slavio_intctl_init(hwaddr addr,
349 hwaddr addrg,
350 qemu_irq **parent_irq)
351 {
352 DeviceState *dev;
353 SysBusDevice *s;
354 unsigned int i, j;
355
356 dev = qdev_create(NULL, "slavio_intctl");
357 qdev_init_nofail(dev);
358
359 s = SYS_BUS_DEVICE(dev);
360
361 for (i = 0; i < MAX_CPUS; i++) {
362 for (j = 0; j < MAX_PILS; j++) {
363 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
364 }
365 }
366 sysbus_mmio_map(s, 0, addrg);
367 for (i = 0; i < MAX_CPUS; i++) {
368 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
369 }
370
371 return dev;
372 }
373
374 #define SYS_TIMER_OFFSET 0x10000ULL
375 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
376
377 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
378 qemu_irq *cpu_irqs, unsigned int num_cpus)
379 {
380 DeviceState *dev;
381 SysBusDevice *s;
382 unsigned int i;
383
384 dev = qdev_create(NULL, "slavio_timer");
385 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
386 qdev_init_nofail(dev);
387 s = SYS_BUS_DEVICE(dev);
388 sysbus_connect_irq(s, 0, master_irq);
389 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
390
391 for (i = 0; i < MAX_CPUS; i++) {
392 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
393 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
394 }
395 }
396
397 static qemu_irq slavio_system_powerdown;
398
399 static void slavio_powerdown_req(Notifier *n, void *opaque)
400 {
401 qemu_irq_raise(slavio_system_powerdown);
402 }
403
404 static Notifier slavio_system_powerdown_notifier = {
405 .notify = slavio_powerdown_req
406 };
407
408 #define MISC_LEDS 0x01600000
409 #define MISC_CFG 0x01800000
410 #define MISC_DIAG 0x01a00000
411 #define MISC_MDM 0x01b00000
412 #define MISC_SYS 0x01f00000
413
414 static void slavio_misc_init(hwaddr base,
415 hwaddr aux1_base,
416 hwaddr aux2_base, qemu_irq irq,
417 qemu_irq fdc_tc)
418 {
419 DeviceState *dev;
420 SysBusDevice *s;
421
422 dev = qdev_create(NULL, "slavio_misc");
423 qdev_init_nofail(dev);
424 s = SYS_BUS_DEVICE(dev);
425 if (base) {
426 /* 8 bit registers */
427 /* Slavio control */
428 sysbus_mmio_map(s, 0, base + MISC_CFG);
429 /* Diagnostics */
430 sysbus_mmio_map(s, 1, base + MISC_DIAG);
431 /* Modem control */
432 sysbus_mmio_map(s, 2, base + MISC_MDM);
433 /* 16 bit registers */
434 /* ss600mp diag LEDs */
435 sysbus_mmio_map(s, 3, base + MISC_LEDS);
436 /* 32 bit registers */
437 /* System control */
438 sysbus_mmio_map(s, 4, base + MISC_SYS);
439 }
440 if (aux1_base) {
441 /* AUX 1 (Misc System Functions) */
442 sysbus_mmio_map(s, 5, aux1_base);
443 }
444 if (aux2_base) {
445 /* AUX 2 (Software Powerdown Control) */
446 sysbus_mmio_map(s, 6, aux2_base);
447 }
448 sysbus_connect_irq(s, 0, irq);
449 sysbus_connect_irq(s, 1, fdc_tc);
450 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
451 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
452 }
453
454 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
455 {
456 DeviceState *dev;
457 SysBusDevice *s;
458
459 dev = qdev_create(NULL, "eccmemctl");
460 qdev_prop_set_uint32(dev, "version", version);
461 qdev_init_nofail(dev);
462 s = SYS_BUS_DEVICE(dev);
463 sysbus_connect_irq(s, 0, irq);
464 sysbus_mmio_map(s, 0, base);
465 if (version == 0) { // SS-600MP only
466 sysbus_mmio_map(s, 1, base + 0x1000);
467 }
468 }
469
470 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
471 {
472 DeviceState *dev;
473 SysBusDevice *s;
474
475 dev = qdev_create(NULL, "apc");
476 qdev_init_nofail(dev);
477 s = SYS_BUS_DEVICE(dev);
478 /* Power management (APC) XXX: not a Slavio device */
479 sysbus_mmio_map(s, 0, power_base);
480 sysbus_connect_irq(s, 0, cpu_halt);
481 }
482
483 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
484 int height, int depth)
485 {
486 DeviceState *dev;
487 SysBusDevice *s;
488
489 dev = qdev_create(NULL, "SUNW,tcx");
490 qdev_prop_set_uint32(dev, "vram_size", vram_size);
491 qdev_prop_set_uint16(dev, "width", width);
492 qdev_prop_set_uint16(dev, "height", height);
493 qdev_prop_set_uint16(dev, "depth", depth);
494 qdev_init_nofail(dev);
495 s = SYS_BUS_DEVICE(dev);
496
497 /* 10/ROM : FCode ROM */
498 sysbus_mmio_map(s, 0, addr);
499 /* 2/STIP : Stipple */
500 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
501 /* 3/BLIT : Blitter */
502 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
503 /* 5/RSTIP : Raw Stipple */
504 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
505 /* 6/RBLIT : Raw Blitter */
506 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
507 /* 7/TEC : Transform Engine */
508 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
509 /* 8/CMAP : DAC */
510 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
511 /* 9/THC : */
512 if (depth == 8) {
513 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
514 } else {
515 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
516 }
517 /* 11/DHC : */
518 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
519 /* 12/ALT : */
520 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
521 /* 0/DFB8 : 8-bit plane */
522 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
523 /* 1/DFB24 : 24bit plane */
524 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
525 /* 4/RDFB32: Raw framebuffer. Control plane */
526 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
527 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
528 if (depth == 8) {
529 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
530 }
531
532 sysbus_connect_irq(s, 0, irq);
533 }
534
535 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
536 int height, int depth)
537 {
538 DeviceState *dev;
539 SysBusDevice *s;
540
541 dev = qdev_create(NULL, "cgthree");
542 qdev_prop_set_uint32(dev, "vram-size", vram_size);
543 qdev_prop_set_uint16(dev, "width", width);
544 qdev_prop_set_uint16(dev, "height", height);
545 qdev_prop_set_uint16(dev, "depth", depth);
546 qdev_init_nofail(dev);
547 s = SYS_BUS_DEVICE(dev);
548
549 /* FCode ROM */
550 sysbus_mmio_map(s, 0, addr);
551 /* DAC */
552 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
553 /* 8-bit plane */
554 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
555
556 sysbus_connect_irq(s, 0, irq);
557 }
558
559 /* NCR89C100/MACIO Internal ID register */
560
561 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
562
563 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
564
565 static void idreg_init(hwaddr addr)
566 {
567 DeviceState *dev;
568 SysBusDevice *s;
569
570 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
571 qdev_init_nofail(dev);
572 s = SYS_BUS_DEVICE(dev);
573
574 sysbus_mmio_map(s, 0, addr);
575 cpu_physical_memory_write_rom(&address_space_memory,
576 addr, idreg_data, sizeof(idreg_data));
577 }
578
579 #define MACIO_ID_REGISTER(obj) \
580 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
581
582 typedef struct IDRegState {
583 SysBusDevice parent_obj;
584
585 MemoryRegion mem;
586 } IDRegState;
587
588 static void idreg_init1(Object *obj)
589 {
590 IDRegState *s = MACIO_ID_REGISTER(obj);
591 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
592
593 memory_region_init_ram_nomigrate(&s->mem, obj,
594 "sun4m.idreg", sizeof(idreg_data), &error_fatal);
595 vmstate_register_ram_global(&s->mem);
596 memory_region_set_readonly(&s->mem, true);
597 sysbus_init_mmio(dev, &s->mem);
598 }
599
600 static const TypeInfo idreg_info = {
601 .name = TYPE_MACIO_ID_REGISTER,
602 .parent = TYPE_SYS_BUS_DEVICE,
603 .instance_size = sizeof(IDRegState),
604 .instance_init = idreg_init1,
605 };
606
607 #define TYPE_TCX_AFX "tcx_afx"
608 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
609
610 typedef struct AFXState {
611 SysBusDevice parent_obj;
612
613 MemoryRegion mem;
614 } AFXState;
615
616 /* SS-5 TCX AFX register */
617 static void afx_init(hwaddr addr)
618 {
619 DeviceState *dev;
620 SysBusDevice *s;
621
622 dev = qdev_create(NULL, TYPE_TCX_AFX);
623 qdev_init_nofail(dev);
624 s = SYS_BUS_DEVICE(dev);
625
626 sysbus_mmio_map(s, 0, addr);
627 }
628
629 static void afx_init1(Object *obj)
630 {
631 AFXState *s = TCX_AFX(obj);
632 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
633
634 memory_region_init_ram_nomigrate(&s->mem, obj, "sun4m.afx", 4, &error_fatal);
635 vmstate_register_ram_global(&s->mem);
636 sysbus_init_mmio(dev, &s->mem);
637 }
638
639 static const TypeInfo afx_info = {
640 .name = TYPE_TCX_AFX,
641 .parent = TYPE_SYS_BUS_DEVICE,
642 .instance_size = sizeof(AFXState),
643 .instance_init = afx_init1,
644 };
645
646 #define TYPE_OPENPROM "openprom"
647 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
648
649 typedef struct PROMState {
650 SysBusDevice parent_obj;
651
652 MemoryRegion prom;
653 } PROMState;
654
655 /* Boot PROM (OpenBIOS) */
656 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
657 {
658 hwaddr *base_addr = (hwaddr *)opaque;
659 return addr + *base_addr - PROM_VADDR;
660 }
661
662 static void prom_init(hwaddr addr, const char *bios_name)
663 {
664 DeviceState *dev;
665 SysBusDevice *s;
666 char *filename;
667 int ret;
668
669 dev = qdev_create(NULL, TYPE_OPENPROM);
670 qdev_init_nofail(dev);
671 s = SYS_BUS_DEVICE(dev);
672
673 sysbus_mmio_map(s, 0, addr);
674
675 /* load boot prom */
676 if (bios_name == NULL) {
677 bios_name = PROM_FILENAME;
678 }
679 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
680 if (filename) {
681 ret = load_elf(filename, translate_prom_address, &addr, NULL,
682 NULL, NULL, 1, EM_SPARC, 0, 0);
683 if (ret < 0 || ret > PROM_SIZE_MAX) {
684 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
685 }
686 g_free(filename);
687 } else {
688 ret = -1;
689 }
690 if (ret < 0 || ret > PROM_SIZE_MAX) {
691 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
692 exit(1);
693 }
694 }
695
696 static void prom_init1(Object *obj)
697 {
698 PROMState *s = OPENPROM(obj);
699 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
700
701 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4m.prom", PROM_SIZE_MAX,
702 &error_fatal);
703 vmstate_register_ram_global(&s->prom);
704 memory_region_set_readonly(&s->prom, true);
705 sysbus_init_mmio(dev, &s->prom);
706 }
707
708 static Property prom_properties[] = {
709 {/* end of property list */},
710 };
711
712 static void prom_class_init(ObjectClass *klass, void *data)
713 {
714 DeviceClass *dc = DEVICE_CLASS(klass);
715
716 dc->props = prom_properties;
717 }
718
719 static const TypeInfo prom_info = {
720 .name = TYPE_OPENPROM,
721 .parent = TYPE_SYS_BUS_DEVICE,
722 .instance_size = sizeof(PROMState),
723 .class_init = prom_class_init,
724 .instance_init = prom_init1,
725 };
726
727 #define TYPE_SUN4M_MEMORY "memory"
728 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
729
730 typedef struct RamDevice {
731 SysBusDevice parent_obj;
732
733 MemoryRegion ram;
734 uint64_t size;
735 } RamDevice;
736
737 /* System RAM */
738 static void ram_realize(DeviceState *dev, Error **errp)
739 {
740 RamDevice *d = SUN4M_RAM(dev);
741 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
742
743 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
744 d->size);
745 sysbus_init_mmio(sbd, &d->ram);
746 }
747
748 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
749 uint64_t max_mem)
750 {
751 DeviceState *dev;
752 SysBusDevice *s;
753 RamDevice *d;
754
755 /* allocate RAM */
756 if ((uint64_t)RAM_size > max_mem) {
757 fprintf(stderr,
758 "qemu: Too much memory for this machine: %d, maximum %d\n",
759 (unsigned int)(RAM_size / (1024 * 1024)),
760 (unsigned int)(max_mem / (1024 * 1024)));
761 exit(1);
762 }
763 dev = qdev_create(NULL, "memory");
764 s = SYS_BUS_DEVICE(dev);
765
766 d = SUN4M_RAM(dev);
767 d->size = RAM_size;
768 qdev_init_nofail(dev);
769
770 sysbus_mmio_map(s, 0, addr);
771 }
772
773 static Property ram_properties[] = {
774 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
775 DEFINE_PROP_END_OF_LIST(),
776 };
777
778 static void ram_class_init(ObjectClass *klass, void *data)
779 {
780 DeviceClass *dc = DEVICE_CLASS(klass);
781
782 dc->realize = ram_realize;
783 dc->props = ram_properties;
784 }
785
786 static const TypeInfo ram_info = {
787 .name = TYPE_SUN4M_MEMORY,
788 .parent = TYPE_SYS_BUS_DEVICE,
789 .instance_size = sizeof(RamDevice),
790 .class_init = ram_class_init,
791 };
792
793 static void cpu_devinit(const char *cpu_model, unsigned int id,
794 uint64_t prom_addr, qemu_irq **cpu_irqs)
795 {
796 CPUState *cs;
797 SPARCCPU *cpu;
798 CPUSPARCState *env;
799
800 cpu = SPARC_CPU(cpu_generic_init(TYPE_SPARC_CPU, cpu_model));
801 env = &cpu->env;
802
803 cpu_sparc_set_id(env, id);
804 if (id == 0) {
805 qemu_register_reset(main_cpu_reset, cpu);
806 } else {
807 qemu_register_reset(secondary_cpu_reset, cpu);
808 cs = CPU(cpu);
809 cs->halted = 1;
810 }
811 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
812 env->prom_addr = prom_addr;
813 }
814
815 static void dummy_fdc_tc(void *opaque, int irq, int level)
816 {
817 }
818
819 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
820 MachineState *machine)
821 {
822 DeviceState *slavio_intctl;
823 const char *cpu_model = machine->cpu_model;
824 unsigned int i;
825 void *iommu, *espdma, *ledma, *nvram;
826 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
827 espdma_irq, ledma_irq;
828 qemu_irq esp_reset, dma_enable;
829 qemu_irq fdc_tc;
830 unsigned long kernel_size;
831 DriveInfo *fd[MAX_FD];
832 FWCfgState *fw_cfg;
833 unsigned int num_vsimms;
834
835 /* init CPUs */
836 if (!cpu_model)
837 cpu_model = hwdef->default_cpu_model;
838
839 for(i = 0; i < smp_cpus; i++) {
840 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
841 }
842
843 for (i = smp_cpus; i < MAX_CPUS; i++)
844 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
845
846
847 /* set up devices */
848 ram_init(0, machine->ram_size, hwdef->max_mem);
849 /* models without ECC don't trap when missing ram is accessed */
850 if (!hwdef->ecc_base) {
851 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
852 }
853
854 prom_init(hwdef->slavio_base, bios_name);
855
856 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
857 hwdef->intctl_base + 0x10000ULL,
858 cpu_irqs);
859
860 for (i = 0; i < 32; i++) {
861 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
862 }
863 for (i = 0; i < MAX_CPUS; i++) {
864 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
865 }
866
867 if (hwdef->idreg_base) {
868 idreg_init(hwdef->idreg_base);
869 }
870
871 if (hwdef->afx_base) {
872 afx_init(hwdef->afx_base);
873 }
874
875 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
876 slavio_irq[30]);
877
878 if (hwdef->iommu_pad_base) {
879 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
880 Software shouldn't use aliased addresses, neither should it crash
881 when does. Using empty_slot instead of aliasing can help with
882 debugging such accesses */
883 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
884 }
885
886 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
887 iommu, &espdma_irq, 0);
888
889 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
890 slavio_irq[16], iommu, &ledma_irq, 1);
891
892 if (graphic_depth != 8 && graphic_depth != 24) {
893 error_report("Unsupported depth: %d", graphic_depth);
894 exit (1);
895 }
896 num_vsimms = 0;
897 if (num_vsimms == 0) {
898 if (vga_interface_type == VGA_CG3) {
899 if (graphic_depth != 8) {
900 error_report("Unsupported depth: %d", graphic_depth);
901 exit(1);
902 }
903
904 if (!(graphic_width == 1024 && graphic_height == 768) &&
905 !(graphic_width == 1152 && graphic_height == 900)) {
906 error_report("Unsupported resolution: %d x %d", graphic_width,
907 graphic_height);
908 exit(1);
909 }
910
911 /* sbus irq 5 */
912 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
913 graphic_width, graphic_height, graphic_depth);
914 } else {
915 /* If no display specified, default to TCX */
916 if (graphic_depth != 8 && graphic_depth != 24) {
917 error_report("Unsupported depth: %d", graphic_depth);
918 exit(1);
919 }
920
921 if (!(graphic_width == 1024 && graphic_height == 768)) {
922 error_report("Unsupported resolution: %d x %d",
923 graphic_width, graphic_height);
924 exit(1);
925 }
926
927 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
928 graphic_width, graphic_height, graphic_depth);
929 }
930 }
931
932 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
933 /* vsimm registers probed by OBP */
934 if (hwdef->vsimm[i].reg_base) {
935 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
936 }
937 }
938
939 if (hwdef->sx_base) {
940 empty_slot_init(hwdef->sx_base, 0x2000);
941 }
942
943 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
944
945 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
946
947 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
948
949 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
950 !machine->enable_graphics, ESCC_CLOCK, 1);
951 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
952 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
953 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
954 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
955
956 if (hwdef->apc_base) {
957 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
958 }
959
960 if (hwdef->fd_base) {
961 /* there is zero or one floppy drive */
962 memset(fd, 0, sizeof(fd));
963 fd[0] = drive_get(IF_FLOPPY, 0, 0);
964 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
965 &fdc_tc);
966 } else {
967 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
968 }
969
970 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
971 slavio_irq[30], fdc_tc);
972
973 esp_init(hwdef->esp_base, 2,
974 espdma_memory_read, espdma_memory_write,
975 espdma, espdma_irq, &esp_reset, &dma_enable);
976
977 qdev_connect_gpio_out(espdma, 0, esp_reset);
978 qdev_connect_gpio_out(espdma, 1, dma_enable);
979
980 if (hwdef->cs_base) {
981 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
982 slavio_irq[5]);
983 }
984
985 if (hwdef->dbri_base) {
986 /* ISDN chip with attached CS4215 audio codec */
987 /* prom space */
988 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
989 /* reg space */
990 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
991 }
992
993 if (hwdef->bpp_base) {
994 /* parallel port */
995 empty_slot_init(hwdef->bpp_base, 0x20);
996 }
997
998 kernel_size = sun4m_load_kernel(machine->kernel_filename,
999 machine->initrd_filename,
1000 machine->ram_size);
1001
1002 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1003 machine->boot_order, machine->ram_size, kernel_size,
1004 graphic_width, graphic_height, graphic_depth,
1005 hwdef->nvram_machine_id, "Sun4m");
1006
1007 if (hwdef->ecc_base)
1008 ecc_init(hwdef->ecc_base, slavio_irq[28],
1009 hwdef->ecc_version);
1010
1011 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
1012 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1013 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1014 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1015 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1016 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1017 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1018 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1019 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1020 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1021 if (machine->kernel_cmdline) {
1022 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1023 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1024 machine->kernel_cmdline);
1025 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1026 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1027 strlen(machine->kernel_cmdline) + 1);
1028 } else {
1029 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1030 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1031 }
1032 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1033 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1034 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1035 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1036 }
1037
1038 enum {
1039 ss5_id = 32,
1040 vger_id,
1041 lx_id,
1042 ss4_id,
1043 scls_id,
1044 sbook_id,
1045 ss10_id = 64,
1046 ss20_id,
1047 ss600mp_id,
1048 };
1049
1050 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1051 /* SS-5 */
1052 {
1053 .iommu_base = 0x10000000,
1054 .iommu_pad_base = 0x10004000,
1055 .iommu_pad_len = 0x0fffb000,
1056 .tcx_base = 0x50000000,
1057 .cs_base = 0x6c000000,
1058 .slavio_base = 0x70000000,
1059 .ms_kb_base = 0x71000000,
1060 .serial_base = 0x71100000,
1061 .nvram_base = 0x71200000,
1062 .fd_base = 0x71400000,
1063 .counter_base = 0x71d00000,
1064 .intctl_base = 0x71e00000,
1065 .idreg_base = 0x78000000,
1066 .dma_base = 0x78400000,
1067 .esp_base = 0x78800000,
1068 .le_base = 0x78c00000,
1069 .apc_base = 0x6a000000,
1070 .afx_base = 0x6e000000,
1071 .aux1_base = 0x71900000,
1072 .aux2_base = 0x71910000,
1073 .nvram_machine_id = 0x80,
1074 .machine_id = ss5_id,
1075 .iommu_version = 0x05000000,
1076 .max_mem = 0x10000000,
1077 .default_cpu_model = "Fujitsu MB86904",
1078 },
1079 /* SS-10 */
1080 {
1081 .iommu_base = 0xfe0000000ULL,
1082 .tcx_base = 0xe20000000ULL,
1083 .slavio_base = 0xff0000000ULL,
1084 .ms_kb_base = 0xff1000000ULL,
1085 .serial_base = 0xff1100000ULL,
1086 .nvram_base = 0xff1200000ULL,
1087 .fd_base = 0xff1700000ULL,
1088 .counter_base = 0xff1300000ULL,
1089 .intctl_base = 0xff1400000ULL,
1090 .idreg_base = 0xef0000000ULL,
1091 .dma_base = 0xef0400000ULL,
1092 .esp_base = 0xef0800000ULL,
1093 .le_base = 0xef0c00000ULL,
1094 .apc_base = 0xefa000000ULL, // XXX should not exist
1095 .aux1_base = 0xff1800000ULL,
1096 .aux2_base = 0xff1a01000ULL,
1097 .ecc_base = 0xf00000000ULL,
1098 .ecc_version = 0x10000000, // version 0, implementation 1
1099 .nvram_machine_id = 0x72,
1100 .machine_id = ss10_id,
1101 .iommu_version = 0x03000000,
1102 .max_mem = 0xf00000000ULL,
1103 .default_cpu_model = "TI SuperSparc II",
1104 },
1105 /* SS-600MP */
1106 {
1107 .iommu_base = 0xfe0000000ULL,
1108 .tcx_base = 0xe20000000ULL,
1109 .slavio_base = 0xff0000000ULL,
1110 .ms_kb_base = 0xff1000000ULL,
1111 .serial_base = 0xff1100000ULL,
1112 .nvram_base = 0xff1200000ULL,
1113 .counter_base = 0xff1300000ULL,
1114 .intctl_base = 0xff1400000ULL,
1115 .dma_base = 0xef0081000ULL,
1116 .esp_base = 0xef0080000ULL,
1117 .le_base = 0xef0060000ULL,
1118 .apc_base = 0xefa000000ULL, // XXX should not exist
1119 .aux1_base = 0xff1800000ULL,
1120 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1121 .ecc_base = 0xf00000000ULL,
1122 .ecc_version = 0x00000000, // version 0, implementation 0
1123 .nvram_machine_id = 0x71,
1124 .machine_id = ss600mp_id,
1125 .iommu_version = 0x01000000,
1126 .max_mem = 0xf00000000ULL,
1127 .default_cpu_model = "TI SuperSparc II",
1128 },
1129 /* SS-20 */
1130 {
1131 .iommu_base = 0xfe0000000ULL,
1132 .tcx_base = 0xe20000000ULL,
1133 .slavio_base = 0xff0000000ULL,
1134 .ms_kb_base = 0xff1000000ULL,
1135 .serial_base = 0xff1100000ULL,
1136 .nvram_base = 0xff1200000ULL,
1137 .fd_base = 0xff1700000ULL,
1138 .counter_base = 0xff1300000ULL,
1139 .intctl_base = 0xff1400000ULL,
1140 .idreg_base = 0xef0000000ULL,
1141 .dma_base = 0xef0400000ULL,
1142 .esp_base = 0xef0800000ULL,
1143 .le_base = 0xef0c00000ULL,
1144 .bpp_base = 0xef4800000ULL,
1145 .apc_base = 0xefa000000ULL, // XXX should not exist
1146 .aux1_base = 0xff1800000ULL,
1147 .aux2_base = 0xff1a01000ULL,
1148 .dbri_base = 0xee0000000ULL,
1149 .sx_base = 0xf80000000ULL,
1150 .vsimm = {
1151 {
1152 .reg_base = 0x9c000000ULL,
1153 .vram_base = 0xfc000000ULL
1154 }, {
1155 .reg_base = 0x90000000ULL,
1156 .vram_base = 0xf0000000ULL
1157 }, {
1158 .reg_base = 0x94000000ULL
1159 }, {
1160 .reg_base = 0x98000000ULL
1161 }
1162 },
1163 .ecc_base = 0xf00000000ULL,
1164 .ecc_version = 0x20000000, // version 0, implementation 2
1165 .nvram_machine_id = 0x72,
1166 .machine_id = ss20_id,
1167 .iommu_version = 0x13000000,
1168 .max_mem = 0xf00000000ULL,
1169 .default_cpu_model = "TI SuperSparc II",
1170 },
1171 /* Voyager */
1172 {
1173 .iommu_base = 0x10000000,
1174 .tcx_base = 0x50000000,
1175 .slavio_base = 0x70000000,
1176 .ms_kb_base = 0x71000000,
1177 .serial_base = 0x71100000,
1178 .nvram_base = 0x71200000,
1179 .fd_base = 0x71400000,
1180 .counter_base = 0x71d00000,
1181 .intctl_base = 0x71e00000,
1182 .idreg_base = 0x78000000,
1183 .dma_base = 0x78400000,
1184 .esp_base = 0x78800000,
1185 .le_base = 0x78c00000,
1186 .apc_base = 0x71300000, // pmc
1187 .aux1_base = 0x71900000,
1188 .aux2_base = 0x71910000,
1189 .nvram_machine_id = 0x80,
1190 .machine_id = vger_id,
1191 .iommu_version = 0x05000000,
1192 .max_mem = 0x10000000,
1193 .default_cpu_model = "Fujitsu MB86904",
1194 },
1195 /* LX */
1196 {
1197 .iommu_base = 0x10000000,
1198 .iommu_pad_base = 0x10004000,
1199 .iommu_pad_len = 0x0fffb000,
1200 .tcx_base = 0x50000000,
1201 .slavio_base = 0x70000000,
1202 .ms_kb_base = 0x71000000,
1203 .serial_base = 0x71100000,
1204 .nvram_base = 0x71200000,
1205 .fd_base = 0x71400000,
1206 .counter_base = 0x71d00000,
1207 .intctl_base = 0x71e00000,
1208 .idreg_base = 0x78000000,
1209 .dma_base = 0x78400000,
1210 .esp_base = 0x78800000,
1211 .le_base = 0x78c00000,
1212 .aux1_base = 0x71900000,
1213 .aux2_base = 0x71910000,
1214 .nvram_machine_id = 0x80,
1215 .machine_id = lx_id,
1216 .iommu_version = 0x04000000,
1217 .max_mem = 0x10000000,
1218 .default_cpu_model = "TI MicroSparc I",
1219 },
1220 /* SS-4 */
1221 {
1222 .iommu_base = 0x10000000,
1223 .tcx_base = 0x50000000,
1224 .cs_base = 0x6c000000,
1225 .slavio_base = 0x70000000,
1226 .ms_kb_base = 0x71000000,
1227 .serial_base = 0x71100000,
1228 .nvram_base = 0x71200000,
1229 .fd_base = 0x71400000,
1230 .counter_base = 0x71d00000,
1231 .intctl_base = 0x71e00000,
1232 .idreg_base = 0x78000000,
1233 .dma_base = 0x78400000,
1234 .esp_base = 0x78800000,
1235 .le_base = 0x78c00000,
1236 .apc_base = 0x6a000000,
1237 .aux1_base = 0x71900000,
1238 .aux2_base = 0x71910000,
1239 .nvram_machine_id = 0x80,
1240 .machine_id = ss4_id,
1241 .iommu_version = 0x05000000,
1242 .max_mem = 0x10000000,
1243 .default_cpu_model = "Fujitsu MB86904",
1244 },
1245 /* SPARCClassic */
1246 {
1247 .iommu_base = 0x10000000,
1248 .tcx_base = 0x50000000,
1249 .slavio_base = 0x70000000,
1250 .ms_kb_base = 0x71000000,
1251 .serial_base = 0x71100000,
1252 .nvram_base = 0x71200000,
1253 .fd_base = 0x71400000,
1254 .counter_base = 0x71d00000,
1255 .intctl_base = 0x71e00000,
1256 .idreg_base = 0x78000000,
1257 .dma_base = 0x78400000,
1258 .esp_base = 0x78800000,
1259 .le_base = 0x78c00000,
1260 .apc_base = 0x6a000000,
1261 .aux1_base = 0x71900000,
1262 .aux2_base = 0x71910000,
1263 .nvram_machine_id = 0x80,
1264 .machine_id = scls_id,
1265 .iommu_version = 0x05000000,
1266 .max_mem = 0x10000000,
1267 .default_cpu_model = "TI MicroSparc I",
1268 },
1269 /* SPARCbook */
1270 {
1271 .iommu_base = 0x10000000,
1272 .tcx_base = 0x50000000, // XXX
1273 .slavio_base = 0x70000000,
1274 .ms_kb_base = 0x71000000,
1275 .serial_base = 0x71100000,
1276 .nvram_base = 0x71200000,
1277 .fd_base = 0x71400000,
1278 .counter_base = 0x71d00000,
1279 .intctl_base = 0x71e00000,
1280 .idreg_base = 0x78000000,
1281 .dma_base = 0x78400000,
1282 .esp_base = 0x78800000,
1283 .le_base = 0x78c00000,
1284 .apc_base = 0x6a000000,
1285 .aux1_base = 0x71900000,
1286 .aux2_base = 0x71910000,
1287 .nvram_machine_id = 0x80,
1288 .machine_id = sbook_id,
1289 .iommu_version = 0x05000000,
1290 .max_mem = 0x10000000,
1291 .default_cpu_model = "TI MicroSparc I",
1292 },
1293 };
1294
1295 /* SPARCstation 5 hardware initialisation */
1296 static void ss5_init(MachineState *machine)
1297 {
1298 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1299 }
1300
1301 /* SPARCstation 10 hardware initialisation */
1302 static void ss10_init(MachineState *machine)
1303 {
1304 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1305 }
1306
1307 /* SPARCserver 600MP hardware initialisation */
1308 static void ss600mp_init(MachineState *machine)
1309 {
1310 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1311 }
1312
1313 /* SPARCstation 20 hardware initialisation */
1314 static void ss20_init(MachineState *machine)
1315 {
1316 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1317 }
1318
1319 /* SPARCstation Voyager hardware initialisation */
1320 static void vger_init(MachineState *machine)
1321 {
1322 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1323 }
1324
1325 /* SPARCstation LX hardware initialisation */
1326 static void ss_lx_init(MachineState *machine)
1327 {
1328 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1329 }
1330
1331 /* SPARCstation 4 hardware initialisation */
1332 static void ss4_init(MachineState *machine)
1333 {
1334 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1335 }
1336
1337 /* SPARCClassic hardware initialisation */
1338 static void scls_init(MachineState *machine)
1339 {
1340 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1341 }
1342
1343 /* SPARCbook hardware initialisation */
1344 static void sbook_init(MachineState *machine)
1345 {
1346 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1347 }
1348
1349 static void ss5_class_init(ObjectClass *oc, void *data)
1350 {
1351 MachineClass *mc = MACHINE_CLASS(oc);
1352
1353 mc->desc = "Sun4m platform, SPARCstation 5";
1354 mc->init = ss5_init;
1355 mc->block_default_type = IF_SCSI;
1356 mc->is_default = 1;
1357 mc->default_boot_order = "c";
1358 }
1359
1360 static const TypeInfo ss5_type = {
1361 .name = MACHINE_TYPE_NAME("SS-5"),
1362 .parent = TYPE_MACHINE,
1363 .class_init = ss5_class_init,
1364 };
1365
1366 static void ss10_class_init(ObjectClass *oc, void *data)
1367 {
1368 MachineClass *mc = MACHINE_CLASS(oc);
1369
1370 mc->desc = "Sun4m platform, SPARCstation 10";
1371 mc->init = ss10_init;
1372 mc->block_default_type = IF_SCSI;
1373 mc->max_cpus = 4;
1374 mc->default_boot_order = "c";
1375 }
1376
1377 static const TypeInfo ss10_type = {
1378 .name = MACHINE_TYPE_NAME("SS-10"),
1379 .parent = TYPE_MACHINE,
1380 .class_init = ss10_class_init,
1381 };
1382
1383 static void ss600mp_class_init(ObjectClass *oc, void *data)
1384 {
1385 MachineClass *mc = MACHINE_CLASS(oc);
1386
1387 mc->desc = "Sun4m platform, SPARCserver 600MP";
1388 mc->init = ss600mp_init;
1389 mc->block_default_type = IF_SCSI;
1390 mc->max_cpus = 4;
1391 mc->default_boot_order = "c";
1392 }
1393
1394 static const TypeInfo ss600mp_type = {
1395 .name = MACHINE_TYPE_NAME("SS-600MP"),
1396 .parent = TYPE_MACHINE,
1397 .class_init = ss600mp_class_init,
1398 };
1399
1400 static void ss20_class_init(ObjectClass *oc, void *data)
1401 {
1402 MachineClass *mc = MACHINE_CLASS(oc);
1403
1404 mc->desc = "Sun4m platform, SPARCstation 20";
1405 mc->init = ss20_init;
1406 mc->block_default_type = IF_SCSI;
1407 mc->max_cpus = 4;
1408 mc->default_boot_order = "c";
1409 }
1410
1411 static const TypeInfo ss20_type = {
1412 .name = MACHINE_TYPE_NAME("SS-20"),
1413 .parent = TYPE_MACHINE,
1414 .class_init = ss20_class_init,
1415 };
1416
1417 static void voyager_class_init(ObjectClass *oc, void *data)
1418 {
1419 MachineClass *mc = MACHINE_CLASS(oc);
1420
1421 mc->desc = "Sun4m platform, SPARCstation Voyager";
1422 mc->init = vger_init;
1423 mc->block_default_type = IF_SCSI;
1424 mc->default_boot_order = "c";
1425 }
1426
1427 static const TypeInfo voyager_type = {
1428 .name = MACHINE_TYPE_NAME("Voyager"),
1429 .parent = TYPE_MACHINE,
1430 .class_init = voyager_class_init,
1431 };
1432
1433 static void ss_lx_class_init(ObjectClass *oc, void *data)
1434 {
1435 MachineClass *mc = MACHINE_CLASS(oc);
1436
1437 mc->desc = "Sun4m platform, SPARCstation LX";
1438 mc->init = ss_lx_init;
1439 mc->block_default_type = IF_SCSI;
1440 mc->default_boot_order = "c";
1441 }
1442
1443 static const TypeInfo ss_lx_type = {
1444 .name = MACHINE_TYPE_NAME("LX"),
1445 .parent = TYPE_MACHINE,
1446 .class_init = ss_lx_class_init,
1447 };
1448
1449 static void ss4_class_init(ObjectClass *oc, void *data)
1450 {
1451 MachineClass *mc = MACHINE_CLASS(oc);
1452
1453 mc->desc = "Sun4m platform, SPARCstation 4";
1454 mc->init = ss4_init;
1455 mc->block_default_type = IF_SCSI;
1456 mc->default_boot_order = "c";
1457 }
1458
1459 static const TypeInfo ss4_type = {
1460 .name = MACHINE_TYPE_NAME("SS-4"),
1461 .parent = TYPE_MACHINE,
1462 .class_init = ss4_class_init,
1463 };
1464
1465 static void scls_class_init(ObjectClass *oc, void *data)
1466 {
1467 MachineClass *mc = MACHINE_CLASS(oc);
1468
1469 mc->desc = "Sun4m platform, SPARCClassic";
1470 mc->init = scls_init;
1471 mc->block_default_type = IF_SCSI;
1472 mc->default_boot_order = "c";
1473 }
1474
1475 static const TypeInfo scls_type = {
1476 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1477 .parent = TYPE_MACHINE,
1478 .class_init = scls_class_init,
1479 };
1480
1481 static void sbook_class_init(ObjectClass *oc, void *data)
1482 {
1483 MachineClass *mc = MACHINE_CLASS(oc);
1484
1485 mc->desc = "Sun4m platform, SPARCbook";
1486 mc->init = sbook_init;
1487 mc->block_default_type = IF_SCSI;
1488 mc->default_boot_order = "c";
1489 }
1490
1491 static const TypeInfo sbook_type = {
1492 .name = MACHINE_TYPE_NAME("SPARCbook"),
1493 .parent = TYPE_MACHINE,
1494 .class_init = sbook_class_init,
1495 };
1496
1497 static void sun4m_register_types(void)
1498 {
1499 type_register_static(&idreg_info);
1500 type_register_static(&afx_info);
1501 type_register_static(&prom_info);
1502 type_register_static(&ram_info);
1503
1504 type_register_static(&ss5_type);
1505 type_register_static(&ss10_type);
1506 type_register_static(&ss600mp_type);
1507 type_register_static(&ss20_type);
1508 type_register_static(&voyager_type);
1509 type_register_static(&ss_lx_type);
1510 type_register_static(&ss4_type);
1511 type_register_static(&scls_type);
1512 type_register_static(&sbook_type);
1513 }
1514
1515 type_init(sun4m_register_types)
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