]> git.proxmox.com Git - mirror_qemu.git/blob - hw/sparc/sun4m.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
i8257: pass ISA bus to DMA_init() function
[mirror_qemu.git] / hw / sparc / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "hw/sysbus.h"
26 #include "qemu/error-report.h"
27 #include "qemu/timer.h"
28 #include "hw/sparc/sun4m.h"
29 #include "hw/timer/m48t59.h"
30 #include "hw/sparc/sparc32_dma.h"
31 #include "hw/block/fdc.h"
32 #include "sysemu/sysemu.h"
33 #include "net/net.h"
34 #include "hw/boards.h"
35 #include "hw/nvram/openbios_firmware_abi.h"
36 #include "hw/scsi/esp.h"
37 #include "hw/i386/pc.h"
38 #include "hw/isa/isa.h"
39 #include "hw/nvram/fw_cfg.h"
40 #include "hw/char/escc.h"
41 #include "hw/empty_slot.h"
42 #include "hw/loader.h"
43 #include "elf.h"
44 #include "sysemu/block-backend.h"
45 #include "trace.h"
46
47 /*
48 * Sun4m architecture was used in the following machines:
49 *
50 * SPARCserver 6xxMP/xx
51 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
52 * SPARCclassic X (4/10)
53 * SPARCstation LX/ZX (4/30)
54 * SPARCstation Voyager
55 * SPARCstation 10/xx, SPARCserver 10/xx
56 * SPARCstation 5, SPARCserver 5
57 * SPARCstation 20/xx, SPARCserver 20
58 * SPARCstation 4
59 *
60 * See for example: http://www.sunhelp.org/faq/sunref1.html
61 */
62
63 #define KERNEL_LOAD_ADDR 0x00004000
64 #define CMDLINE_ADDR 0x007ff000
65 #define INITRD_LOAD_ADDR 0x00800000
66 #define PROM_SIZE_MAX (1024 * 1024)
67 #define PROM_VADDR 0xffd00000
68 #define PROM_FILENAME "openbios-sparc32"
69 #define CFG_ADDR 0xd00000510ULL
70 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
71 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
72 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
73
74 #define MAX_CPUS 16
75 #define MAX_PILS 16
76 #define MAX_VSIMMS 4
77
78 #define ESCC_CLOCK 4915200
79
80 struct sun4m_hwdef {
81 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
82 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
83 hwaddr serial_base, fd_base;
84 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
85 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
86 hwaddr bpp_base, dbri_base, sx_base;
87 struct {
88 hwaddr reg_base, vram_base;
89 } vsimm[MAX_VSIMMS];
90 hwaddr ecc_base;
91 uint64_t max_mem;
92 const char * const default_cpu_model;
93 uint32_t ecc_version;
94 uint32_t iommu_version;
95 uint16_t machine_id;
96 uint8_t nvram_machine_id;
97 };
98
99 int DMA_get_channel_mode (int nchan)
100 {
101 return 0;
102 }
103 int DMA_read_memory (int nchan, void *buf, int pos, int size)
104 {
105 return 0;
106 }
107 int DMA_write_memory (int nchan, void *buf, int pos, int size)
108 {
109 return 0;
110 }
111 void DMA_hold_DREQ (int nchan) {}
112 void DMA_release_DREQ (int nchan) {}
113 void DMA_schedule(void) {}
114
115 void DMA_init(ISABus *bus, int high_page_enable)
116 {
117 }
118
119 void DMA_register_channel (int nchan,
120 DMA_transfer_handler transfer_handler,
121 void *opaque)
122 {
123 }
124
125 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
126 Error **errp)
127 {
128 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
129 }
130
131 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
132 const char *cmdline, const char *boot_devices,
133 ram_addr_t RAM_size, uint32_t kernel_size,
134 int width, int height, int depth,
135 int nvram_machine_id, const char *arch)
136 {
137 unsigned int i;
138 uint32_t start, end;
139 uint8_t image[0x1ff0];
140 struct OpenBIOS_nvpart_v1 *part_header;
141 NvramClass *k = NVRAM_GET_CLASS(nvram);
142
143 memset(image, '\0', sizeof(image));
144
145 start = 0;
146
147 // OpenBIOS nvram variables
148 // Variable partition
149 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
150 part_header->signature = OPENBIOS_PART_SYSTEM;
151 pstrcpy(part_header->name, sizeof(part_header->name), "system");
152
153 end = start + sizeof(struct OpenBIOS_nvpart_v1);
154 for (i = 0; i < nb_prom_envs; i++)
155 end = OpenBIOS_set_var(image, end, prom_envs[i]);
156
157 // End marker
158 image[end++] = '\0';
159
160 end = start + ((end - start + 15) & ~15);
161 OpenBIOS_finish_partition(part_header, end - start);
162
163 // free partition
164 start = end;
165 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
166 part_header->signature = OPENBIOS_PART_FREE;
167 pstrcpy(part_header->name, sizeof(part_header->name), "free");
168
169 end = 0x1fd0;
170 OpenBIOS_finish_partition(part_header, end - start);
171
172 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
173 nvram_machine_id);
174
175 for (i = 0; i < sizeof(image); i++) {
176 (k->write)(nvram, i, image[i]);
177 }
178 }
179
180 static DeviceState *slavio_intctl;
181
182 void sun4m_hmp_info_pic(Monitor *mon, const QDict *qdict)
183 {
184 if (slavio_intctl)
185 slavio_pic_info(mon, slavio_intctl);
186 }
187
188 void sun4m_hmp_info_irq(Monitor *mon, const QDict *qdict)
189 {
190 if (slavio_intctl)
191 slavio_irq_info(mon, slavio_intctl);
192 }
193
194 void cpu_check_irqs(CPUSPARCState *env)
195 {
196 CPUState *cs;
197
198 if (env->pil_in && (env->interrupt_index == 0 ||
199 (env->interrupt_index & ~15) == TT_EXTINT)) {
200 unsigned int i;
201
202 for (i = 15; i > 0; i--) {
203 if (env->pil_in & (1 << i)) {
204 int old_interrupt = env->interrupt_index;
205
206 env->interrupt_index = TT_EXTINT | i;
207 if (old_interrupt != env->interrupt_index) {
208 cs = CPU(sparc_env_get_cpu(env));
209 trace_sun4m_cpu_interrupt(i);
210 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
211 }
212 break;
213 }
214 }
215 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
216 cs = CPU(sparc_env_get_cpu(env));
217 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
218 env->interrupt_index = 0;
219 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
220 }
221 }
222
223 static void cpu_kick_irq(SPARCCPU *cpu)
224 {
225 CPUSPARCState *env = &cpu->env;
226 CPUState *cs = CPU(cpu);
227
228 cs->halted = 0;
229 cpu_check_irqs(env);
230 qemu_cpu_kick(cs);
231 }
232
233 static void cpu_set_irq(void *opaque, int irq, int level)
234 {
235 SPARCCPU *cpu = opaque;
236 CPUSPARCState *env = &cpu->env;
237
238 if (level) {
239 trace_sun4m_cpu_set_irq_raise(irq);
240 env->pil_in |= 1 << irq;
241 cpu_kick_irq(cpu);
242 } else {
243 trace_sun4m_cpu_set_irq_lower(irq);
244 env->pil_in &= ~(1 << irq);
245 cpu_check_irqs(env);
246 }
247 }
248
249 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
250 {
251 }
252
253 static void main_cpu_reset(void *opaque)
254 {
255 SPARCCPU *cpu = opaque;
256 CPUState *cs = CPU(cpu);
257
258 cpu_reset(cs);
259 cs->halted = 0;
260 }
261
262 static void secondary_cpu_reset(void *opaque)
263 {
264 SPARCCPU *cpu = opaque;
265 CPUState *cs = CPU(cpu);
266
267 cpu_reset(cs);
268 cs->halted = 1;
269 }
270
271 static void cpu_halt_signal(void *opaque, int irq, int level)
272 {
273 if (level && current_cpu) {
274 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
275 }
276 }
277
278 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
279 {
280 return addr - 0xf0000000ULL;
281 }
282
283 static unsigned long sun4m_load_kernel(const char *kernel_filename,
284 const char *initrd_filename,
285 ram_addr_t RAM_size)
286 {
287 int linux_boot;
288 unsigned int i;
289 long initrd_size, kernel_size;
290 uint8_t *ptr;
291
292 linux_boot = (kernel_filename != NULL);
293
294 kernel_size = 0;
295 if (linux_boot) {
296 int bswap_needed;
297
298 #ifdef BSWAP_NEEDED
299 bswap_needed = 1;
300 #else
301 bswap_needed = 0;
302 #endif
303 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
304 NULL, NULL, NULL, 1, EM_SPARC, 0);
305 if (kernel_size < 0)
306 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
307 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
308 TARGET_PAGE_SIZE);
309 if (kernel_size < 0)
310 kernel_size = load_image_targphys(kernel_filename,
311 KERNEL_LOAD_ADDR,
312 RAM_size - KERNEL_LOAD_ADDR);
313 if (kernel_size < 0) {
314 fprintf(stderr, "qemu: could not load kernel '%s'\n",
315 kernel_filename);
316 exit(1);
317 }
318
319 /* load initrd */
320 initrd_size = 0;
321 if (initrd_filename) {
322 initrd_size = load_image_targphys(initrd_filename,
323 INITRD_LOAD_ADDR,
324 RAM_size - INITRD_LOAD_ADDR);
325 if (initrd_size < 0) {
326 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
327 initrd_filename);
328 exit(1);
329 }
330 }
331 if (initrd_size > 0) {
332 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
333 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
334 if (ldl_p(ptr) == 0x48647253) { // HdrS
335 stl_p(ptr + 16, INITRD_LOAD_ADDR);
336 stl_p(ptr + 20, initrd_size);
337 break;
338 }
339 }
340 }
341 }
342 return kernel_size;
343 }
344
345 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
346 {
347 DeviceState *dev;
348 SysBusDevice *s;
349
350 dev = qdev_create(NULL, "iommu");
351 qdev_prop_set_uint32(dev, "version", version);
352 qdev_init_nofail(dev);
353 s = SYS_BUS_DEVICE(dev);
354 sysbus_connect_irq(s, 0, irq);
355 sysbus_mmio_map(s, 0, addr);
356
357 return s;
358 }
359
360 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
361 void *iommu, qemu_irq *dev_irq, int is_ledma)
362 {
363 DeviceState *dev;
364 SysBusDevice *s;
365
366 dev = qdev_create(NULL, "sparc32_dma");
367 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
368 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
369 qdev_init_nofail(dev);
370 s = SYS_BUS_DEVICE(dev);
371 sysbus_connect_irq(s, 0, parent_irq);
372 *dev_irq = qdev_get_gpio_in(dev, 0);
373 sysbus_mmio_map(s, 0, daddr);
374
375 return s;
376 }
377
378 static void lance_init(NICInfo *nd, hwaddr leaddr,
379 void *dma_opaque, qemu_irq irq)
380 {
381 DeviceState *dev;
382 SysBusDevice *s;
383 qemu_irq reset;
384
385 qemu_check_nic_model(&nd_table[0], "lance");
386
387 dev = qdev_create(NULL, "lance");
388 qdev_set_nic_properties(dev, nd);
389 qdev_prop_set_ptr(dev, "dma", dma_opaque);
390 qdev_init_nofail(dev);
391 s = SYS_BUS_DEVICE(dev);
392 sysbus_mmio_map(s, 0, leaddr);
393 sysbus_connect_irq(s, 0, irq);
394 reset = qdev_get_gpio_in(dev, 0);
395 qdev_connect_gpio_out(dma_opaque, 0, reset);
396 }
397
398 static DeviceState *slavio_intctl_init(hwaddr addr,
399 hwaddr addrg,
400 qemu_irq **parent_irq)
401 {
402 DeviceState *dev;
403 SysBusDevice *s;
404 unsigned int i, j;
405
406 dev = qdev_create(NULL, "slavio_intctl");
407 qdev_init_nofail(dev);
408
409 s = SYS_BUS_DEVICE(dev);
410
411 for (i = 0; i < MAX_CPUS; i++) {
412 for (j = 0; j < MAX_PILS; j++) {
413 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
414 }
415 }
416 sysbus_mmio_map(s, 0, addrg);
417 for (i = 0; i < MAX_CPUS; i++) {
418 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
419 }
420
421 return dev;
422 }
423
424 #define SYS_TIMER_OFFSET 0x10000ULL
425 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
426
427 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
428 qemu_irq *cpu_irqs, unsigned int num_cpus)
429 {
430 DeviceState *dev;
431 SysBusDevice *s;
432 unsigned int i;
433
434 dev = qdev_create(NULL, "slavio_timer");
435 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
436 qdev_init_nofail(dev);
437 s = SYS_BUS_DEVICE(dev);
438 sysbus_connect_irq(s, 0, master_irq);
439 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
440
441 for (i = 0; i < MAX_CPUS; i++) {
442 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
443 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
444 }
445 }
446
447 static qemu_irq slavio_system_powerdown;
448
449 static void slavio_powerdown_req(Notifier *n, void *opaque)
450 {
451 qemu_irq_raise(slavio_system_powerdown);
452 }
453
454 static Notifier slavio_system_powerdown_notifier = {
455 .notify = slavio_powerdown_req
456 };
457
458 #define MISC_LEDS 0x01600000
459 #define MISC_CFG 0x01800000
460 #define MISC_DIAG 0x01a00000
461 #define MISC_MDM 0x01b00000
462 #define MISC_SYS 0x01f00000
463
464 static void slavio_misc_init(hwaddr base,
465 hwaddr aux1_base,
466 hwaddr aux2_base, qemu_irq irq,
467 qemu_irq fdc_tc)
468 {
469 DeviceState *dev;
470 SysBusDevice *s;
471
472 dev = qdev_create(NULL, "slavio_misc");
473 qdev_init_nofail(dev);
474 s = SYS_BUS_DEVICE(dev);
475 if (base) {
476 /* 8 bit registers */
477 /* Slavio control */
478 sysbus_mmio_map(s, 0, base + MISC_CFG);
479 /* Diagnostics */
480 sysbus_mmio_map(s, 1, base + MISC_DIAG);
481 /* Modem control */
482 sysbus_mmio_map(s, 2, base + MISC_MDM);
483 /* 16 bit registers */
484 /* ss600mp diag LEDs */
485 sysbus_mmio_map(s, 3, base + MISC_LEDS);
486 /* 32 bit registers */
487 /* System control */
488 sysbus_mmio_map(s, 4, base + MISC_SYS);
489 }
490 if (aux1_base) {
491 /* AUX 1 (Misc System Functions) */
492 sysbus_mmio_map(s, 5, aux1_base);
493 }
494 if (aux2_base) {
495 /* AUX 2 (Software Powerdown Control) */
496 sysbus_mmio_map(s, 6, aux2_base);
497 }
498 sysbus_connect_irq(s, 0, irq);
499 sysbus_connect_irq(s, 1, fdc_tc);
500 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
501 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
502 }
503
504 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
505 {
506 DeviceState *dev;
507 SysBusDevice *s;
508
509 dev = qdev_create(NULL, "eccmemctl");
510 qdev_prop_set_uint32(dev, "version", version);
511 qdev_init_nofail(dev);
512 s = SYS_BUS_DEVICE(dev);
513 sysbus_connect_irq(s, 0, irq);
514 sysbus_mmio_map(s, 0, base);
515 if (version == 0) { // SS-600MP only
516 sysbus_mmio_map(s, 1, base + 0x1000);
517 }
518 }
519
520 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
521 {
522 DeviceState *dev;
523 SysBusDevice *s;
524
525 dev = qdev_create(NULL, "apc");
526 qdev_init_nofail(dev);
527 s = SYS_BUS_DEVICE(dev);
528 /* Power management (APC) XXX: not a Slavio device */
529 sysbus_mmio_map(s, 0, power_base);
530 sysbus_connect_irq(s, 0, cpu_halt);
531 }
532
533 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
534 int height, int depth)
535 {
536 DeviceState *dev;
537 SysBusDevice *s;
538
539 dev = qdev_create(NULL, "SUNW,tcx");
540 qdev_prop_set_uint32(dev, "vram_size", vram_size);
541 qdev_prop_set_uint16(dev, "width", width);
542 qdev_prop_set_uint16(dev, "height", height);
543 qdev_prop_set_uint16(dev, "depth", depth);
544 qdev_prop_set_uint64(dev, "prom_addr", addr);
545 qdev_init_nofail(dev);
546 s = SYS_BUS_DEVICE(dev);
547
548 /* 10/ROM : FCode ROM */
549 sysbus_mmio_map(s, 0, addr);
550 /* 2/STIP : Stipple */
551 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
552 /* 3/BLIT : Blitter */
553 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
554 /* 5/RSTIP : Raw Stipple */
555 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
556 /* 6/RBLIT : Raw Blitter */
557 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
558 /* 7/TEC : Transform Engine */
559 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
560 /* 8/CMAP : DAC */
561 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
562 /* 9/THC : */
563 if (depth == 8) {
564 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
565 } else {
566 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
567 }
568 /* 11/DHC : */
569 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
570 /* 12/ALT : */
571 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
572 /* 0/DFB8 : 8-bit plane */
573 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
574 /* 1/DFB24 : 24bit plane */
575 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
576 /* 4/RDFB32: Raw framebuffer. Control plane */
577 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
578 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
579 if (depth == 8) {
580 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
581 }
582
583 sysbus_connect_irq(s, 0, irq);
584 }
585
586 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
587 int height, int depth)
588 {
589 DeviceState *dev;
590 SysBusDevice *s;
591
592 dev = qdev_create(NULL, "cgthree");
593 qdev_prop_set_uint32(dev, "vram-size", vram_size);
594 qdev_prop_set_uint16(dev, "width", width);
595 qdev_prop_set_uint16(dev, "height", height);
596 qdev_prop_set_uint16(dev, "depth", depth);
597 qdev_prop_set_uint64(dev, "prom-addr", addr);
598 qdev_init_nofail(dev);
599 s = SYS_BUS_DEVICE(dev);
600
601 /* FCode ROM */
602 sysbus_mmio_map(s, 0, addr);
603 /* DAC */
604 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
605 /* 8-bit plane */
606 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
607
608 sysbus_connect_irq(s, 0, irq);
609 }
610
611 /* NCR89C100/MACIO Internal ID register */
612
613 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
614
615 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
616
617 static void idreg_init(hwaddr addr)
618 {
619 DeviceState *dev;
620 SysBusDevice *s;
621
622 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
623 qdev_init_nofail(dev);
624 s = SYS_BUS_DEVICE(dev);
625
626 sysbus_mmio_map(s, 0, addr);
627 cpu_physical_memory_write_rom(&address_space_memory,
628 addr, idreg_data, sizeof(idreg_data));
629 }
630
631 #define MACIO_ID_REGISTER(obj) \
632 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
633
634 typedef struct IDRegState {
635 SysBusDevice parent_obj;
636
637 MemoryRegion mem;
638 } IDRegState;
639
640 static int idreg_init1(SysBusDevice *dev)
641 {
642 IDRegState *s = MACIO_ID_REGISTER(dev);
643
644 memory_region_init_ram(&s->mem, OBJECT(s),
645 "sun4m.idreg", sizeof(idreg_data), &error_fatal);
646 vmstate_register_ram_global(&s->mem);
647 memory_region_set_readonly(&s->mem, true);
648 sysbus_init_mmio(dev, &s->mem);
649 return 0;
650 }
651
652 static void idreg_class_init(ObjectClass *klass, void *data)
653 {
654 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
655
656 k->init = idreg_init1;
657 }
658
659 static const TypeInfo idreg_info = {
660 .name = TYPE_MACIO_ID_REGISTER,
661 .parent = TYPE_SYS_BUS_DEVICE,
662 .instance_size = sizeof(IDRegState),
663 .class_init = idreg_class_init,
664 };
665
666 #define TYPE_TCX_AFX "tcx_afx"
667 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
668
669 typedef struct AFXState {
670 SysBusDevice parent_obj;
671
672 MemoryRegion mem;
673 } AFXState;
674
675 /* SS-5 TCX AFX register */
676 static void afx_init(hwaddr addr)
677 {
678 DeviceState *dev;
679 SysBusDevice *s;
680
681 dev = qdev_create(NULL, TYPE_TCX_AFX);
682 qdev_init_nofail(dev);
683 s = SYS_BUS_DEVICE(dev);
684
685 sysbus_mmio_map(s, 0, addr);
686 }
687
688 static int afx_init1(SysBusDevice *dev)
689 {
690 AFXState *s = TCX_AFX(dev);
691
692 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_fatal);
693 vmstate_register_ram_global(&s->mem);
694 sysbus_init_mmio(dev, &s->mem);
695 return 0;
696 }
697
698 static void afx_class_init(ObjectClass *klass, void *data)
699 {
700 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
701
702 k->init = afx_init1;
703 }
704
705 static const TypeInfo afx_info = {
706 .name = TYPE_TCX_AFX,
707 .parent = TYPE_SYS_BUS_DEVICE,
708 .instance_size = sizeof(AFXState),
709 .class_init = afx_class_init,
710 };
711
712 #define TYPE_OPENPROM "openprom"
713 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
714
715 typedef struct PROMState {
716 SysBusDevice parent_obj;
717
718 MemoryRegion prom;
719 } PROMState;
720
721 /* Boot PROM (OpenBIOS) */
722 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
723 {
724 hwaddr *base_addr = (hwaddr *)opaque;
725 return addr + *base_addr - PROM_VADDR;
726 }
727
728 static void prom_init(hwaddr addr, const char *bios_name)
729 {
730 DeviceState *dev;
731 SysBusDevice *s;
732 char *filename;
733 int ret;
734
735 dev = qdev_create(NULL, TYPE_OPENPROM);
736 qdev_init_nofail(dev);
737 s = SYS_BUS_DEVICE(dev);
738
739 sysbus_mmio_map(s, 0, addr);
740
741 /* load boot prom */
742 if (bios_name == NULL) {
743 bios_name = PROM_FILENAME;
744 }
745 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
746 if (filename) {
747 ret = load_elf(filename, translate_prom_address, &addr, NULL,
748 NULL, NULL, 1, EM_SPARC, 0);
749 if (ret < 0 || ret > PROM_SIZE_MAX) {
750 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
751 }
752 g_free(filename);
753 } else {
754 ret = -1;
755 }
756 if (ret < 0 || ret > PROM_SIZE_MAX) {
757 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
758 exit(1);
759 }
760 }
761
762 static int prom_init1(SysBusDevice *dev)
763 {
764 PROMState *s = OPENPROM(dev);
765
766 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX,
767 &error_fatal);
768 vmstate_register_ram_global(&s->prom);
769 memory_region_set_readonly(&s->prom, true);
770 sysbus_init_mmio(dev, &s->prom);
771 return 0;
772 }
773
774 static Property prom_properties[] = {
775 {/* end of property list */},
776 };
777
778 static void prom_class_init(ObjectClass *klass, void *data)
779 {
780 DeviceClass *dc = DEVICE_CLASS(klass);
781 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
782
783 k->init = prom_init1;
784 dc->props = prom_properties;
785 }
786
787 static const TypeInfo prom_info = {
788 .name = TYPE_OPENPROM,
789 .parent = TYPE_SYS_BUS_DEVICE,
790 .instance_size = sizeof(PROMState),
791 .class_init = prom_class_init,
792 };
793
794 #define TYPE_SUN4M_MEMORY "memory"
795 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
796
797 typedef struct RamDevice {
798 SysBusDevice parent_obj;
799
800 MemoryRegion ram;
801 uint64_t size;
802 } RamDevice;
803
804 /* System RAM */
805 static int ram_init1(SysBusDevice *dev)
806 {
807 RamDevice *d = SUN4M_RAM(dev);
808
809 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
810 d->size);
811 sysbus_init_mmio(dev, &d->ram);
812 return 0;
813 }
814
815 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
816 uint64_t max_mem)
817 {
818 DeviceState *dev;
819 SysBusDevice *s;
820 RamDevice *d;
821
822 /* allocate RAM */
823 if ((uint64_t)RAM_size > max_mem) {
824 fprintf(stderr,
825 "qemu: Too much memory for this machine: %d, maximum %d\n",
826 (unsigned int)(RAM_size / (1024 * 1024)),
827 (unsigned int)(max_mem / (1024 * 1024)));
828 exit(1);
829 }
830 dev = qdev_create(NULL, "memory");
831 s = SYS_BUS_DEVICE(dev);
832
833 d = SUN4M_RAM(dev);
834 d->size = RAM_size;
835 qdev_init_nofail(dev);
836
837 sysbus_mmio_map(s, 0, addr);
838 }
839
840 static Property ram_properties[] = {
841 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
842 DEFINE_PROP_END_OF_LIST(),
843 };
844
845 static void ram_class_init(ObjectClass *klass, void *data)
846 {
847 DeviceClass *dc = DEVICE_CLASS(klass);
848 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
849
850 k->init = ram_init1;
851 dc->props = ram_properties;
852 }
853
854 static const TypeInfo ram_info = {
855 .name = TYPE_SUN4M_MEMORY,
856 .parent = TYPE_SYS_BUS_DEVICE,
857 .instance_size = sizeof(RamDevice),
858 .class_init = ram_class_init,
859 };
860
861 static void cpu_devinit(const char *cpu_model, unsigned int id,
862 uint64_t prom_addr, qemu_irq **cpu_irqs)
863 {
864 CPUState *cs;
865 SPARCCPU *cpu;
866 CPUSPARCState *env;
867
868 cpu = cpu_sparc_init(cpu_model);
869 if (cpu == NULL) {
870 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
871 exit(1);
872 }
873 env = &cpu->env;
874
875 cpu_sparc_set_id(env, id);
876 if (id == 0) {
877 qemu_register_reset(main_cpu_reset, cpu);
878 } else {
879 qemu_register_reset(secondary_cpu_reset, cpu);
880 cs = CPU(cpu);
881 cs->halted = 1;
882 }
883 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
884 env->prom_addr = prom_addr;
885 }
886
887 static void dummy_fdc_tc(void *opaque, int irq, int level)
888 {
889 }
890
891 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
892 MachineState *machine)
893 {
894 const char *cpu_model = machine->cpu_model;
895 unsigned int i;
896 void *iommu, *espdma, *ledma, *nvram;
897 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
898 espdma_irq, ledma_irq;
899 qemu_irq esp_reset, dma_enable;
900 qemu_irq fdc_tc;
901 unsigned long kernel_size;
902 DriveInfo *fd[MAX_FD];
903 FWCfgState *fw_cfg;
904 unsigned int num_vsimms;
905
906 /* init CPUs */
907 if (!cpu_model)
908 cpu_model = hwdef->default_cpu_model;
909
910 for(i = 0; i < smp_cpus; i++) {
911 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
912 }
913
914 for (i = smp_cpus; i < MAX_CPUS; i++)
915 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
916
917
918 /* set up devices */
919 ram_init(0, machine->ram_size, hwdef->max_mem);
920 /* models without ECC don't trap when missing ram is accessed */
921 if (!hwdef->ecc_base) {
922 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
923 }
924
925 prom_init(hwdef->slavio_base, bios_name);
926
927 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
928 hwdef->intctl_base + 0x10000ULL,
929 cpu_irqs);
930
931 for (i = 0; i < 32; i++) {
932 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
933 }
934 for (i = 0; i < MAX_CPUS; i++) {
935 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
936 }
937
938 if (hwdef->idreg_base) {
939 idreg_init(hwdef->idreg_base);
940 }
941
942 if (hwdef->afx_base) {
943 afx_init(hwdef->afx_base);
944 }
945
946 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
947 slavio_irq[30]);
948
949 if (hwdef->iommu_pad_base) {
950 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
951 Software shouldn't use aliased addresses, neither should it crash
952 when does. Using empty_slot instead of aliasing can help with
953 debugging such accesses */
954 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
955 }
956
957 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
958 iommu, &espdma_irq, 0);
959
960 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
961 slavio_irq[16], iommu, &ledma_irq, 1);
962
963 if (graphic_depth != 8 && graphic_depth != 24) {
964 error_report("Unsupported depth: %d", graphic_depth);
965 exit (1);
966 }
967 num_vsimms = 0;
968 if (num_vsimms == 0) {
969 if (vga_interface_type == VGA_CG3) {
970 if (graphic_depth != 8) {
971 error_report("Unsupported depth: %d", graphic_depth);
972 exit(1);
973 }
974
975 if (!(graphic_width == 1024 && graphic_height == 768) &&
976 !(graphic_width == 1152 && graphic_height == 900)) {
977 error_report("Unsupported resolution: %d x %d", graphic_width,
978 graphic_height);
979 exit(1);
980 }
981
982 /* sbus irq 5 */
983 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
984 graphic_width, graphic_height, graphic_depth);
985 } else {
986 /* If no display specified, default to TCX */
987 if (graphic_depth != 8 && graphic_depth != 24) {
988 error_report("Unsupported depth: %d", graphic_depth);
989 exit(1);
990 }
991
992 if (!(graphic_width == 1024 && graphic_height == 768)) {
993 error_report("Unsupported resolution: %d x %d",
994 graphic_width, graphic_height);
995 exit(1);
996 }
997
998 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
999 graphic_width, graphic_height, graphic_depth);
1000 }
1001 }
1002
1003 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
1004 /* vsimm registers probed by OBP */
1005 if (hwdef->vsimm[i].reg_base) {
1006 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
1007 }
1008 }
1009
1010 if (hwdef->sx_base) {
1011 empty_slot_init(hwdef->sx_base, 0x2000);
1012 }
1013
1014 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1015
1016 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
1017
1018 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
1019
1020 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
1021 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1022 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1023 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1024 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
1025 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1026
1027 if (hwdef->apc_base) {
1028 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1029 }
1030
1031 if (hwdef->fd_base) {
1032 /* there is zero or one floppy drive */
1033 memset(fd, 0, sizeof(fd));
1034 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1035 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1036 &fdc_tc);
1037 } else {
1038 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1039 }
1040
1041 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1042 slavio_irq[30], fdc_tc);
1043
1044 if (drive_get_max_bus(IF_SCSI) > 0) {
1045 fprintf(stderr, "qemu: too many SCSI bus\n");
1046 exit(1);
1047 }
1048
1049 esp_init(hwdef->esp_base, 2,
1050 espdma_memory_read, espdma_memory_write,
1051 espdma, espdma_irq, &esp_reset, &dma_enable);
1052
1053 qdev_connect_gpio_out(espdma, 0, esp_reset);
1054 qdev_connect_gpio_out(espdma, 1, dma_enable);
1055
1056 if (hwdef->cs_base) {
1057 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1058 slavio_irq[5]);
1059 }
1060
1061 if (hwdef->dbri_base) {
1062 /* ISDN chip with attached CS4215 audio codec */
1063 /* prom space */
1064 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1065 /* reg space */
1066 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1067 }
1068
1069 if (hwdef->bpp_base) {
1070 /* parallel port */
1071 empty_slot_init(hwdef->bpp_base, 0x20);
1072 }
1073
1074 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1075 machine->initrd_filename,
1076 machine->ram_size);
1077
1078 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1079 machine->boot_order, machine->ram_size, kernel_size,
1080 graphic_width, graphic_height, graphic_depth,
1081 hwdef->nvram_machine_id, "Sun4m");
1082
1083 if (hwdef->ecc_base)
1084 ecc_init(hwdef->ecc_base, slavio_irq[28],
1085 hwdef->ecc_version);
1086
1087 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
1088 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1089 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1090 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1091 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1092 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1093 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1094 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1095 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1096 if (machine->kernel_cmdline) {
1097 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1098 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1099 machine->kernel_cmdline);
1100 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1101 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1102 strlen(machine->kernel_cmdline) + 1);
1103 } else {
1104 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1105 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1106 }
1107 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1108 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1109 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1110 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1111 }
1112
1113 enum {
1114 ss5_id = 32,
1115 vger_id,
1116 lx_id,
1117 ss4_id,
1118 scls_id,
1119 sbook_id,
1120 ss10_id = 64,
1121 ss20_id,
1122 ss600mp_id,
1123 };
1124
1125 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1126 /* SS-5 */
1127 {
1128 .iommu_base = 0x10000000,
1129 .iommu_pad_base = 0x10004000,
1130 .iommu_pad_len = 0x0fffb000,
1131 .tcx_base = 0x50000000,
1132 .cs_base = 0x6c000000,
1133 .slavio_base = 0x70000000,
1134 .ms_kb_base = 0x71000000,
1135 .serial_base = 0x71100000,
1136 .nvram_base = 0x71200000,
1137 .fd_base = 0x71400000,
1138 .counter_base = 0x71d00000,
1139 .intctl_base = 0x71e00000,
1140 .idreg_base = 0x78000000,
1141 .dma_base = 0x78400000,
1142 .esp_base = 0x78800000,
1143 .le_base = 0x78c00000,
1144 .apc_base = 0x6a000000,
1145 .afx_base = 0x6e000000,
1146 .aux1_base = 0x71900000,
1147 .aux2_base = 0x71910000,
1148 .nvram_machine_id = 0x80,
1149 .machine_id = ss5_id,
1150 .iommu_version = 0x05000000,
1151 .max_mem = 0x10000000,
1152 .default_cpu_model = "Fujitsu MB86904",
1153 },
1154 /* SS-10 */
1155 {
1156 .iommu_base = 0xfe0000000ULL,
1157 .tcx_base = 0xe20000000ULL,
1158 .slavio_base = 0xff0000000ULL,
1159 .ms_kb_base = 0xff1000000ULL,
1160 .serial_base = 0xff1100000ULL,
1161 .nvram_base = 0xff1200000ULL,
1162 .fd_base = 0xff1700000ULL,
1163 .counter_base = 0xff1300000ULL,
1164 .intctl_base = 0xff1400000ULL,
1165 .idreg_base = 0xef0000000ULL,
1166 .dma_base = 0xef0400000ULL,
1167 .esp_base = 0xef0800000ULL,
1168 .le_base = 0xef0c00000ULL,
1169 .apc_base = 0xefa000000ULL, // XXX should not exist
1170 .aux1_base = 0xff1800000ULL,
1171 .aux2_base = 0xff1a01000ULL,
1172 .ecc_base = 0xf00000000ULL,
1173 .ecc_version = 0x10000000, // version 0, implementation 1
1174 .nvram_machine_id = 0x72,
1175 .machine_id = ss10_id,
1176 .iommu_version = 0x03000000,
1177 .max_mem = 0xf00000000ULL,
1178 .default_cpu_model = "TI SuperSparc II",
1179 },
1180 /* SS-600MP */
1181 {
1182 .iommu_base = 0xfe0000000ULL,
1183 .tcx_base = 0xe20000000ULL,
1184 .slavio_base = 0xff0000000ULL,
1185 .ms_kb_base = 0xff1000000ULL,
1186 .serial_base = 0xff1100000ULL,
1187 .nvram_base = 0xff1200000ULL,
1188 .counter_base = 0xff1300000ULL,
1189 .intctl_base = 0xff1400000ULL,
1190 .dma_base = 0xef0081000ULL,
1191 .esp_base = 0xef0080000ULL,
1192 .le_base = 0xef0060000ULL,
1193 .apc_base = 0xefa000000ULL, // XXX should not exist
1194 .aux1_base = 0xff1800000ULL,
1195 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1196 .ecc_base = 0xf00000000ULL,
1197 .ecc_version = 0x00000000, // version 0, implementation 0
1198 .nvram_machine_id = 0x71,
1199 .machine_id = ss600mp_id,
1200 .iommu_version = 0x01000000,
1201 .max_mem = 0xf00000000ULL,
1202 .default_cpu_model = "TI SuperSparc II",
1203 },
1204 /* SS-20 */
1205 {
1206 .iommu_base = 0xfe0000000ULL,
1207 .tcx_base = 0xe20000000ULL,
1208 .slavio_base = 0xff0000000ULL,
1209 .ms_kb_base = 0xff1000000ULL,
1210 .serial_base = 0xff1100000ULL,
1211 .nvram_base = 0xff1200000ULL,
1212 .fd_base = 0xff1700000ULL,
1213 .counter_base = 0xff1300000ULL,
1214 .intctl_base = 0xff1400000ULL,
1215 .idreg_base = 0xef0000000ULL,
1216 .dma_base = 0xef0400000ULL,
1217 .esp_base = 0xef0800000ULL,
1218 .le_base = 0xef0c00000ULL,
1219 .bpp_base = 0xef4800000ULL,
1220 .apc_base = 0xefa000000ULL, // XXX should not exist
1221 .aux1_base = 0xff1800000ULL,
1222 .aux2_base = 0xff1a01000ULL,
1223 .dbri_base = 0xee0000000ULL,
1224 .sx_base = 0xf80000000ULL,
1225 .vsimm = {
1226 {
1227 .reg_base = 0x9c000000ULL,
1228 .vram_base = 0xfc000000ULL
1229 }, {
1230 .reg_base = 0x90000000ULL,
1231 .vram_base = 0xf0000000ULL
1232 }, {
1233 .reg_base = 0x94000000ULL
1234 }, {
1235 .reg_base = 0x98000000ULL
1236 }
1237 },
1238 .ecc_base = 0xf00000000ULL,
1239 .ecc_version = 0x20000000, // version 0, implementation 2
1240 .nvram_machine_id = 0x72,
1241 .machine_id = ss20_id,
1242 .iommu_version = 0x13000000,
1243 .max_mem = 0xf00000000ULL,
1244 .default_cpu_model = "TI SuperSparc II",
1245 },
1246 /* Voyager */
1247 {
1248 .iommu_base = 0x10000000,
1249 .tcx_base = 0x50000000,
1250 .slavio_base = 0x70000000,
1251 .ms_kb_base = 0x71000000,
1252 .serial_base = 0x71100000,
1253 .nvram_base = 0x71200000,
1254 .fd_base = 0x71400000,
1255 .counter_base = 0x71d00000,
1256 .intctl_base = 0x71e00000,
1257 .idreg_base = 0x78000000,
1258 .dma_base = 0x78400000,
1259 .esp_base = 0x78800000,
1260 .le_base = 0x78c00000,
1261 .apc_base = 0x71300000, // pmc
1262 .aux1_base = 0x71900000,
1263 .aux2_base = 0x71910000,
1264 .nvram_machine_id = 0x80,
1265 .machine_id = vger_id,
1266 .iommu_version = 0x05000000,
1267 .max_mem = 0x10000000,
1268 .default_cpu_model = "Fujitsu MB86904",
1269 },
1270 /* LX */
1271 {
1272 .iommu_base = 0x10000000,
1273 .iommu_pad_base = 0x10004000,
1274 .iommu_pad_len = 0x0fffb000,
1275 .tcx_base = 0x50000000,
1276 .slavio_base = 0x70000000,
1277 .ms_kb_base = 0x71000000,
1278 .serial_base = 0x71100000,
1279 .nvram_base = 0x71200000,
1280 .fd_base = 0x71400000,
1281 .counter_base = 0x71d00000,
1282 .intctl_base = 0x71e00000,
1283 .idreg_base = 0x78000000,
1284 .dma_base = 0x78400000,
1285 .esp_base = 0x78800000,
1286 .le_base = 0x78c00000,
1287 .aux1_base = 0x71900000,
1288 .aux2_base = 0x71910000,
1289 .nvram_machine_id = 0x80,
1290 .machine_id = lx_id,
1291 .iommu_version = 0x04000000,
1292 .max_mem = 0x10000000,
1293 .default_cpu_model = "TI MicroSparc I",
1294 },
1295 /* SS-4 */
1296 {
1297 .iommu_base = 0x10000000,
1298 .tcx_base = 0x50000000,
1299 .cs_base = 0x6c000000,
1300 .slavio_base = 0x70000000,
1301 .ms_kb_base = 0x71000000,
1302 .serial_base = 0x71100000,
1303 .nvram_base = 0x71200000,
1304 .fd_base = 0x71400000,
1305 .counter_base = 0x71d00000,
1306 .intctl_base = 0x71e00000,
1307 .idreg_base = 0x78000000,
1308 .dma_base = 0x78400000,
1309 .esp_base = 0x78800000,
1310 .le_base = 0x78c00000,
1311 .apc_base = 0x6a000000,
1312 .aux1_base = 0x71900000,
1313 .aux2_base = 0x71910000,
1314 .nvram_machine_id = 0x80,
1315 .machine_id = ss4_id,
1316 .iommu_version = 0x05000000,
1317 .max_mem = 0x10000000,
1318 .default_cpu_model = "Fujitsu MB86904",
1319 },
1320 /* SPARCClassic */
1321 {
1322 .iommu_base = 0x10000000,
1323 .tcx_base = 0x50000000,
1324 .slavio_base = 0x70000000,
1325 .ms_kb_base = 0x71000000,
1326 .serial_base = 0x71100000,
1327 .nvram_base = 0x71200000,
1328 .fd_base = 0x71400000,
1329 .counter_base = 0x71d00000,
1330 .intctl_base = 0x71e00000,
1331 .idreg_base = 0x78000000,
1332 .dma_base = 0x78400000,
1333 .esp_base = 0x78800000,
1334 .le_base = 0x78c00000,
1335 .apc_base = 0x6a000000,
1336 .aux1_base = 0x71900000,
1337 .aux2_base = 0x71910000,
1338 .nvram_machine_id = 0x80,
1339 .machine_id = scls_id,
1340 .iommu_version = 0x05000000,
1341 .max_mem = 0x10000000,
1342 .default_cpu_model = "TI MicroSparc I",
1343 },
1344 /* SPARCbook */
1345 {
1346 .iommu_base = 0x10000000,
1347 .tcx_base = 0x50000000, // XXX
1348 .slavio_base = 0x70000000,
1349 .ms_kb_base = 0x71000000,
1350 .serial_base = 0x71100000,
1351 .nvram_base = 0x71200000,
1352 .fd_base = 0x71400000,
1353 .counter_base = 0x71d00000,
1354 .intctl_base = 0x71e00000,
1355 .idreg_base = 0x78000000,
1356 .dma_base = 0x78400000,
1357 .esp_base = 0x78800000,
1358 .le_base = 0x78c00000,
1359 .apc_base = 0x6a000000,
1360 .aux1_base = 0x71900000,
1361 .aux2_base = 0x71910000,
1362 .nvram_machine_id = 0x80,
1363 .machine_id = sbook_id,
1364 .iommu_version = 0x05000000,
1365 .max_mem = 0x10000000,
1366 .default_cpu_model = "TI MicroSparc I",
1367 },
1368 };
1369
1370 /* SPARCstation 5 hardware initialisation */
1371 static void ss5_init(MachineState *machine)
1372 {
1373 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1374 }
1375
1376 /* SPARCstation 10 hardware initialisation */
1377 static void ss10_init(MachineState *machine)
1378 {
1379 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1380 }
1381
1382 /* SPARCserver 600MP hardware initialisation */
1383 static void ss600mp_init(MachineState *machine)
1384 {
1385 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1386 }
1387
1388 /* SPARCstation 20 hardware initialisation */
1389 static void ss20_init(MachineState *machine)
1390 {
1391 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1392 }
1393
1394 /* SPARCstation Voyager hardware initialisation */
1395 static void vger_init(MachineState *machine)
1396 {
1397 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1398 }
1399
1400 /* SPARCstation LX hardware initialisation */
1401 static void ss_lx_init(MachineState *machine)
1402 {
1403 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1404 }
1405
1406 /* SPARCstation 4 hardware initialisation */
1407 static void ss4_init(MachineState *machine)
1408 {
1409 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1410 }
1411
1412 /* SPARCClassic hardware initialisation */
1413 static void scls_init(MachineState *machine)
1414 {
1415 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1416 }
1417
1418 /* SPARCbook hardware initialisation */
1419 static void sbook_init(MachineState *machine)
1420 {
1421 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1422 }
1423
1424 static void ss5_class_init(ObjectClass *oc, void *data)
1425 {
1426 MachineClass *mc = MACHINE_CLASS(oc);
1427
1428 mc->desc = "Sun4m platform, SPARCstation 5";
1429 mc->init = ss5_init;
1430 mc->block_default_type = IF_SCSI;
1431 mc->is_default = 1;
1432 mc->default_boot_order = "c";
1433 }
1434
1435 static const TypeInfo ss5_type = {
1436 .name = MACHINE_TYPE_NAME("SS-5"),
1437 .parent = TYPE_MACHINE,
1438 .class_init = ss5_class_init,
1439 };
1440
1441 static void ss10_class_init(ObjectClass *oc, void *data)
1442 {
1443 MachineClass *mc = MACHINE_CLASS(oc);
1444
1445 mc->desc = "Sun4m platform, SPARCstation 10";
1446 mc->init = ss10_init;
1447 mc->block_default_type = IF_SCSI;
1448 mc->max_cpus = 4;
1449 mc->default_boot_order = "c";
1450 }
1451
1452 static const TypeInfo ss10_type = {
1453 .name = MACHINE_TYPE_NAME("SS-10"),
1454 .parent = TYPE_MACHINE,
1455 .class_init = ss10_class_init,
1456 };
1457
1458 static void ss600mp_class_init(ObjectClass *oc, void *data)
1459 {
1460 MachineClass *mc = MACHINE_CLASS(oc);
1461
1462 mc->desc = "Sun4m platform, SPARCserver 600MP";
1463 mc->init = ss600mp_init;
1464 mc->block_default_type = IF_SCSI;
1465 mc->max_cpus = 4;
1466 mc->default_boot_order = "c";
1467 }
1468
1469 static const TypeInfo ss600mp_type = {
1470 .name = MACHINE_TYPE_NAME("SS-600MP"),
1471 .parent = TYPE_MACHINE,
1472 .class_init = ss600mp_class_init,
1473 };
1474
1475 static void ss20_class_init(ObjectClass *oc, void *data)
1476 {
1477 MachineClass *mc = MACHINE_CLASS(oc);
1478
1479 mc->desc = "Sun4m platform, SPARCstation 20";
1480 mc->init = ss20_init;
1481 mc->block_default_type = IF_SCSI;
1482 mc->max_cpus = 4;
1483 mc->default_boot_order = "c";
1484 }
1485
1486 static const TypeInfo ss20_type = {
1487 .name = MACHINE_TYPE_NAME("SS-20"),
1488 .parent = TYPE_MACHINE,
1489 .class_init = ss20_class_init,
1490 };
1491
1492 static void voyager_class_init(ObjectClass *oc, void *data)
1493 {
1494 MachineClass *mc = MACHINE_CLASS(oc);
1495
1496 mc->desc = "Sun4m platform, SPARCstation Voyager";
1497 mc->init = vger_init;
1498 mc->block_default_type = IF_SCSI;
1499 mc->default_boot_order = "c";
1500 }
1501
1502 static const TypeInfo voyager_type = {
1503 .name = MACHINE_TYPE_NAME("Voyager"),
1504 .parent = TYPE_MACHINE,
1505 .class_init = voyager_class_init,
1506 };
1507
1508 static void ss_lx_class_init(ObjectClass *oc, void *data)
1509 {
1510 MachineClass *mc = MACHINE_CLASS(oc);
1511
1512 mc->desc = "Sun4m platform, SPARCstation LX";
1513 mc->init = ss_lx_init;
1514 mc->block_default_type = IF_SCSI;
1515 mc->default_boot_order = "c";
1516 }
1517
1518 static const TypeInfo ss_lx_type = {
1519 .name = MACHINE_TYPE_NAME("LX"),
1520 .parent = TYPE_MACHINE,
1521 .class_init = ss_lx_class_init,
1522 };
1523
1524 static void ss4_class_init(ObjectClass *oc, void *data)
1525 {
1526 MachineClass *mc = MACHINE_CLASS(oc);
1527
1528 mc->desc = "Sun4m platform, SPARCstation 4";
1529 mc->init = ss4_init;
1530 mc->block_default_type = IF_SCSI;
1531 mc->default_boot_order = "c";
1532 }
1533
1534 static const TypeInfo ss4_type = {
1535 .name = MACHINE_TYPE_NAME("SS-4"),
1536 .parent = TYPE_MACHINE,
1537 .class_init = ss4_class_init,
1538 };
1539
1540 static void scls_class_init(ObjectClass *oc, void *data)
1541 {
1542 MachineClass *mc = MACHINE_CLASS(oc);
1543
1544 mc->desc = "Sun4m platform, SPARCClassic";
1545 mc->init = scls_init;
1546 mc->block_default_type = IF_SCSI;
1547 mc->default_boot_order = "c";
1548 }
1549
1550 static const TypeInfo scls_type = {
1551 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1552 .parent = TYPE_MACHINE,
1553 .class_init = scls_class_init,
1554 };
1555
1556 static void sbook_class_init(ObjectClass *oc, void *data)
1557 {
1558 MachineClass *mc = MACHINE_CLASS(oc);
1559
1560 mc->desc = "Sun4m platform, SPARCbook";
1561 mc->init = sbook_init;
1562 mc->block_default_type = IF_SCSI;
1563 mc->default_boot_order = "c";
1564 }
1565
1566 static const TypeInfo sbook_type = {
1567 .name = MACHINE_TYPE_NAME("SPARCbook"),
1568 .parent = TYPE_MACHINE,
1569 .class_init = sbook_class_init,
1570 };
1571
1572 static void sun4m_register_types(void)
1573 {
1574 type_register_static(&idreg_info);
1575 type_register_static(&afx_info);
1576 type_register_static(&prom_info);
1577 type_register_static(&ram_info);
1578 }
1579
1580 static void sun4m_machine_init(void)
1581 {
1582 type_register_static(&ss5_type);
1583 type_register_static(&ss10_type);
1584 type_register_static(&ss600mp_type);
1585 type_register_static(&ss20_type);
1586 type_register_static(&voyager_type);
1587 type_register_static(&ss_lx_type);
1588 type_register_static(&ss4_type);
1589 type_register_static(&scls_type);
1590 type_register_static(&sbook_type);
1591 }
1592
1593 type_init(sun4m_register_types)
1594 machine_init(sun4m_machine_init)
QEMU mirror