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Merge remote-tracking branch 'remotes/mcayland/tags/qemu-openbios-signed' into staging
[mirror_qemu.git] / hw / sparc / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "hw/sparc/sun4m.h"
32 #include "hw/timer/m48t59.h"
33 #include "hw/sparc/sparc32_dma.h"
34 #include "hw/block/fdc.h"
35 #include "sysemu/sysemu.h"
36 #include "net/net.h"
37 #include "hw/boards.h"
38 #include "hw/scsi/esp.h"
39 #include "hw/i386/pc.h"
40 #include "hw/isa/isa.h"
41 #include "hw/nvram/sun_nvram.h"
42 #include "hw/nvram/chrp_nvram.h"
43 #include "hw/nvram/fw_cfg.h"
44 #include "hw/char/escc.h"
45 #include "hw/empty_slot.h"
46 #include "hw/loader.h"
47 #include "elf.h"
48 #include "sysemu/block-backend.h"
49 #include "trace.h"
50 #include "qemu/cutils.h"
51
52 /*
53 * Sun4m architecture was used in the following machines:
54 *
55 * SPARCserver 6xxMP/xx
56 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
57 * SPARCclassic X (4/10)
58 * SPARCstation LX/ZX (4/30)
59 * SPARCstation Voyager
60 * SPARCstation 10/xx, SPARCserver 10/xx
61 * SPARCstation 5, SPARCserver 5
62 * SPARCstation 20/xx, SPARCserver 20
63 * SPARCstation 4
64 *
65 * See for example: http://www.sunhelp.org/faq/sunref1.html
66 */
67
68 #define KERNEL_LOAD_ADDR 0x00004000
69 #define CMDLINE_ADDR 0x007ff000
70 #define INITRD_LOAD_ADDR 0x00800000
71 #define PROM_SIZE_MAX (1024 * 1024)
72 #define PROM_VADDR 0xffd00000
73 #define PROM_FILENAME "openbios-sparc32"
74 #define CFG_ADDR 0xd00000510ULL
75 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
76 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
77 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
78
79 #define MAX_CPUS 16
80 #define MAX_PILS 16
81 #define MAX_VSIMMS 4
82
83 #define ESCC_CLOCK 4915200
84
85 struct sun4m_hwdef {
86 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
87 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
88 hwaddr serial_base, fd_base;
89 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
90 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
91 hwaddr bpp_base, dbri_base, sx_base;
92 struct {
93 hwaddr reg_base, vram_base;
94 } vsimm[MAX_VSIMMS];
95 hwaddr ecc_base;
96 uint64_t max_mem;
97 const char * const default_cpu_model;
98 uint32_t ecc_version;
99 uint32_t iommu_version;
100 uint16_t machine_id;
101 uint8_t nvram_machine_id;
102 };
103
104 void DMA_init(ISABus *bus, int high_page_enable)
105 {
106 }
107
108 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
109 Error **errp)
110 {
111 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
112 }
113
114 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
115 const char *cmdline, const char *boot_devices,
116 ram_addr_t RAM_size, uint32_t kernel_size,
117 int width, int height, int depth,
118 int nvram_machine_id, const char *arch)
119 {
120 unsigned int i;
121 int sysp_end;
122 uint8_t image[0x1ff0];
123 NvramClass *k = NVRAM_GET_CLASS(nvram);
124
125 memset(image, '\0', sizeof(image));
126
127 /* OpenBIOS nvram variables partition */
128 sysp_end = chrp_nvram_create_system_partition(image, 0);
129
130 /* Free space partition */
131 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
132
133 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
134 nvram_machine_id);
135
136 for (i = 0; i < sizeof(image); i++) {
137 (k->write)(nvram, i, image[i]);
138 }
139 }
140
141 void cpu_check_irqs(CPUSPARCState *env)
142 {
143 CPUState *cs;
144
145 /* We should be holding the BQL before we mess with IRQs */
146 g_assert(qemu_mutex_iothread_locked());
147
148 if (env->pil_in && (env->interrupt_index == 0 ||
149 (env->interrupt_index & ~15) == TT_EXTINT)) {
150 unsigned int i;
151
152 for (i = 15; i > 0; i--) {
153 if (env->pil_in & (1 << i)) {
154 int old_interrupt = env->interrupt_index;
155
156 env->interrupt_index = TT_EXTINT | i;
157 if (old_interrupt != env->interrupt_index) {
158 cs = CPU(sparc_env_get_cpu(env));
159 trace_sun4m_cpu_interrupt(i);
160 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
161 }
162 break;
163 }
164 }
165 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
166 cs = CPU(sparc_env_get_cpu(env));
167 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
168 env->interrupt_index = 0;
169 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
170 }
171 }
172
173 static void cpu_kick_irq(SPARCCPU *cpu)
174 {
175 CPUSPARCState *env = &cpu->env;
176 CPUState *cs = CPU(cpu);
177
178 cs->halted = 0;
179 cpu_check_irqs(env);
180 qemu_cpu_kick(cs);
181 }
182
183 static void cpu_set_irq(void *opaque, int irq, int level)
184 {
185 SPARCCPU *cpu = opaque;
186 CPUSPARCState *env = &cpu->env;
187
188 if (level) {
189 trace_sun4m_cpu_set_irq_raise(irq);
190 env->pil_in |= 1 << irq;
191 cpu_kick_irq(cpu);
192 } else {
193 trace_sun4m_cpu_set_irq_lower(irq);
194 env->pil_in &= ~(1 << irq);
195 cpu_check_irqs(env);
196 }
197 }
198
199 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
200 {
201 }
202
203 static void main_cpu_reset(void *opaque)
204 {
205 SPARCCPU *cpu = opaque;
206 CPUState *cs = CPU(cpu);
207
208 cpu_reset(cs);
209 cs->halted = 0;
210 }
211
212 static void secondary_cpu_reset(void *opaque)
213 {
214 SPARCCPU *cpu = opaque;
215 CPUState *cs = CPU(cpu);
216
217 cpu_reset(cs);
218 cs->halted = 1;
219 }
220
221 static void cpu_halt_signal(void *opaque, int irq, int level)
222 {
223 if (level && current_cpu) {
224 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
225 }
226 }
227
228 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
229 {
230 return addr - 0xf0000000ULL;
231 }
232
233 static unsigned long sun4m_load_kernel(const char *kernel_filename,
234 const char *initrd_filename,
235 ram_addr_t RAM_size)
236 {
237 int linux_boot;
238 unsigned int i;
239 long initrd_size, kernel_size;
240 uint8_t *ptr;
241
242 linux_boot = (kernel_filename != NULL);
243
244 kernel_size = 0;
245 if (linux_boot) {
246 int bswap_needed;
247
248 #ifdef BSWAP_NEEDED
249 bswap_needed = 1;
250 #else
251 bswap_needed = 0;
252 #endif
253 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
254 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
255 if (kernel_size < 0)
256 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
257 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
258 TARGET_PAGE_SIZE);
259 if (kernel_size < 0)
260 kernel_size = load_image_targphys(kernel_filename,
261 KERNEL_LOAD_ADDR,
262 RAM_size - KERNEL_LOAD_ADDR);
263 if (kernel_size < 0) {
264 fprintf(stderr, "qemu: could not load kernel '%s'\n",
265 kernel_filename);
266 exit(1);
267 }
268
269 /* load initrd */
270 initrd_size = 0;
271 if (initrd_filename) {
272 initrd_size = load_image_targphys(initrd_filename,
273 INITRD_LOAD_ADDR,
274 RAM_size - INITRD_LOAD_ADDR);
275 if (initrd_size < 0) {
276 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
277 initrd_filename);
278 exit(1);
279 }
280 }
281 if (initrd_size > 0) {
282 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
283 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
284 if (ldl_p(ptr) == 0x48647253) { // HdrS
285 stl_p(ptr + 16, INITRD_LOAD_ADDR);
286 stl_p(ptr + 20, initrd_size);
287 break;
288 }
289 }
290 }
291 }
292 return kernel_size;
293 }
294
295 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
296 {
297 DeviceState *dev;
298 SysBusDevice *s;
299
300 dev = qdev_create(NULL, "iommu");
301 qdev_prop_set_uint32(dev, "version", version);
302 qdev_init_nofail(dev);
303 s = SYS_BUS_DEVICE(dev);
304 sysbus_connect_irq(s, 0, irq);
305 sysbus_mmio_map(s, 0, addr);
306
307 return s;
308 }
309
310 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
311 void *iommu, qemu_irq *dev_irq, int is_ledma)
312 {
313 DeviceState *dev;
314 SysBusDevice *s;
315
316 dev = qdev_create(NULL, "sparc32_dma");
317 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
318 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
319 qdev_init_nofail(dev);
320 s = SYS_BUS_DEVICE(dev);
321 sysbus_connect_irq(s, 0, parent_irq);
322 *dev_irq = qdev_get_gpio_in(dev, 0);
323 sysbus_mmio_map(s, 0, daddr);
324
325 return s;
326 }
327
328 static void lance_init(NICInfo *nd, hwaddr leaddr,
329 void *dma_opaque, qemu_irq irq)
330 {
331 DeviceState *dev;
332 SysBusDevice *s;
333 qemu_irq reset;
334
335 qemu_check_nic_model(&nd_table[0], "lance");
336
337 dev = qdev_create(NULL, "lance");
338 qdev_set_nic_properties(dev, nd);
339 qdev_prop_set_ptr(dev, "dma", dma_opaque);
340 qdev_init_nofail(dev);
341 s = SYS_BUS_DEVICE(dev);
342 sysbus_mmio_map(s, 0, leaddr);
343 sysbus_connect_irq(s, 0, irq);
344 reset = qdev_get_gpio_in(dev, 0);
345 qdev_connect_gpio_out(dma_opaque, 0, reset);
346 }
347
348 static DeviceState *slavio_intctl_init(hwaddr addr,
349 hwaddr addrg,
350 qemu_irq **parent_irq)
351 {
352 DeviceState *dev;
353 SysBusDevice *s;
354 unsigned int i, j;
355
356 dev = qdev_create(NULL, "slavio_intctl");
357 qdev_init_nofail(dev);
358
359 s = SYS_BUS_DEVICE(dev);
360
361 for (i = 0; i < MAX_CPUS; i++) {
362 for (j = 0; j < MAX_PILS; j++) {
363 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
364 }
365 }
366 sysbus_mmio_map(s, 0, addrg);
367 for (i = 0; i < MAX_CPUS; i++) {
368 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
369 }
370
371 return dev;
372 }
373
374 #define SYS_TIMER_OFFSET 0x10000ULL
375 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
376
377 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
378 qemu_irq *cpu_irqs, unsigned int num_cpus)
379 {
380 DeviceState *dev;
381 SysBusDevice *s;
382 unsigned int i;
383
384 dev = qdev_create(NULL, "slavio_timer");
385 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
386 qdev_init_nofail(dev);
387 s = SYS_BUS_DEVICE(dev);
388 sysbus_connect_irq(s, 0, master_irq);
389 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
390
391 for (i = 0; i < MAX_CPUS; i++) {
392 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
393 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
394 }
395 }
396
397 static qemu_irq slavio_system_powerdown;
398
399 static void slavio_powerdown_req(Notifier *n, void *opaque)
400 {
401 qemu_irq_raise(slavio_system_powerdown);
402 }
403
404 static Notifier slavio_system_powerdown_notifier = {
405 .notify = slavio_powerdown_req
406 };
407
408 #define MISC_LEDS 0x01600000
409 #define MISC_CFG 0x01800000
410 #define MISC_DIAG 0x01a00000
411 #define MISC_MDM 0x01b00000
412 #define MISC_SYS 0x01f00000
413
414 static void slavio_misc_init(hwaddr base,
415 hwaddr aux1_base,
416 hwaddr aux2_base, qemu_irq irq,
417 qemu_irq fdc_tc)
418 {
419 DeviceState *dev;
420 SysBusDevice *s;
421
422 dev = qdev_create(NULL, "slavio_misc");
423 qdev_init_nofail(dev);
424 s = SYS_BUS_DEVICE(dev);
425 if (base) {
426 /* 8 bit registers */
427 /* Slavio control */
428 sysbus_mmio_map(s, 0, base + MISC_CFG);
429 /* Diagnostics */
430 sysbus_mmio_map(s, 1, base + MISC_DIAG);
431 /* Modem control */
432 sysbus_mmio_map(s, 2, base + MISC_MDM);
433 /* 16 bit registers */
434 /* ss600mp diag LEDs */
435 sysbus_mmio_map(s, 3, base + MISC_LEDS);
436 /* 32 bit registers */
437 /* System control */
438 sysbus_mmio_map(s, 4, base + MISC_SYS);
439 }
440 if (aux1_base) {
441 /* AUX 1 (Misc System Functions) */
442 sysbus_mmio_map(s, 5, aux1_base);
443 }
444 if (aux2_base) {
445 /* AUX 2 (Software Powerdown Control) */
446 sysbus_mmio_map(s, 6, aux2_base);
447 }
448 sysbus_connect_irq(s, 0, irq);
449 sysbus_connect_irq(s, 1, fdc_tc);
450 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
451 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
452 }
453
454 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
455 {
456 DeviceState *dev;
457 SysBusDevice *s;
458
459 dev = qdev_create(NULL, "eccmemctl");
460 qdev_prop_set_uint32(dev, "version", version);
461 qdev_init_nofail(dev);
462 s = SYS_BUS_DEVICE(dev);
463 sysbus_connect_irq(s, 0, irq);
464 sysbus_mmio_map(s, 0, base);
465 if (version == 0) { // SS-600MP only
466 sysbus_mmio_map(s, 1, base + 0x1000);
467 }
468 }
469
470 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
471 {
472 DeviceState *dev;
473 SysBusDevice *s;
474
475 dev = qdev_create(NULL, "apc");
476 qdev_init_nofail(dev);
477 s = SYS_BUS_DEVICE(dev);
478 /* Power management (APC) XXX: not a Slavio device */
479 sysbus_mmio_map(s, 0, power_base);
480 sysbus_connect_irq(s, 0, cpu_halt);
481 }
482
483 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
484 int height, int depth)
485 {
486 DeviceState *dev;
487 SysBusDevice *s;
488
489 dev = qdev_create(NULL, "SUNW,tcx");
490 qdev_prop_set_uint32(dev, "vram_size", vram_size);
491 qdev_prop_set_uint16(dev, "width", width);
492 qdev_prop_set_uint16(dev, "height", height);
493 qdev_prop_set_uint16(dev, "depth", depth);
494 qdev_init_nofail(dev);
495 s = SYS_BUS_DEVICE(dev);
496
497 /* 10/ROM : FCode ROM */
498 sysbus_mmio_map(s, 0, addr);
499 /* 2/STIP : Stipple */
500 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
501 /* 3/BLIT : Blitter */
502 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
503 /* 5/RSTIP : Raw Stipple */
504 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
505 /* 6/RBLIT : Raw Blitter */
506 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
507 /* 7/TEC : Transform Engine */
508 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
509 /* 8/CMAP : DAC */
510 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
511 /* 9/THC : */
512 if (depth == 8) {
513 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
514 } else {
515 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
516 }
517 /* 11/DHC : */
518 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
519 /* 12/ALT : */
520 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
521 /* 0/DFB8 : 8-bit plane */
522 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
523 /* 1/DFB24 : 24bit plane */
524 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
525 /* 4/RDFB32: Raw framebuffer. Control plane */
526 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
527 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
528 if (depth == 8) {
529 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
530 }
531
532 sysbus_connect_irq(s, 0, irq);
533 }
534
535 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
536 int height, int depth)
537 {
538 DeviceState *dev;
539 SysBusDevice *s;
540
541 dev = qdev_create(NULL, "cgthree");
542 qdev_prop_set_uint32(dev, "vram-size", vram_size);
543 qdev_prop_set_uint16(dev, "width", width);
544 qdev_prop_set_uint16(dev, "height", height);
545 qdev_prop_set_uint16(dev, "depth", depth);
546 qdev_init_nofail(dev);
547 s = SYS_BUS_DEVICE(dev);
548
549 /* FCode ROM */
550 sysbus_mmio_map(s, 0, addr);
551 /* DAC */
552 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
553 /* 8-bit plane */
554 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
555
556 sysbus_connect_irq(s, 0, irq);
557 }
558
559 /* NCR89C100/MACIO Internal ID register */
560
561 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
562
563 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
564
565 static void idreg_init(hwaddr addr)
566 {
567 DeviceState *dev;
568 SysBusDevice *s;
569
570 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
571 qdev_init_nofail(dev);
572 s = SYS_BUS_DEVICE(dev);
573
574 sysbus_mmio_map(s, 0, addr);
575 cpu_physical_memory_write_rom(&address_space_memory,
576 addr, idreg_data, sizeof(idreg_data));
577 }
578
579 #define MACIO_ID_REGISTER(obj) \
580 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
581
582 typedef struct IDRegState {
583 SysBusDevice parent_obj;
584
585 MemoryRegion mem;
586 } IDRegState;
587
588 static int idreg_init1(SysBusDevice *dev)
589 {
590 IDRegState *s = MACIO_ID_REGISTER(dev);
591
592 memory_region_init_ram(&s->mem, OBJECT(s),
593 "sun4m.idreg", sizeof(idreg_data), &error_fatal);
594 vmstate_register_ram_global(&s->mem);
595 memory_region_set_readonly(&s->mem, true);
596 sysbus_init_mmio(dev, &s->mem);
597 return 0;
598 }
599
600 static void idreg_class_init(ObjectClass *klass, void *data)
601 {
602 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
603
604 k->init = idreg_init1;
605 }
606
607 static const TypeInfo idreg_info = {
608 .name = TYPE_MACIO_ID_REGISTER,
609 .parent = TYPE_SYS_BUS_DEVICE,
610 .instance_size = sizeof(IDRegState),
611 .class_init = idreg_class_init,
612 };
613
614 #define TYPE_TCX_AFX "tcx_afx"
615 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
616
617 typedef struct AFXState {
618 SysBusDevice parent_obj;
619
620 MemoryRegion mem;
621 } AFXState;
622
623 /* SS-5 TCX AFX register */
624 static void afx_init(hwaddr addr)
625 {
626 DeviceState *dev;
627 SysBusDevice *s;
628
629 dev = qdev_create(NULL, TYPE_TCX_AFX);
630 qdev_init_nofail(dev);
631 s = SYS_BUS_DEVICE(dev);
632
633 sysbus_mmio_map(s, 0, addr);
634 }
635
636 static int afx_init1(SysBusDevice *dev)
637 {
638 AFXState *s = TCX_AFX(dev);
639
640 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_fatal);
641 vmstate_register_ram_global(&s->mem);
642 sysbus_init_mmio(dev, &s->mem);
643 return 0;
644 }
645
646 static void afx_class_init(ObjectClass *klass, void *data)
647 {
648 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
649
650 k->init = afx_init1;
651 }
652
653 static const TypeInfo afx_info = {
654 .name = TYPE_TCX_AFX,
655 .parent = TYPE_SYS_BUS_DEVICE,
656 .instance_size = sizeof(AFXState),
657 .class_init = afx_class_init,
658 };
659
660 #define TYPE_OPENPROM "openprom"
661 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
662
663 typedef struct PROMState {
664 SysBusDevice parent_obj;
665
666 MemoryRegion prom;
667 } PROMState;
668
669 /* Boot PROM (OpenBIOS) */
670 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
671 {
672 hwaddr *base_addr = (hwaddr *)opaque;
673 return addr + *base_addr - PROM_VADDR;
674 }
675
676 static void prom_init(hwaddr addr, const char *bios_name)
677 {
678 DeviceState *dev;
679 SysBusDevice *s;
680 char *filename;
681 int ret;
682
683 dev = qdev_create(NULL, TYPE_OPENPROM);
684 qdev_init_nofail(dev);
685 s = SYS_BUS_DEVICE(dev);
686
687 sysbus_mmio_map(s, 0, addr);
688
689 /* load boot prom */
690 if (bios_name == NULL) {
691 bios_name = PROM_FILENAME;
692 }
693 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
694 if (filename) {
695 ret = load_elf(filename, translate_prom_address, &addr, NULL,
696 NULL, NULL, 1, EM_SPARC, 0, 0);
697 if (ret < 0 || ret > PROM_SIZE_MAX) {
698 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
699 }
700 g_free(filename);
701 } else {
702 ret = -1;
703 }
704 if (ret < 0 || ret > PROM_SIZE_MAX) {
705 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
706 exit(1);
707 }
708 }
709
710 static int prom_init1(SysBusDevice *dev)
711 {
712 PROMState *s = OPENPROM(dev);
713
714 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX,
715 &error_fatal);
716 vmstate_register_ram_global(&s->prom);
717 memory_region_set_readonly(&s->prom, true);
718 sysbus_init_mmio(dev, &s->prom);
719 return 0;
720 }
721
722 static Property prom_properties[] = {
723 {/* end of property list */},
724 };
725
726 static void prom_class_init(ObjectClass *klass, void *data)
727 {
728 DeviceClass *dc = DEVICE_CLASS(klass);
729 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
730
731 k->init = prom_init1;
732 dc->props = prom_properties;
733 }
734
735 static const TypeInfo prom_info = {
736 .name = TYPE_OPENPROM,
737 .parent = TYPE_SYS_BUS_DEVICE,
738 .instance_size = sizeof(PROMState),
739 .class_init = prom_class_init,
740 };
741
742 #define TYPE_SUN4M_MEMORY "memory"
743 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
744
745 typedef struct RamDevice {
746 SysBusDevice parent_obj;
747
748 MemoryRegion ram;
749 uint64_t size;
750 } RamDevice;
751
752 /* System RAM */
753 static int ram_init1(SysBusDevice *dev)
754 {
755 RamDevice *d = SUN4M_RAM(dev);
756
757 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
758 d->size);
759 sysbus_init_mmio(dev, &d->ram);
760 return 0;
761 }
762
763 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
764 uint64_t max_mem)
765 {
766 DeviceState *dev;
767 SysBusDevice *s;
768 RamDevice *d;
769
770 /* allocate RAM */
771 if ((uint64_t)RAM_size > max_mem) {
772 fprintf(stderr,
773 "qemu: Too much memory for this machine: %d, maximum %d\n",
774 (unsigned int)(RAM_size / (1024 * 1024)),
775 (unsigned int)(max_mem / (1024 * 1024)));
776 exit(1);
777 }
778 dev = qdev_create(NULL, "memory");
779 s = SYS_BUS_DEVICE(dev);
780
781 d = SUN4M_RAM(dev);
782 d->size = RAM_size;
783 qdev_init_nofail(dev);
784
785 sysbus_mmio_map(s, 0, addr);
786 }
787
788 static Property ram_properties[] = {
789 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
790 DEFINE_PROP_END_OF_LIST(),
791 };
792
793 static void ram_class_init(ObjectClass *klass, void *data)
794 {
795 DeviceClass *dc = DEVICE_CLASS(klass);
796 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
797
798 k->init = ram_init1;
799 dc->props = ram_properties;
800 }
801
802 static const TypeInfo ram_info = {
803 .name = TYPE_SUN4M_MEMORY,
804 .parent = TYPE_SYS_BUS_DEVICE,
805 .instance_size = sizeof(RamDevice),
806 .class_init = ram_class_init,
807 };
808
809 static void cpu_devinit(const char *cpu_model, unsigned int id,
810 uint64_t prom_addr, qemu_irq **cpu_irqs)
811 {
812 CPUState *cs;
813 SPARCCPU *cpu;
814 CPUSPARCState *env;
815
816 cpu = cpu_sparc_init(cpu_model);
817 if (cpu == NULL) {
818 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
819 exit(1);
820 }
821 env = &cpu->env;
822
823 cpu_sparc_set_id(env, id);
824 if (id == 0) {
825 qemu_register_reset(main_cpu_reset, cpu);
826 } else {
827 qemu_register_reset(secondary_cpu_reset, cpu);
828 cs = CPU(cpu);
829 cs->halted = 1;
830 }
831 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
832 env->prom_addr = prom_addr;
833 }
834
835 static void dummy_fdc_tc(void *opaque, int irq, int level)
836 {
837 }
838
839 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
840 MachineState *machine)
841 {
842 DeviceState *slavio_intctl;
843 const char *cpu_model = machine->cpu_model;
844 unsigned int i;
845 void *iommu, *espdma, *ledma, *nvram;
846 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
847 espdma_irq, ledma_irq;
848 qemu_irq esp_reset, dma_enable;
849 qemu_irq fdc_tc;
850 unsigned long kernel_size;
851 DriveInfo *fd[MAX_FD];
852 FWCfgState *fw_cfg;
853 unsigned int num_vsimms;
854
855 /* init CPUs */
856 if (!cpu_model)
857 cpu_model = hwdef->default_cpu_model;
858
859 for(i = 0; i < smp_cpus; i++) {
860 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
861 }
862
863 for (i = smp_cpus; i < MAX_CPUS; i++)
864 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
865
866
867 /* set up devices */
868 ram_init(0, machine->ram_size, hwdef->max_mem);
869 /* models without ECC don't trap when missing ram is accessed */
870 if (!hwdef->ecc_base) {
871 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
872 }
873
874 prom_init(hwdef->slavio_base, bios_name);
875
876 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
877 hwdef->intctl_base + 0x10000ULL,
878 cpu_irqs);
879
880 for (i = 0; i < 32; i++) {
881 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
882 }
883 for (i = 0; i < MAX_CPUS; i++) {
884 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
885 }
886
887 if (hwdef->idreg_base) {
888 idreg_init(hwdef->idreg_base);
889 }
890
891 if (hwdef->afx_base) {
892 afx_init(hwdef->afx_base);
893 }
894
895 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
896 slavio_irq[30]);
897
898 if (hwdef->iommu_pad_base) {
899 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
900 Software shouldn't use aliased addresses, neither should it crash
901 when does. Using empty_slot instead of aliasing can help with
902 debugging such accesses */
903 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
904 }
905
906 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
907 iommu, &espdma_irq, 0);
908
909 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
910 slavio_irq[16], iommu, &ledma_irq, 1);
911
912 if (graphic_depth != 8 && graphic_depth != 24) {
913 error_report("Unsupported depth: %d", graphic_depth);
914 exit (1);
915 }
916 num_vsimms = 0;
917 if (num_vsimms == 0) {
918 if (vga_interface_type == VGA_CG3) {
919 if (graphic_depth != 8) {
920 error_report("Unsupported depth: %d", graphic_depth);
921 exit(1);
922 }
923
924 if (!(graphic_width == 1024 && graphic_height == 768) &&
925 !(graphic_width == 1152 && graphic_height == 900)) {
926 error_report("Unsupported resolution: %d x %d", graphic_width,
927 graphic_height);
928 exit(1);
929 }
930
931 /* sbus irq 5 */
932 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
933 graphic_width, graphic_height, graphic_depth);
934 } else {
935 /* If no display specified, default to TCX */
936 if (graphic_depth != 8 && graphic_depth != 24) {
937 error_report("Unsupported depth: %d", graphic_depth);
938 exit(1);
939 }
940
941 if (!(graphic_width == 1024 && graphic_height == 768)) {
942 error_report("Unsupported resolution: %d x %d",
943 graphic_width, graphic_height);
944 exit(1);
945 }
946
947 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
948 graphic_width, graphic_height, graphic_depth);
949 }
950 }
951
952 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
953 /* vsimm registers probed by OBP */
954 if (hwdef->vsimm[i].reg_base) {
955 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
956 }
957 }
958
959 if (hwdef->sx_base) {
960 empty_slot_init(hwdef->sx_base, 0x2000);
961 }
962
963 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
964
965 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
966
967 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
968
969 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
970 !machine->enable_graphics, ESCC_CLOCK, 1);
971 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
972 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
973 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
974 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
975
976 if (hwdef->apc_base) {
977 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
978 }
979
980 if (hwdef->fd_base) {
981 /* there is zero or one floppy drive */
982 memset(fd, 0, sizeof(fd));
983 fd[0] = drive_get(IF_FLOPPY, 0, 0);
984 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
985 &fdc_tc);
986 } else {
987 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
988 }
989
990 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
991 slavio_irq[30], fdc_tc);
992
993 esp_init(hwdef->esp_base, 2,
994 espdma_memory_read, espdma_memory_write,
995 espdma, espdma_irq, &esp_reset, &dma_enable);
996
997 qdev_connect_gpio_out(espdma, 0, esp_reset);
998 qdev_connect_gpio_out(espdma, 1, dma_enable);
999
1000 if (hwdef->cs_base) {
1001 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1002 slavio_irq[5]);
1003 }
1004
1005 if (hwdef->dbri_base) {
1006 /* ISDN chip with attached CS4215 audio codec */
1007 /* prom space */
1008 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1009 /* reg space */
1010 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1011 }
1012
1013 if (hwdef->bpp_base) {
1014 /* parallel port */
1015 empty_slot_init(hwdef->bpp_base, 0x20);
1016 }
1017
1018 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1019 machine->initrd_filename,
1020 machine->ram_size);
1021
1022 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1023 machine->boot_order, machine->ram_size, kernel_size,
1024 graphic_width, graphic_height, graphic_depth,
1025 hwdef->nvram_machine_id, "Sun4m");
1026
1027 if (hwdef->ecc_base)
1028 ecc_init(hwdef->ecc_base, slavio_irq[28],
1029 hwdef->ecc_version);
1030
1031 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
1032 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1033 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1034 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1035 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1036 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1037 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1038 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1039 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1040 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1041 if (machine->kernel_cmdline) {
1042 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1043 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1044 machine->kernel_cmdline);
1045 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1046 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1047 strlen(machine->kernel_cmdline) + 1);
1048 } else {
1049 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1050 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1051 }
1052 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1053 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1054 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1055 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1056 }
1057
1058 enum {
1059 ss5_id = 32,
1060 vger_id,
1061 lx_id,
1062 ss4_id,
1063 scls_id,
1064 sbook_id,
1065 ss10_id = 64,
1066 ss20_id,
1067 ss600mp_id,
1068 };
1069
1070 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1071 /* SS-5 */
1072 {
1073 .iommu_base = 0x10000000,
1074 .iommu_pad_base = 0x10004000,
1075 .iommu_pad_len = 0x0fffb000,
1076 .tcx_base = 0x50000000,
1077 .cs_base = 0x6c000000,
1078 .slavio_base = 0x70000000,
1079 .ms_kb_base = 0x71000000,
1080 .serial_base = 0x71100000,
1081 .nvram_base = 0x71200000,
1082 .fd_base = 0x71400000,
1083 .counter_base = 0x71d00000,
1084 .intctl_base = 0x71e00000,
1085 .idreg_base = 0x78000000,
1086 .dma_base = 0x78400000,
1087 .esp_base = 0x78800000,
1088 .le_base = 0x78c00000,
1089 .apc_base = 0x6a000000,
1090 .afx_base = 0x6e000000,
1091 .aux1_base = 0x71900000,
1092 .aux2_base = 0x71910000,
1093 .nvram_machine_id = 0x80,
1094 .machine_id = ss5_id,
1095 .iommu_version = 0x05000000,
1096 .max_mem = 0x10000000,
1097 .default_cpu_model = "Fujitsu MB86904",
1098 },
1099 /* SS-10 */
1100 {
1101 .iommu_base = 0xfe0000000ULL,
1102 .tcx_base = 0xe20000000ULL,
1103 .slavio_base = 0xff0000000ULL,
1104 .ms_kb_base = 0xff1000000ULL,
1105 .serial_base = 0xff1100000ULL,
1106 .nvram_base = 0xff1200000ULL,
1107 .fd_base = 0xff1700000ULL,
1108 .counter_base = 0xff1300000ULL,
1109 .intctl_base = 0xff1400000ULL,
1110 .idreg_base = 0xef0000000ULL,
1111 .dma_base = 0xef0400000ULL,
1112 .esp_base = 0xef0800000ULL,
1113 .le_base = 0xef0c00000ULL,
1114 .apc_base = 0xefa000000ULL, // XXX should not exist
1115 .aux1_base = 0xff1800000ULL,
1116 .aux2_base = 0xff1a01000ULL,
1117 .ecc_base = 0xf00000000ULL,
1118 .ecc_version = 0x10000000, // version 0, implementation 1
1119 .nvram_machine_id = 0x72,
1120 .machine_id = ss10_id,
1121 .iommu_version = 0x03000000,
1122 .max_mem = 0xf00000000ULL,
1123 .default_cpu_model = "TI SuperSparc II",
1124 },
1125 /* SS-600MP */
1126 {
1127 .iommu_base = 0xfe0000000ULL,
1128 .tcx_base = 0xe20000000ULL,
1129 .slavio_base = 0xff0000000ULL,
1130 .ms_kb_base = 0xff1000000ULL,
1131 .serial_base = 0xff1100000ULL,
1132 .nvram_base = 0xff1200000ULL,
1133 .counter_base = 0xff1300000ULL,
1134 .intctl_base = 0xff1400000ULL,
1135 .dma_base = 0xef0081000ULL,
1136 .esp_base = 0xef0080000ULL,
1137 .le_base = 0xef0060000ULL,
1138 .apc_base = 0xefa000000ULL, // XXX should not exist
1139 .aux1_base = 0xff1800000ULL,
1140 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1141 .ecc_base = 0xf00000000ULL,
1142 .ecc_version = 0x00000000, // version 0, implementation 0
1143 .nvram_machine_id = 0x71,
1144 .machine_id = ss600mp_id,
1145 .iommu_version = 0x01000000,
1146 .max_mem = 0xf00000000ULL,
1147 .default_cpu_model = "TI SuperSparc II",
1148 },
1149 /* SS-20 */
1150 {
1151 .iommu_base = 0xfe0000000ULL,
1152 .tcx_base = 0xe20000000ULL,
1153 .slavio_base = 0xff0000000ULL,
1154 .ms_kb_base = 0xff1000000ULL,
1155 .serial_base = 0xff1100000ULL,
1156 .nvram_base = 0xff1200000ULL,
1157 .fd_base = 0xff1700000ULL,
1158 .counter_base = 0xff1300000ULL,
1159 .intctl_base = 0xff1400000ULL,
1160 .idreg_base = 0xef0000000ULL,
1161 .dma_base = 0xef0400000ULL,
1162 .esp_base = 0xef0800000ULL,
1163 .le_base = 0xef0c00000ULL,
1164 .bpp_base = 0xef4800000ULL,
1165 .apc_base = 0xefa000000ULL, // XXX should not exist
1166 .aux1_base = 0xff1800000ULL,
1167 .aux2_base = 0xff1a01000ULL,
1168 .dbri_base = 0xee0000000ULL,
1169 .sx_base = 0xf80000000ULL,
1170 .vsimm = {
1171 {
1172 .reg_base = 0x9c000000ULL,
1173 .vram_base = 0xfc000000ULL
1174 }, {
1175 .reg_base = 0x90000000ULL,
1176 .vram_base = 0xf0000000ULL
1177 }, {
1178 .reg_base = 0x94000000ULL
1179 }, {
1180 .reg_base = 0x98000000ULL
1181 }
1182 },
1183 .ecc_base = 0xf00000000ULL,
1184 .ecc_version = 0x20000000, // version 0, implementation 2
1185 .nvram_machine_id = 0x72,
1186 .machine_id = ss20_id,
1187 .iommu_version = 0x13000000,
1188 .max_mem = 0xf00000000ULL,
1189 .default_cpu_model = "TI SuperSparc II",
1190 },
1191 /* Voyager */
1192 {
1193 .iommu_base = 0x10000000,
1194 .tcx_base = 0x50000000,
1195 .slavio_base = 0x70000000,
1196 .ms_kb_base = 0x71000000,
1197 .serial_base = 0x71100000,
1198 .nvram_base = 0x71200000,
1199 .fd_base = 0x71400000,
1200 .counter_base = 0x71d00000,
1201 .intctl_base = 0x71e00000,
1202 .idreg_base = 0x78000000,
1203 .dma_base = 0x78400000,
1204 .esp_base = 0x78800000,
1205 .le_base = 0x78c00000,
1206 .apc_base = 0x71300000, // pmc
1207 .aux1_base = 0x71900000,
1208 .aux2_base = 0x71910000,
1209 .nvram_machine_id = 0x80,
1210 .machine_id = vger_id,
1211 .iommu_version = 0x05000000,
1212 .max_mem = 0x10000000,
1213 .default_cpu_model = "Fujitsu MB86904",
1214 },
1215 /* LX */
1216 {
1217 .iommu_base = 0x10000000,
1218 .iommu_pad_base = 0x10004000,
1219 .iommu_pad_len = 0x0fffb000,
1220 .tcx_base = 0x50000000,
1221 .slavio_base = 0x70000000,
1222 .ms_kb_base = 0x71000000,
1223 .serial_base = 0x71100000,
1224 .nvram_base = 0x71200000,
1225 .fd_base = 0x71400000,
1226 .counter_base = 0x71d00000,
1227 .intctl_base = 0x71e00000,
1228 .idreg_base = 0x78000000,
1229 .dma_base = 0x78400000,
1230 .esp_base = 0x78800000,
1231 .le_base = 0x78c00000,
1232 .aux1_base = 0x71900000,
1233 .aux2_base = 0x71910000,
1234 .nvram_machine_id = 0x80,
1235 .machine_id = lx_id,
1236 .iommu_version = 0x04000000,
1237 .max_mem = 0x10000000,
1238 .default_cpu_model = "TI MicroSparc I",
1239 },
1240 /* SS-4 */
1241 {
1242 .iommu_base = 0x10000000,
1243 .tcx_base = 0x50000000,
1244 .cs_base = 0x6c000000,
1245 .slavio_base = 0x70000000,
1246 .ms_kb_base = 0x71000000,
1247 .serial_base = 0x71100000,
1248 .nvram_base = 0x71200000,
1249 .fd_base = 0x71400000,
1250 .counter_base = 0x71d00000,
1251 .intctl_base = 0x71e00000,
1252 .idreg_base = 0x78000000,
1253 .dma_base = 0x78400000,
1254 .esp_base = 0x78800000,
1255 .le_base = 0x78c00000,
1256 .apc_base = 0x6a000000,
1257 .aux1_base = 0x71900000,
1258 .aux2_base = 0x71910000,
1259 .nvram_machine_id = 0x80,
1260 .machine_id = ss4_id,
1261 .iommu_version = 0x05000000,
1262 .max_mem = 0x10000000,
1263 .default_cpu_model = "Fujitsu MB86904",
1264 },
1265 /* SPARCClassic */
1266 {
1267 .iommu_base = 0x10000000,
1268 .tcx_base = 0x50000000,
1269 .slavio_base = 0x70000000,
1270 .ms_kb_base = 0x71000000,
1271 .serial_base = 0x71100000,
1272 .nvram_base = 0x71200000,
1273 .fd_base = 0x71400000,
1274 .counter_base = 0x71d00000,
1275 .intctl_base = 0x71e00000,
1276 .idreg_base = 0x78000000,
1277 .dma_base = 0x78400000,
1278 .esp_base = 0x78800000,
1279 .le_base = 0x78c00000,
1280 .apc_base = 0x6a000000,
1281 .aux1_base = 0x71900000,
1282 .aux2_base = 0x71910000,
1283 .nvram_machine_id = 0x80,
1284 .machine_id = scls_id,
1285 .iommu_version = 0x05000000,
1286 .max_mem = 0x10000000,
1287 .default_cpu_model = "TI MicroSparc I",
1288 },
1289 /* SPARCbook */
1290 {
1291 .iommu_base = 0x10000000,
1292 .tcx_base = 0x50000000, // XXX
1293 .slavio_base = 0x70000000,
1294 .ms_kb_base = 0x71000000,
1295 .serial_base = 0x71100000,
1296 .nvram_base = 0x71200000,
1297 .fd_base = 0x71400000,
1298 .counter_base = 0x71d00000,
1299 .intctl_base = 0x71e00000,
1300 .idreg_base = 0x78000000,
1301 .dma_base = 0x78400000,
1302 .esp_base = 0x78800000,
1303 .le_base = 0x78c00000,
1304 .apc_base = 0x6a000000,
1305 .aux1_base = 0x71900000,
1306 .aux2_base = 0x71910000,
1307 .nvram_machine_id = 0x80,
1308 .machine_id = sbook_id,
1309 .iommu_version = 0x05000000,
1310 .max_mem = 0x10000000,
1311 .default_cpu_model = "TI MicroSparc I",
1312 },
1313 };
1314
1315 /* SPARCstation 5 hardware initialisation */
1316 static void ss5_init(MachineState *machine)
1317 {
1318 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1319 }
1320
1321 /* SPARCstation 10 hardware initialisation */
1322 static void ss10_init(MachineState *machine)
1323 {
1324 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1325 }
1326
1327 /* SPARCserver 600MP hardware initialisation */
1328 static void ss600mp_init(MachineState *machine)
1329 {
1330 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1331 }
1332
1333 /* SPARCstation 20 hardware initialisation */
1334 static void ss20_init(MachineState *machine)
1335 {
1336 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1337 }
1338
1339 /* SPARCstation Voyager hardware initialisation */
1340 static void vger_init(MachineState *machine)
1341 {
1342 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1343 }
1344
1345 /* SPARCstation LX hardware initialisation */
1346 static void ss_lx_init(MachineState *machine)
1347 {
1348 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1349 }
1350
1351 /* SPARCstation 4 hardware initialisation */
1352 static void ss4_init(MachineState *machine)
1353 {
1354 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1355 }
1356
1357 /* SPARCClassic hardware initialisation */
1358 static void scls_init(MachineState *machine)
1359 {
1360 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1361 }
1362
1363 /* SPARCbook hardware initialisation */
1364 static void sbook_init(MachineState *machine)
1365 {
1366 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1367 }
1368
1369 static void ss5_class_init(ObjectClass *oc, void *data)
1370 {
1371 MachineClass *mc = MACHINE_CLASS(oc);
1372
1373 mc->desc = "Sun4m platform, SPARCstation 5";
1374 mc->init = ss5_init;
1375 mc->block_default_type = IF_SCSI;
1376 mc->is_default = 1;
1377 mc->default_boot_order = "c";
1378 }
1379
1380 static const TypeInfo ss5_type = {
1381 .name = MACHINE_TYPE_NAME("SS-5"),
1382 .parent = TYPE_MACHINE,
1383 .class_init = ss5_class_init,
1384 };
1385
1386 static void ss10_class_init(ObjectClass *oc, void *data)
1387 {
1388 MachineClass *mc = MACHINE_CLASS(oc);
1389
1390 mc->desc = "Sun4m platform, SPARCstation 10";
1391 mc->init = ss10_init;
1392 mc->block_default_type = IF_SCSI;
1393 mc->max_cpus = 4;
1394 mc->default_boot_order = "c";
1395 }
1396
1397 static const TypeInfo ss10_type = {
1398 .name = MACHINE_TYPE_NAME("SS-10"),
1399 .parent = TYPE_MACHINE,
1400 .class_init = ss10_class_init,
1401 };
1402
1403 static void ss600mp_class_init(ObjectClass *oc, void *data)
1404 {
1405 MachineClass *mc = MACHINE_CLASS(oc);
1406
1407 mc->desc = "Sun4m platform, SPARCserver 600MP";
1408 mc->init = ss600mp_init;
1409 mc->block_default_type = IF_SCSI;
1410 mc->max_cpus = 4;
1411 mc->default_boot_order = "c";
1412 }
1413
1414 static const TypeInfo ss600mp_type = {
1415 .name = MACHINE_TYPE_NAME("SS-600MP"),
1416 .parent = TYPE_MACHINE,
1417 .class_init = ss600mp_class_init,
1418 };
1419
1420 static void ss20_class_init(ObjectClass *oc, void *data)
1421 {
1422 MachineClass *mc = MACHINE_CLASS(oc);
1423
1424 mc->desc = "Sun4m platform, SPARCstation 20";
1425 mc->init = ss20_init;
1426 mc->block_default_type = IF_SCSI;
1427 mc->max_cpus = 4;
1428 mc->default_boot_order = "c";
1429 }
1430
1431 static const TypeInfo ss20_type = {
1432 .name = MACHINE_TYPE_NAME("SS-20"),
1433 .parent = TYPE_MACHINE,
1434 .class_init = ss20_class_init,
1435 };
1436
1437 static void voyager_class_init(ObjectClass *oc, void *data)
1438 {
1439 MachineClass *mc = MACHINE_CLASS(oc);
1440
1441 mc->desc = "Sun4m platform, SPARCstation Voyager";
1442 mc->init = vger_init;
1443 mc->block_default_type = IF_SCSI;
1444 mc->default_boot_order = "c";
1445 }
1446
1447 static const TypeInfo voyager_type = {
1448 .name = MACHINE_TYPE_NAME("Voyager"),
1449 .parent = TYPE_MACHINE,
1450 .class_init = voyager_class_init,
1451 };
1452
1453 static void ss_lx_class_init(ObjectClass *oc, void *data)
1454 {
1455 MachineClass *mc = MACHINE_CLASS(oc);
1456
1457 mc->desc = "Sun4m platform, SPARCstation LX";
1458 mc->init = ss_lx_init;
1459 mc->block_default_type = IF_SCSI;
1460 mc->default_boot_order = "c";
1461 }
1462
1463 static const TypeInfo ss_lx_type = {
1464 .name = MACHINE_TYPE_NAME("LX"),
1465 .parent = TYPE_MACHINE,
1466 .class_init = ss_lx_class_init,
1467 };
1468
1469 static void ss4_class_init(ObjectClass *oc, void *data)
1470 {
1471 MachineClass *mc = MACHINE_CLASS(oc);
1472
1473 mc->desc = "Sun4m platform, SPARCstation 4";
1474 mc->init = ss4_init;
1475 mc->block_default_type = IF_SCSI;
1476 mc->default_boot_order = "c";
1477 }
1478
1479 static const TypeInfo ss4_type = {
1480 .name = MACHINE_TYPE_NAME("SS-4"),
1481 .parent = TYPE_MACHINE,
1482 .class_init = ss4_class_init,
1483 };
1484
1485 static void scls_class_init(ObjectClass *oc, void *data)
1486 {
1487 MachineClass *mc = MACHINE_CLASS(oc);
1488
1489 mc->desc = "Sun4m platform, SPARCClassic";
1490 mc->init = scls_init;
1491 mc->block_default_type = IF_SCSI;
1492 mc->default_boot_order = "c";
1493 }
1494
1495 static const TypeInfo scls_type = {
1496 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1497 .parent = TYPE_MACHINE,
1498 .class_init = scls_class_init,
1499 };
1500
1501 static void sbook_class_init(ObjectClass *oc, void *data)
1502 {
1503 MachineClass *mc = MACHINE_CLASS(oc);
1504
1505 mc->desc = "Sun4m platform, SPARCbook";
1506 mc->init = sbook_init;
1507 mc->block_default_type = IF_SCSI;
1508 mc->default_boot_order = "c";
1509 }
1510
1511 static const TypeInfo sbook_type = {
1512 .name = MACHINE_TYPE_NAME("SPARCbook"),
1513 .parent = TYPE_MACHINE,
1514 .class_init = sbook_class_init,
1515 };
1516
1517 static void sun4m_register_types(void)
1518 {
1519 type_register_static(&idreg_info);
1520 type_register_static(&afx_info);
1521 type_register_static(&prom_info);
1522 type_register_static(&ram_info);
1523
1524 type_register_static(&ss5_type);
1525 type_register_static(&ss10_type);
1526 type_register_static(&ss600mp_type);
1527 type_register_static(&ss20_type);
1528 type_register_static(&voyager_type);
1529 type_register_static(&ss_lx_type);
1530 type_register_static(&ss4_type);
1531 type_register_static(&scls_type);
1532 type_register_static(&sbook_type);
1533 }
1534
1535 type_init(sun4m_register_types)
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