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Merge remote-tracking branch 'luiz/queue/qmp' into staging
[mirror_qemu.git] / hw / sparc / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/sysbus.h"
25 #include "qemu/timer.h"
26 #include "hw/sparc/sun4m.h"
27 #include "hw/timer/m48t59.h"
28 #include "hw/sparc/sparc32_dma.h"
29 #include "hw/block/fdc.h"
30 #include "sysemu/sysemu.h"
31 #include "net/net.h"
32 #include "hw/boards.h"
33 #include "hw/sparc/firmware_abi.h"
34 #include "hw/scsi/esp.h"
35 #include "hw/i386/pc.h"
36 #include "hw/isa/isa.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/char/escc.h"
39 #include "hw/empty_slot.h"
40 #include "hw/loader.h"
41 #include "elf.h"
42 #include "sysemu/blockdev.h"
43 #include "trace.h"
44
45 /*
46 * Sun4m architecture was used in the following machines:
47 *
48 * SPARCserver 6xxMP/xx
49 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
50 * SPARCclassic X (4/10)
51 * SPARCstation LX/ZX (4/30)
52 * SPARCstation Voyager
53 * SPARCstation 10/xx, SPARCserver 10/xx
54 * SPARCstation 5, SPARCserver 5
55 * SPARCstation 20/xx, SPARCserver 20
56 * SPARCstation 4
57 *
58 * Sun4d architecture was used in the following machines:
59 *
60 * SPARCcenter 2000
61 * SPARCserver 1000
62 *
63 * Sun4c architecture was used in the following machines:
64 * SPARCstation 1/1+, SPARCserver 1/1+
65 * SPARCstation SLC
66 * SPARCstation IPC
67 * SPARCstation ELC
68 * SPARCstation IPX
69 *
70 * See for example: http://www.sunhelp.org/faq/sunref1.html
71 */
72
73 #define KERNEL_LOAD_ADDR 0x00004000
74 #define CMDLINE_ADDR 0x007ff000
75 #define INITRD_LOAD_ADDR 0x00800000
76 #define PROM_SIZE_MAX (1024 * 1024)
77 #define PROM_VADDR 0xffd00000
78 #define PROM_FILENAME "openbios-sparc32"
79 #define CFG_ADDR 0xd00000510ULL
80 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
81
82 #define MAX_CPUS 16
83 #define MAX_PILS 16
84 #define MAX_VSIMMS 4
85
86 #define ESCC_CLOCK 4915200
87
88 struct sun4m_hwdef {
89 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
90 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
91 hwaddr serial_base, fd_base;
92 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
93 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
94 hwaddr bpp_base, dbri_base, sx_base;
95 struct {
96 hwaddr reg_base, vram_base;
97 } vsimm[MAX_VSIMMS];
98 hwaddr ecc_base;
99 uint64_t max_mem;
100 const char * const default_cpu_model;
101 uint32_t ecc_version;
102 uint32_t iommu_version;
103 uint16_t machine_id;
104 uint8_t nvram_machine_id;
105 };
106
107 #define MAX_IOUNITS 5
108
109 struct sun4d_hwdef {
110 hwaddr iounit_bases[MAX_IOUNITS], slavio_base;
111 hwaddr counter_base, nvram_base, ms_kb_base;
112 hwaddr serial_base;
113 hwaddr espdma_base, esp_base;
114 hwaddr ledma_base, le_base;
115 hwaddr tcx_base;
116 hwaddr sbi_base;
117 uint64_t max_mem;
118 const char * const default_cpu_model;
119 uint32_t iounit_version;
120 uint16_t machine_id;
121 uint8_t nvram_machine_id;
122 };
123
124 struct sun4c_hwdef {
125 hwaddr iommu_base, slavio_base;
126 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
127 hwaddr serial_base, fd_base;
128 hwaddr idreg_base, dma_base, esp_base, le_base;
129 hwaddr tcx_base, aux1_base;
130 uint64_t max_mem;
131 const char * const default_cpu_model;
132 uint32_t iommu_version;
133 uint16_t machine_id;
134 uint8_t nvram_machine_id;
135 };
136
137 int DMA_get_channel_mode (int nchan)
138 {
139 return 0;
140 }
141 int DMA_read_memory (int nchan, void *buf, int pos, int size)
142 {
143 return 0;
144 }
145 int DMA_write_memory (int nchan, void *buf, int pos, int size)
146 {
147 return 0;
148 }
149 void DMA_hold_DREQ (int nchan) {}
150 void DMA_release_DREQ (int nchan) {}
151 void DMA_schedule(int nchan) {}
152
153 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
154 {
155 }
156
157 void DMA_register_channel (int nchan,
158 DMA_transfer_handler transfer_handler,
159 void *opaque)
160 {
161 }
162
163 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
164 {
165 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
166 return 0;
167 }
168
169 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
170 const char *cmdline, const char *boot_devices,
171 ram_addr_t RAM_size, uint32_t kernel_size,
172 int width, int height, int depth,
173 int nvram_machine_id, const char *arch)
174 {
175 unsigned int i;
176 uint32_t start, end;
177 uint8_t image[0x1ff0];
178 struct OpenBIOS_nvpart_v1 *part_header;
179
180 memset(image, '\0', sizeof(image));
181
182 start = 0;
183
184 // OpenBIOS nvram variables
185 // Variable partition
186 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
187 part_header->signature = OPENBIOS_PART_SYSTEM;
188 pstrcpy(part_header->name, sizeof(part_header->name), "system");
189
190 end = start + sizeof(struct OpenBIOS_nvpart_v1);
191 for (i = 0; i < nb_prom_envs; i++)
192 end = OpenBIOS_set_var(image, end, prom_envs[i]);
193
194 // End marker
195 image[end++] = '\0';
196
197 end = start + ((end - start + 15) & ~15);
198 OpenBIOS_finish_partition(part_header, end - start);
199
200 // free partition
201 start = end;
202 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
203 part_header->signature = OPENBIOS_PART_FREE;
204 pstrcpy(part_header->name, sizeof(part_header->name), "free");
205
206 end = 0x1fd0;
207 OpenBIOS_finish_partition(part_header, end - start);
208
209 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
210 nvram_machine_id);
211
212 for (i = 0; i < sizeof(image); i++)
213 m48t59_write(nvram, i, image[i]);
214 }
215
216 static DeviceState *slavio_intctl;
217
218 void sun4m_pic_info(Monitor *mon, const QDict *qdict)
219 {
220 if (slavio_intctl)
221 slavio_pic_info(mon, slavio_intctl);
222 }
223
224 void sun4m_irq_info(Monitor *mon, const QDict *qdict)
225 {
226 if (slavio_intctl)
227 slavio_irq_info(mon, slavio_intctl);
228 }
229
230 void cpu_check_irqs(CPUSPARCState *env)
231 {
232 CPUState *cs;
233
234 if (env->pil_in && (env->interrupt_index == 0 ||
235 (env->interrupt_index & ~15) == TT_EXTINT)) {
236 unsigned int i;
237
238 for (i = 15; i > 0; i--) {
239 if (env->pil_in & (1 << i)) {
240 int old_interrupt = env->interrupt_index;
241
242 env->interrupt_index = TT_EXTINT | i;
243 if (old_interrupt != env->interrupt_index) {
244 cs = CPU(sparc_env_get_cpu(env));
245 trace_sun4m_cpu_interrupt(i);
246 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
247 }
248 break;
249 }
250 }
251 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
252 cs = CPU(sparc_env_get_cpu(env));
253 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
254 env->interrupt_index = 0;
255 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
256 }
257 }
258
259 static void cpu_kick_irq(SPARCCPU *cpu)
260 {
261 CPUSPARCState *env = &cpu->env;
262 CPUState *cs = CPU(cpu);
263
264 cs->halted = 0;
265 cpu_check_irqs(env);
266 qemu_cpu_kick(cs);
267 }
268
269 static void cpu_set_irq(void *opaque, int irq, int level)
270 {
271 SPARCCPU *cpu = opaque;
272 CPUSPARCState *env = &cpu->env;
273
274 if (level) {
275 trace_sun4m_cpu_set_irq_raise(irq);
276 env->pil_in |= 1 << irq;
277 cpu_kick_irq(cpu);
278 } else {
279 trace_sun4m_cpu_set_irq_lower(irq);
280 env->pil_in &= ~(1 << irq);
281 cpu_check_irqs(env);
282 }
283 }
284
285 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
286 {
287 }
288
289 static void main_cpu_reset(void *opaque)
290 {
291 SPARCCPU *cpu = opaque;
292 CPUState *cs = CPU(cpu);
293
294 cpu_reset(cs);
295 cs->halted = 0;
296 }
297
298 static void secondary_cpu_reset(void *opaque)
299 {
300 SPARCCPU *cpu = opaque;
301 CPUState *cs = CPU(cpu);
302
303 cpu_reset(cs);
304 cs->halted = 1;
305 }
306
307 static void cpu_halt_signal(void *opaque, int irq, int level)
308 {
309 if (level && cpu_single_env) {
310 cpu_interrupt(CPU(sparc_env_get_cpu(cpu_single_env)),
311 CPU_INTERRUPT_HALT);
312 }
313 }
314
315 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
316 {
317 return addr - 0xf0000000ULL;
318 }
319
320 static unsigned long sun4m_load_kernel(const char *kernel_filename,
321 const char *initrd_filename,
322 ram_addr_t RAM_size)
323 {
324 int linux_boot;
325 unsigned int i;
326 long initrd_size, kernel_size;
327 uint8_t *ptr;
328
329 linux_boot = (kernel_filename != NULL);
330
331 kernel_size = 0;
332 if (linux_boot) {
333 int bswap_needed;
334
335 #ifdef BSWAP_NEEDED
336 bswap_needed = 1;
337 #else
338 bswap_needed = 0;
339 #endif
340 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
341 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
342 if (kernel_size < 0)
343 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
344 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
345 TARGET_PAGE_SIZE);
346 if (kernel_size < 0)
347 kernel_size = load_image_targphys(kernel_filename,
348 KERNEL_LOAD_ADDR,
349 RAM_size - KERNEL_LOAD_ADDR);
350 if (kernel_size < 0) {
351 fprintf(stderr, "qemu: could not load kernel '%s'\n",
352 kernel_filename);
353 exit(1);
354 }
355
356 /* load initrd */
357 initrd_size = 0;
358 if (initrd_filename) {
359 initrd_size = load_image_targphys(initrd_filename,
360 INITRD_LOAD_ADDR,
361 RAM_size - INITRD_LOAD_ADDR);
362 if (initrd_size < 0) {
363 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
364 initrd_filename);
365 exit(1);
366 }
367 }
368 if (initrd_size > 0) {
369 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
370 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
371 if (ldl_p(ptr) == 0x48647253) { // HdrS
372 stl_p(ptr + 16, INITRD_LOAD_ADDR);
373 stl_p(ptr + 20, initrd_size);
374 break;
375 }
376 }
377 }
378 }
379 return kernel_size;
380 }
381
382 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
383 {
384 DeviceState *dev;
385 SysBusDevice *s;
386
387 dev = qdev_create(NULL, "iommu");
388 qdev_prop_set_uint32(dev, "version", version);
389 qdev_init_nofail(dev);
390 s = SYS_BUS_DEVICE(dev);
391 sysbus_connect_irq(s, 0, irq);
392 sysbus_mmio_map(s, 0, addr);
393
394 return s;
395 }
396
397 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
398 void *iommu, qemu_irq *dev_irq, int is_ledma)
399 {
400 DeviceState *dev;
401 SysBusDevice *s;
402
403 dev = qdev_create(NULL, "sparc32_dma");
404 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
405 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
406 qdev_init_nofail(dev);
407 s = SYS_BUS_DEVICE(dev);
408 sysbus_connect_irq(s, 0, parent_irq);
409 *dev_irq = qdev_get_gpio_in(dev, 0);
410 sysbus_mmio_map(s, 0, daddr);
411
412 return s;
413 }
414
415 static void lance_init(NICInfo *nd, hwaddr leaddr,
416 void *dma_opaque, qemu_irq irq)
417 {
418 DeviceState *dev;
419 SysBusDevice *s;
420 qemu_irq reset;
421
422 qemu_check_nic_model(&nd_table[0], "lance");
423
424 dev = qdev_create(NULL, "lance");
425 qdev_set_nic_properties(dev, nd);
426 qdev_prop_set_ptr(dev, "dma", dma_opaque);
427 qdev_init_nofail(dev);
428 s = SYS_BUS_DEVICE(dev);
429 sysbus_mmio_map(s, 0, leaddr);
430 sysbus_connect_irq(s, 0, irq);
431 reset = qdev_get_gpio_in(dev, 0);
432 qdev_connect_gpio_out(dma_opaque, 0, reset);
433 }
434
435 static DeviceState *slavio_intctl_init(hwaddr addr,
436 hwaddr addrg,
437 qemu_irq **parent_irq)
438 {
439 DeviceState *dev;
440 SysBusDevice *s;
441 unsigned int i, j;
442
443 dev = qdev_create(NULL, "slavio_intctl");
444 qdev_init_nofail(dev);
445
446 s = SYS_BUS_DEVICE(dev);
447
448 for (i = 0; i < MAX_CPUS; i++) {
449 for (j = 0; j < MAX_PILS; j++) {
450 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
451 }
452 }
453 sysbus_mmio_map(s, 0, addrg);
454 for (i = 0; i < MAX_CPUS; i++) {
455 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
456 }
457
458 return dev;
459 }
460
461 #define SYS_TIMER_OFFSET 0x10000ULL
462 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
463
464 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
465 qemu_irq *cpu_irqs, unsigned int num_cpus)
466 {
467 DeviceState *dev;
468 SysBusDevice *s;
469 unsigned int i;
470
471 dev = qdev_create(NULL, "slavio_timer");
472 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
473 qdev_init_nofail(dev);
474 s = SYS_BUS_DEVICE(dev);
475 sysbus_connect_irq(s, 0, master_irq);
476 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
477
478 for (i = 0; i < MAX_CPUS; i++) {
479 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
480 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
481 }
482 }
483
484 static qemu_irq slavio_system_powerdown;
485
486 static void slavio_powerdown_req(Notifier *n, void *opaque)
487 {
488 qemu_irq_raise(slavio_system_powerdown);
489 }
490
491 static Notifier slavio_system_powerdown_notifier = {
492 .notify = slavio_powerdown_req
493 };
494
495 #define MISC_LEDS 0x01600000
496 #define MISC_CFG 0x01800000
497 #define MISC_DIAG 0x01a00000
498 #define MISC_MDM 0x01b00000
499 #define MISC_SYS 0x01f00000
500
501 static void slavio_misc_init(hwaddr base,
502 hwaddr aux1_base,
503 hwaddr aux2_base, qemu_irq irq,
504 qemu_irq fdc_tc)
505 {
506 DeviceState *dev;
507 SysBusDevice *s;
508
509 dev = qdev_create(NULL, "slavio_misc");
510 qdev_init_nofail(dev);
511 s = SYS_BUS_DEVICE(dev);
512 if (base) {
513 /* 8 bit registers */
514 /* Slavio control */
515 sysbus_mmio_map(s, 0, base + MISC_CFG);
516 /* Diagnostics */
517 sysbus_mmio_map(s, 1, base + MISC_DIAG);
518 /* Modem control */
519 sysbus_mmio_map(s, 2, base + MISC_MDM);
520 /* 16 bit registers */
521 /* ss600mp diag LEDs */
522 sysbus_mmio_map(s, 3, base + MISC_LEDS);
523 /* 32 bit registers */
524 /* System control */
525 sysbus_mmio_map(s, 4, base + MISC_SYS);
526 }
527 if (aux1_base) {
528 /* AUX 1 (Misc System Functions) */
529 sysbus_mmio_map(s, 5, aux1_base);
530 }
531 if (aux2_base) {
532 /* AUX 2 (Software Powerdown Control) */
533 sysbus_mmio_map(s, 6, aux2_base);
534 }
535 sysbus_connect_irq(s, 0, irq);
536 sysbus_connect_irq(s, 1, fdc_tc);
537 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
538 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
539 }
540
541 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
542 {
543 DeviceState *dev;
544 SysBusDevice *s;
545
546 dev = qdev_create(NULL, "eccmemctl");
547 qdev_prop_set_uint32(dev, "version", version);
548 qdev_init_nofail(dev);
549 s = SYS_BUS_DEVICE(dev);
550 sysbus_connect_irq(s, 0, irq);
551 sysbus_mmio_map(s, 0, base);
552 if (version == 0) { // SS-600MP only
553 sysbus_mmio_map(s, 1, base + 0x1000);
554 }
555 }
556
557 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
558 {
559 DeviceState *dev;
560 SysBusDevice *s;
561
562 dev = qdev_create(NULL, "apc");
563 qdev_init_nofail(dev);
564 s = SYS_BUS_DEVICE(dev);
565 /* Power management (APC) XXX: not a Slavio device */
566 sysbus_mmio_map(s, 0, power_base);
567 sysbus_connect_irq(s, 0, cpu_halt);
568 }
569
570 static void tcx_init(hwaddr addr, int vram_size, int width,
571 int height, int depth)
572 {
573 DeviceState *dev;
574 SysBusDevice *s;
575
576 dev = qdev_create(NULL, "SUNW,tcx");
577 qdev_prop_set_uint32(dev, "vram_size", vram_size);
578 qdev_prop_set_uint16(dev, "width", width);
579 qdev_prop_set_uint16(dev, "height", height);
580 qdev_prop_set_uint16(dev, "depth", depth);
581 qdev_init_nofail(dev);
582 s = SYS_BUS_DEVICE(dev);
583 /* 8-bit plane */
584 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
585 /* DAC */
586 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
587 /* TEC (dummy) */
588 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
589 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
590 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
591 if (depth == 24) {
592 /* 24-bit plane */
593 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
594 /* Control plane */
595 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
596 } else {
597 /* THC 8 bit (dummy) */
598 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
599 }
600 }
601
602 /* NCR89C100/MACIO Internal ID register */
603 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
604
605 static void idreg_init(hwaddr addr)
606 {
607 DeviceState *dev;
608 SysBusDevice *s;
609
610 dev = qdev_create(NULL, "macio_idreg");
611 qdev_init_nofail(dev);
612 s = SYS_BUS_DEVICE(dev);
613
614 sysbus_mmio_map(s, 0, addr);
615 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
616 }
617
618 typedef struct IDRegState {
619 SysBusDevice busdev;
620 MemoryRegion mem;
621 } IDRegState;
622
623 static int idreg_init1(SysBusDevice *dev)
624 {
625 IDRegState *s = FROM_SYSBUS(IDRegState, dev);
626
627 memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
628 vmstate_register_ram_global(&s->mem);
629 memory_region_set_readonly(&s->mem, true);
630 sysbus_init_mmio(dev, &s->mem);
631 return 0;
632 }
633
634 static void idreg_class_init(ObjectClass *klass, void *data)
635 {
636 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
637
638 k->init = idreg_init1;
639 }
640
641 static const TypeInfo idreg_info = {
642 .name = "macio_idreg",
643 .parent = TYPE_SYS_BUS_DEVICE,
644 .instance_size = sizeof(IDRegState),
645 .class_init = idreg_class_init,
646 };
647
648 typedef struct AFXState {
649 SysBusDevice busdev;
650 MemoryRegion mem;
651 } AFXState;
652
653 /* SS-5 TCX AFX register */
654 static void afx_init(hwaddr addr)
655 {
656 DeviceState *dev;
657 SysBusDevice *s;
658
659 dev = qdev_create(NULL, "tcx_afx");
660 qdev_init_nofail(dev);
661 s = SYS_BUS_DEVICE(dev);
662
663 sysbus_mmio_map(s, 0, addr);
664 }
665
666 static int afx_init1(SysBusDevice *dev)
667 {
668 AFXState *s = FROM_SYSBUS(AFXState, dev);
669
670 memory_region_init_ram(&s->mem, "sun4m.afx", 4);
671 vmstate_register_ram_global(&s->mem);
672 sysbus_init_mmio(dev, &s->mem);
673 return 0;
674 }
675
676 static void afx_class_init(ObjectClass *klass, void *data)
677 {
678 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
679
680 k->init = afx_init1;
681 }
682
683 static const TypeInfo afx_info = {
684 .name = "tcx_afx",
685 .parent = TYPE_SYS_BUS_DEVICE,
686 .instance_size = sizeof(AFXState),
687 .class_init = afx_class_init,
688 };
689
690 typedef struct PROMState {
691 SysBusDevice busdev;
692 MemoryRegion prom;
693 } PROMState;
694
695 /* Boot PROM (OpenBIOS) */
696 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
697 {
698 hwaddr *base_addr = (hwaddr *)opaque;
699 return addr + *base_addr - PROM_VADDR;
700 }
701
702 static void prom_init(hwaddr addr, const char *bios_name)
703 {
704 DeviceState *dev;
705 SysBusDevice *s;
706 char *filename;
707 int ret;
708
709 dev = qdev_create(NULL, "openprom");
710 qdev_init_nofail(dev);
711 s = SYS_BUS_DEVICE(dev);
712
713 sysbus_mmio_map(s, 0, addr);
714
715 /* load boot prom */
716 if (bios_name == NULL) {
717 bios_name = PROM_FILENAME;
718 }
719 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
720 if (filename) {
721 ret = load_elf(filename, translate_prom_address, &addr, NULL,
722 NULL, NULL, 1, ELF_MACHINE, 0);
723 if (ret < 0 || ret > PROM_SIZE_MAX) {
724 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
725 }
726 g_free(filename);
727 } else {
728 ret = -1;
729 }
730 if (ret < 0 || ret > PROM_SIZE_MAX) {
731 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
732 exit(1);
733 }
734 }
735
736 static int prom_init1(SysBusDevice *dev)
737 {
738 PROMState *s = FROM_SYSBUS(PROMState, dev);
739
740 memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
741 vmstate_register_ram_global(&s->prom);
742 memory_region_set_readonly(&s->prom, true);
743 sysbus_init_mmio(dev, &s->prom);
744 return 0;
745 }
746
747 static Property prom_properties[] = {
748 {/* end of property list */},
749 };
750
751 static void prom_class_init(ObjectClass *klass, void *data)
752 {
753 DeviceClass *dc = DEVICE_CLASS(klass);
754 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
755
756 k->init = prom_init1;
757 dc->props = prom_properties;
758 }
759
760 static const TypeInfo prom_info = {
761 .name = "openprom",
762 .parent = TYPE_SYS_BUS_DEVICE,
763 .instance_size = sizeof(PROMState),
764 .class_init = prom_class_init,
765 };
766
767 typedef struct RamDevice
768 {
769 SysBusDevice busdev;
770 MemoryRegion ram;
771 uint64_t size;
772 } RamDevice;
773
774 /* System RAM */
775 static int ram_init1(SysBusDevice *dev)
776 {
777 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
778
779 memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
780 vmstate_register_ram_global(&d->ram);
781 sysbus_init_mmio(dev, &d->ram);
782 return 0;
783 }
784
785 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
786 uint64_t max_mem)
787 {
788 DeviceState *dev;
789 SysBusDevice *s;
790 RamDevice *d;
791
792 /* allocate RAM */
793 if ((uint64_t)RAM_size > max_mem) {
794 fprintf(stderr,
795 "qemu: Too much memory for this machine: %d, maximum %d\n",
796 (unsigned int)(RAM_size / (1024 * 1024)),
797 (unsigned int)(max_mem / (1024 * 1024)));
798 exit(1);
799 }
800 dev = qdev_create(NULL, "memory");
801 s = SYS_BUS_DEVICE(dev);
802
803 d = FROM_SYSBUS(RamDevice, s);
804 d->size = RAM_size;
805 qdev_init_nofail(dev);
806
807 sysbus_mmio_map(s, 0, addr);
808 }
809
810 static Property ram_properties[] = {
811 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
812 DEFINE_PROP_END_OF_LIST(),
813 };
814
815 static void ram_class_init(ObjectClass *klass, void *data)
816 {
817 DeviceClass *dc = DEVICE_CLASS(klass);
818 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
819
820 k->init = ram_init1;
821 dc->props = ram_properties;
822 }
823
824 static const TypeInfo ram_info = {
825 .name = "memory",
826 .parent = TYPE_SYS_BUS_DEVICE,
827 .instance_size = sizeof(RamDevice),
828 .class_init = ram_class_init,
829 };
830
831 static void cpu_devinit(const char *cpu_model, unsigned int id,
832 uint64_t prom_addr, qemu_irq **cpu_irqs)
833 {
834 CPUState *cs;
835 SPARCCPU *cpu;
836 CPUSPARCState *env;
837
838 cpu = cpu_sparc_init(cpu_model);
839 if (cpu == NULL) {
840 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
841 exit(1);
842 }
843 env = &cpu->env;
844
845 cpu_sparc_set_id(env, id);
846 if (id == 0) {
847 qemu_register_reset(main_cpu_reset, cpu);
848 } else {
849 qemu_register_reset(secondary_cpu_reset, cpu);
850 cs = CPU(cpu);
851 cs->halted = 1;
852 }
853 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
854 env->prom_addr = prom_addr;
855 }
856
857 static void dummy_fdc_tc(void *opaque, int irq, int level)
858 {
859 }
860
861 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
862 const char *boot_device,
863 const char *kernel_filename,
864 const char *kernel_cmdline,
865 const char *initrd_filename, const char *cpu_model)
866 {
867 unsigned int i;
868 void *iommu, *espdma, *ledma, *nvram;
869 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
870 espdma_irq, ledma_irq;
871 qemu_irq esp_reset, dma_enable;
872 qemu_irq fdc_tc;
873 qemu_irq *cpu_halt;
874 unsigned long kernel_size;
875 DriveInfo *fd[MAX_FD];
876 void *fw_cfg;
877 unsigned int num_vsimms;
878
879 /* init CPUs */
880 if (!cpu_model)
881 cpu_model = hwdef->default_cpu_model;
882
883 for(i = 0; i < smp_cpus; i++) {
884 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
885 }
886
887 for (i = smp_cpus; i < MAX_CPUS; i++)
888 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
889
890
891 /* set up devices */
892 ram_init(0, RAM_size, hwdef->max_mem);
893 /* models without ECC don't trap when missing ram is accessed */
894 if (!hwdef->ecc_base) {
895 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
896 }
897
898 prom_init(hwdef->slavio_base, bios_name);
899
900 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
901 hwdef->intctl_base + 0x10000ULL,
902 cpu_irqs);
903
904 for (i = 0; i < 32; i++) {
905 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
906 }
907 for (i = 0; i < MAX_CPUS; i++) {
908 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
909 }
910
911 if (hwdef->idreg_base) {
912 idreg_init(hwdef->idreg_base);
913 }
914
915 if (hwdef->afx_base) {
916 afx_init(hwdef->afx_base);
917 }
918
919 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
920 slavio_irq[30]);
921
922 if (hwdef->iommu_pad_base) {
923 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
924 Software shouldn't use aliased addresses, neither should it crash
925 when does. Using empty_slot instead of aliasing can help with
926 debugging such accesses */
927 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
928 }
929
930 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
931 iommu, &espdma_irq, 0);
932
933 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
934 slavio_irq[16], iommu, &ledma_irq, 1);
935
936 if (graphic_depth != 8 && graphic_depth != 24) {
937 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
938 exit (1);
939 }
940 num_vsimms = 0;
941 if (num_vsimms == 0) {
942 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
943 graphic_depth);
944 }
945
946 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
947 /* vsimm registers probed by OBP */
948 if (hwdef->vsimm[i].reg_base) {
949 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
950 }
951 }
952
953 if (hwdef->sx_base) {
954 empty_slot_init(hwdef->sx_base, 0x2000);
955 }
956
957 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
958
959 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
960
961 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
962
963 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
964 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
965 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
966 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
967 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
968 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
969
970 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
971 if (hwdef->apc_base) {
972 apc_init(hwdef->apc_base, cpu_halt[0]);
973 }
974
975 if (hwdef->fd_base) {
976 /* there is zero or one floppy drive */
977 memset(fd, 0, sizeof(fd));
978 fd[0] = drive_get(IF_FLOPPY, 0, 0);
979 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
980 &fdc_tc);
981 } else {
982 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
983 }
984
985 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
986 slavio_irq[30], fdc_tc);
987
988 if (drive_get_max_bus(IF_SCSI) > 0) {
989 fprintf(stderr, "qemu: too many SCSI bus\n");
990 exit(1);
991 }
992
993 esp_init(hwdef->esp_base, 2,
994 espdma_memory_read, espdma_memory_write,
995 espdma, espdma_irq, &esp_reset, &dma_enable);
996
997 qdev_connect_gpio_out(espdma, 0, esp_reset);
998 qdev_connect_gpio_out(espdma, 1, dma_enable);
999
1000 if (hwdef->cs_base) {
1001 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1002 slavio_irq[5]);
1003 }
1004
1005 if (hwdef->dbri_base) {
1006 /* ISDN chip with attached CS4215 audio codec */
1007 /* prom space */
1008 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1009 /* reg space */
1010 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1011 }
1012
1013 if (hwdef->bpp_base) {
1014 /* parallel port */
1015 empty_slot_init(hwdef->bpp_base, 0x20);
1016 }
1017
1018 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1019 RAM_size);
1020
1021 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1022 boot_device, RAM_size, kernel_size, graphic_width,
1023 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1024 "Sun4m");
1025
1026 if (hwdef->ecc_base)
1027 ecc_init(hwdef->ecc_base, slavio_irq[28],
1028 hwdef->ecc_version);
1029
1030 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1031 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1032 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1033 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1034 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1035 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1036 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1037 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1038 if (kernel_cmdline) {
1039 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1040 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1041 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1042 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1043 strlen(kernel_cmdline) + 1);
1044 } else {
1045 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1046 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1047 }
1048 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1049 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1050 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1051 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1052 }
1053
1054 enum {
1055 ss2_id = 0,
1056 ss5_id = 32,
1057 vger_id,
1058 lx_id,
1059 ss4_id,
1060 scls_id,
1061 sbook_id,
1062 ss10_id = 64,
1063 ss20_id,
1064 ss600mp_id,
1065 ss1000_id = 96,
1066 ss2000_id,
1067 };
1068
1069 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1070 /* SS-5 */
1071 {
1072 .iommu_base = 0x10000000,
1073 .iommu_pad_base = 0x10004000,
1074 .iommu_pad_len = 0x0fffb000,
1075 .tcx_base = 0x50000000,
1076 .cs_base = 0x6c000000,
1077 .slavio_base = 0x70000000,
1078 .ms_kb_base = 0x71000000,
1079 .serial_base = 0x71100000,
1080 .nvram_base = 0x71200000,
1081 .fd_base = 0x71400000,
1082 .counter_base = 0x71d00000,
1083 .intctl_base = 0x71e00000,
1084 .idreg_base = 0x78000000,
1085 .dma_base = 0x78400000,
1086 .esp_base = 0x78800000,
1087 .le_base = 0x78c00000,
1088 .apc_base = 0x6a000000,
1089 .afx_base = 0x6e000000,
1090 .aux1_base = 0x71900000,
1091 .aux2_base = 0x71910000,
1092 .nvram_machine_id = 0x80,
1093 .machine_id = ss5_id,
1094 .iommu_version = 0x05000000,
1095 .max_mem = 0x10000000,
1096 .default_cpu_model = "Fujitsu MB86904",
1097 },
1098 /* SS-10 */
1099 {
1100 .iommu_base = 0xfe0000000ULL,
1101 .tcx_base = 0xe20000000ULL,
1102 .slavio_base = 0xff0000000ULL,
1103 .ms_kb_base = 0xff1000000ULL,
1104 .serial_base = 0xff1100000ULL,
1105 .nvram_base = 0xff1200000ULL,
1106 .fd_base = 0xff1700000ULL,
1107 .counter_base = 0xff1300000ULL,
1108 .intctl_base = 0xff1400000ULL,
1109 .idreg_base = 0xef0000000ULL,
1110 .dma_base = 0xef0400000ULL,
1111 .esp_base = 0xef0800000ULL,
1112 .le_base = 0xef0c00000ULL,
1113 .apc_base = 0xefa000000ULL, // XXX should not exist
1114 .aux1_base = 0xff1800000ULL,
1115 .aux2_base = 0xff1a01000ULL,
1116 .ecc_base = 0xf00000000ULL,
1117 .ecc_version = 0x10000000, // version 0, implementation 1
1118 .nvram_machine_id = 0x72,
1119 .machine_id = ss10_id,
1120 .iommu_version = 0x03000000,
1121 .max_mem = 0xf00000000ULL,
1122 .default_cpu_model = "TI SuperSparc II",
1123 },
1124 /* SS-600MP */
1125 {
1126 .iommu_base = 0xfe0000000ULL,
1127 .tcx_base = 0xe20000000ULL,
1128 .slavio_base = 0xff0000000ULL,
1129 .ms_kb_base = 0xff1000000ULL,
1130 .serial_base = 0xff1100000ULL,
1131 .nvram_base = 0xff1200000ULL,
1132 .counter_base = 0xff1300000ULL,
1133 .intctl_base = 0xff1400000ULL,
1134 .dma_base = 0xef0081000ULL,
1135 .esp_base = 0xef0080000ULL,
1136 .le_base = 0xef0060000ULL,
1137 .apc_base = 0xefa000000ULL, // XXX should not exist
1138 .aux1_base = 0xff1800000ULL,
1139 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1140 .ecc_base = 0xf00000000ULL,
1141 .ecc_version = 0x00000000, // version 0, implementation 0
1142 .nvram_machine_id = 0x71,
1143 .machine_id = ss600mp_id,
1144 .iommu_version = 0x01000000,
1145 .max_mem = 0xf00000000ULL,
1146 .default_cpu_model = "TI SuperSparc II",
1147 },
1148 /* SS-20 */
1149 {
1150 .iommu_base = 0xfe0000000ULL,
1151 .tcx_base = 0xe20000000ULL,
1152 .slavio_base = 0xff0000000ULL,
1153 .ms_kb_base = 0xff1000000ULL,
1154 .serial_base = 0xff1100000ULL,
1155 .nvram_base = 0xff1200000ULL,
1156 .fd_base = 0xff1700000ULL,
1157 .counter_base = 0xff1300000ULL,
1158 .intctl_base = 0xff1400000ULL,
1159 .idreg_base = 0xef0000000ULL,
1160 .dma_base = 0xef0400000ULL,
1161 .esp_base = 0xef0800000ULL,
1162 .le_base = 0xef0c00000ULL,
1163 .bpp_base = 0xef4800000ULL,
1164 .apc_base = 0xefa000000ULL, // XXX should not exist
1165 .aux1_base = 0xff1800000ULL,
1166 .aux2_base = 0xff1a01000ULL,
1167 .dbri_base = 0xee0000000ULL,
1168 .sx_base = 0xf80000000ULL,
1169 .vsimm = {
1170 {
1171 .reg_base = 0x9c000000ULL,
1172 .vram_base = 0xfc000000ULL
1173 }, {
1174 .reg_base = 0x90000000ULL,
1175 .vram_base = 0xf0000000ULL
1176 }, {
1177 .reg_base = 0x94000000ULL
1178 }, {
1179 .reg_base = 0x98000000ULL
1180 }
1181 },
1182 .ecc_base = 0xf00000000ULL,
1183 .ecc_version = 0x20000000, // version 0, implementation 2
1184 .nvram_machine_id = 0x72,
1185 .machine_id = ss20_id,
1186 .iommu_version = 0x13000000,
1187 .max_mem = 0xf00000000ULL,
1188 .default_cpu_model = "TI SuperSparc II",
1189 },
1190 /* Voyager */
1191 {
1192 .iommu_base = 0x10000000,
1193 .tcx_base = 0x50000000,
1194 .slavio_base = 0x70000000,
1195 .ms_kb_base = 0x71000000,
1196 .serial_base = 0x71100000,
1197 .nvram_base = 0x71200000,
1198 .fd_base = 0x71400000,
1199 .counter_base = 0x71d00000,
1200 .intctl_base = 0x71e00000,
1201 .idreg_base = 0x78000000,
1202 .dma_base = 0x78400000,
1203 .esp_base = 0x78800000,
1204 .le_base = 0x78c00000,
1205 .apc_base = 0x71300000, // pmc
1206 .aux1_base = 0x71900000,
1207 .aux2_base = 0x71910000,
1208 .nvram_machine_id = 0x80,
1209 .machine_id = vger_id,
1210 .iommu_version = 0x05000000,
1211 .max_mem = 0x10000000,
1212 .default_cpu_model = "Fujitsu MB86904",
1213 },
1214 /* LX */
1215 {
1216 .iommu_base = 0x10000000,
1217 .iommu_pad_base = 0x10004000,
1218 .iommu_pad_len = 0x0fffb000,
1219 .tcx_base = 0x50000000,
1220 .slavio_base = 0x70000000,
1221 .ms_kb_base = 0x71000000,
1222 .serial_base = 0x71100000,
1223 .nvram_base = 0x71200000,
1224 .fd_base = 0x71400000,
1225 .counter_base = 0x71d00000,
1226 .intctl_base = 0x71e00000,
1227 .idreg_base = 0x78000000,
1228 .dma_base = 0x78400000,
1229 .esp_base = 0x78800000,
1230 .le_base = 0x78c00000,
1231 .aux1_base = 0x71900000,
1232 .aux2_base = 0x71910000,
1233 .nvram_machine_id = 0x80,
1234 .machine_id = lx_id,
1235 .iommu_version = 0x04000000,
1236 .max_mem = 0x10000000,
1237 .default_cpu_model = "TI MicroSparc I",
1238 },
1239 /* SS-4 */
1240 {
1241 .iommu_base = 0x10000000,
1242 .tcx_base = 0x50000000,
1243 .cs_base = 0x6c000000,
1244 .slavio_base = 0x70000000,
1245 .ms_kb_base = 0x71000000,
1246 .serial_base = 0x71100000,
1247 .nvram_base = 0x71200000,
1248 .fd_base = 0x71400000,
1249 .counter_base = 0x71d00000,
1250 .intctl_base = 0x71e00000,
1251 .idreg_base = 0x78000000,
1252 .dma_base = 0x78400000,
1253 .esp_base = 0x78800000,
1254 .le_base = 0x78c00000,
1255 .apc_base = 0x6a000000,
1256 .aux1_base = 0x71900000,
1257 .aux2_base = 0x71910000,
1258 .nvram_machine_id = 0x80,
1259 .machine_id = ss4_id,
1260 .iommu_version = 0x05000000,
1261 .max_mem = 0x10000000,
1262 .default_cpu_model = "Fujitsu MB86904",
1263 },
1264 /* SPARCClassic */
1265 {
1266 .iommu_base = 0x10000000,
1267 .tcx_base = 0x50000000,
1268 .slavio_base = 0x70000000,
1269 .ms_kb_base = 0x71000000,
1270 .serial_base = 0x71100000,
1271 .nvram_base = 0x71200000,
1272 .fd_base = 0x71400000,
1273 .counter_base = 0x71d00000,
1274 .intctl_base = 0x71e00000,
1275 .idreg_base = 0x78000000,
1276 .dma_base = 0x78400000,
1277 .esp_base = 0x78800000,
1278 .le_base = 0x78c00000,
1279 .apc_base = 0x6a000000,
1280 .aux1_base = 0x71900000,
1281 .aux2_base = 0x71910000,
1282 .nvram_machine_id = 0x80,
1283 .machine_id = scls_id,
1284 .iommu_version = 0x05000000,
1285 .max_mem = 0x10000000,
1286 .default_cpu_model = "TI MicroSparc I",
1287 },
1288 /* SPARCbook */
1289 {
1290 .iommu_base = 0x10000000,
1291 .tcx_base = 0x50000000, // XXX
1292 .slavio_base = 0x70000000,
1293 .ms_kb_base = 0x71000000,
1294 .serial_base = 0x71100000,
1295 .nvram_base = 0x71200000,
1296 .fd_base = 0x71400000,
1297 .counter_base = 0x71d00000,
1298 .intctl_base = 0x71e00000,
1299 .idreg_base = 0x78000000,
1300 .dma_base = 0x78400000,
1301 .esp_base = 0x78800000,
1302 .le_base = 0x78c00000,
1303 .apc_base = 0x6a000000,
1304 .aux1_base = 0x71900000,
1305 .aux2_base = 0x71910000,
1306 .nvram_machine_id = 0x80,
1307 .machine_id = sbook_id,
1308 .iommu_version = 0x05000000,
1309 .max_mem = 0x10000000,
1310 .default_cpu_model = "TI MicroSparc I",
1311 },
1312 };
1313
1314 /* SPARCstation 5 hardware initialisation */
1315 static void ss5_init(QEMUMachineInitArgs *args)
1316 {
1317 ram_addr_t RAM_size = args->ram_size;
1318 const char *cpu_model = args->cpu_model;
1319 const char *kernel_filename = args->kernel_filename;
1320 const char *kernel_cmdline = args->kernel_cmdline;
1321 const char *initrd_filename = args->initrd_filename;
1322 const char *boot_device = args->boot_device;
1323 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1324 kernel_cmdline, initrd_filename, cpu_model);
1325 }
1326
1327 /* SPARCstation 10 hardware initialisation */
1328 static void ss10_init(QEMUMachineInitArgs *args)
1329 {
1330 ram_addr_t RAM_size = args->ram_size;
1331 const char *cpu_model = args->cpu_model;
1332 const char *kernel_filename = args->kernel_filename;
1333 const char *kernel_cmdline = args->kernel_cmdline;
1334 const char *initrd_filename = args->initrd_filename;
1335 const char *boot_device = args->boot_device;
1336 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1337 kernel_cmdline, initrd_filename, cpu_model);
1338 }
1339
1340 /* SPARCserver 600MP hardware initialisation */
1341 static void ss600mp_init(QEMUMachineInitArgs *args)
1342 {
1343 ram_addr_t RAM_size = args->ram_size;
1344 const char *cpu_model = args->cpu_model;
1345 const char *kernel_filename = args->kernel_filename;
1346 const char *kernel_cmdline = args->kernel_cmdline;
1347 const char *initrd_filename = args->initrd_filename;
1348 const char *boot_device = args->boot_device;
1349 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1350 kernel_cmdline, initrd_filename, cpu_model);
1351 }
1352
1353 /* SPARCstation 20 hardware initialisation */
1354 static void ss20_init(QEMUMachineInitArgs *args)
1355 {
1356 ram_addr_t RAM_size = args->ram_size;
1357 const char *cpu_model = args->cpu_model;
1358 const char *kernel_filename = args->kernel_filename;
1359 const char *kernel_cmdline = args->kernel_cmdline;
1360 const char *initrd_filename = args->initrd_filename;
1361 const char *boot_device = args->boot_device;
1362 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1363 kernel_cmdline, initrd_filename, cpu_model);
1364 }
1365
1366 /* SPARCstation Voyager hardware initialisation */
1367 static void vger_init(QEMUMachineInitArgs *args)
1368 {
1369 ram_addr_t RAM_size = args->ram_size;
1370 const char *cpu_model = args->cpu_model;
1371 const char *kernel_filename = args->kernel_filename;
1372 const char *kernel_cmdline = args->kernel_cmdline;
1373 const char *initrd_filename = args->initrd_filename;
1374 const char *boot_device = args->boot_device;
1375 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1376 kernel_cmdline, initrd_filename, cpu_model);
1377 }
1378
1379 /* SPARCstation LX hardware initialisation */
1380 static void ss_lx_init(QEMUMachineInitArgs *args)
1381 {
1382 ram_addr_t RAM_size = args->ram_size;
1383 const char *cpu_model = args->cpu_model;
1384 const char *kernel_filename = args->kernel_filename;
1385 const char *kernel_cmdline = args->kernel_cmdline;
1386 const char *initrd_filename = args->initrd_filename;
1387 const char *boot_device = args->boot_device;
1388 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1389 kernel_cmdline, initrd_filename, cpu_model);
1390 }
1391
1392 /* SPARCstation 4 hardware initialisation */
1393 static void ss4_init(QEMUMachineInitArgs *args)
1394 {
1395 ram_addr_t RAM_size = args->ram_size;
1396 const char *cpu_model = args->cpu_model;
1397 const char *kernel_filename = args->kernel_filename;
1398 const char *kernel_cmdline = args->kernel_cmdline;
1399 const char *initrd_filename = args->initrd_filename;
1400 const char *boot_device = args->boot_device;
1401 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1402 kernel_cmdline, initrd_filename, cpu_model);
1403 }
1404
1405 /* SPARCClassic hardware initialisation */
1406 static void scls_init(QEMUMachineInitArgs *args)
1407 {
1408 ram_addr_t RAM_size = args->ram_size;
1409 const char *cpu_model = args->cpu_model;
1410 const char *kernel_filename = args->kernel_filename;
1411 const char *kernel_cmdline = args->kernel_cmdline;
1412 const char *initrd_filename = args->initrd_filename;
1413 const char *boot_device = args->boot_device;
1414 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1415 kernel_cmdline, initrd_filename, cpu_model);
1416 }
1417
1418 /* SPARCbook hardware initialisation */
1419 static void sbook_init(QEMUMachineInitArgs *args)
1420 {
1421 ram_addr_t RAM_size = args->ram_size;
1422 const char *cpu_model = args->cpu_model;
1423 const char *kernel_filename = args->kernel_filename;
1424 const char *kernel_cmdline = args->kernel_cmdline;
1425 const char *initrd_filename = args->initrd_filename;
1426 const char *boot_device = args->boot_device;
1427 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1428 kernel_cmdline, initrd_filename, cpu_model);
1429 }
1430
1431 static QEMUMachine ss5_machine = {
1432 .name = "SS-5",
1433 .desc = "Sun4m platform, SPARCstation 5",
1434 .init = ss5_init,
1435 .block_default_type = IF_SCSI,
1436 .is_default = 1,
1437 DEFAULT_MACHINE_OPTIONS,
1438 };
1439
1440 static QEMUMachine ss10_machine = {
1441 .name = "SS-10",
1442 .desc = "Sun4m platform, SPARCstation 10",
1443 .init = ss10_init,
1444 .block_default_type = IF_SCSI,
1445 .max_cpus = 4,
1446 DEFAULT_MACHINE_OPTIONS,
1447 };
1448
1449 static QEMUMachine ss600mp_machine = {
1450 .name = "SS-600MP",
1451 .desc = "Sun4m platform, SPARCserver 600MP",
1452 .init = ss600mp_init,
1453 .block_default_type = IF_SCSI,
1454 .max_cpus = 4,
1455 DEFAULT_MACHINE_OPTIONS,
1456 };
1457
1458 static QEMUMachine ss20_machine = {
1459 .name = "SS-20",
1460 .desc = "Sun4m platform, SPARCstation 20",
1461 .init = ss20_init,
1462 .block_default_type = IF_SCSI,
1463 .max_cpus = 4,
1464 DEFAULT_MACHINE_OPTIONS,
1465 };
1466
1467 static QEMUMachine voyager_machine = {
1468 .name = "Voyager",
1469 .desc = "Sun4m platform, SPARCstation Voyager",
1470 .init = vger_init,
1471 .block_default_type = IF_SCSI,
1472 DEFAULT_MACHINE_OPTIONS,
1473 };
1474
1475 static QEMUMachine ss_lx_machine = {
1476 .name = "LX",
1477 .desc = "Sun4m platform, SPARCstation LX",
1478 .init = ss_lx_init,
1479 .block_default_type = IF_SCSI,
1480 DEFAULT_MACHINE_OPTIONS,
1481 };
1482
1483 static QEMUMachine ss4_machine = {
1484 .name = "SS-4",
1485 .desc = "Sun4m platform, SPARCstation 4",
1486 .init = ss4_init,
1487 .block_default_type = IF_SCSI,
1488 DEFAULT_MACHINE_OPTIONS,
1489 };
1490
1491 static QEMUMachine scls_machine = {
1492 .name = "SPARCClassic",
1493 .desc = "Sun4m platform, SPARCClassic",
1494 .init = scls_init,
1495 .block_default_type = IF_SCSI,
1496 DEFAULT_MACHINE_OPTIONS,
1497 };
1498
1499 static QEMUMachine sbook_machine = {
1500 .name = "SPARCbook",
1501 .desc = "Sun4m platform, SPARCbook",
1502 .init = sbook_init,
1503 .block_default_type = IF_SCSI,
1504 DEFAULT_MACHINE_OPTIONS,
1505 };
1506
1507 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1508 /* SS-1000 */
1509 {
1510 .iounit_bases = {
1511 0xfe0200000ULL,
1512 0xfe1200000ULL,
1513 0xfe2200000ULL,
1514 0xfe3200000ULL,
1515 -1,
1516 },
1517 .tcx_base = 0x820000000ULL,
1518 .slavio_base = 0xf00000000ULL,
1519 .ms_kb_base = 0xf00240000ULL,
1520 .serial_base = 0xf00200000ULL,
1521 .nvram_base = 0xf00280000ULL,
1522 .counter_base = 0xf00300000ULL,
1523 .espdma_base = 0x800081000ULL,
1524 .esp_base = 0x800080000ULL,
1525 .ledma_base = 0x800040000ULL,
1526 .le_base = 0x800060000ULL,
1527 .sbi_base = 0xf02800000ULL,
1528 .nvram_machine_id = 0x80,
1529 .machine_id = ss1000_id,
1530 .iounit_version = 0x03000000,
1531 .max_mem = 0xf00000000ULL,
1532 .default_cpu_model = "TI SuperSparc II",
1533 },
1534 /* SS-2000 */
1535 {
1536 .iounit_bases = {
1537 0xfe0200000ULL,
1538 0xfe1200000ULL,
1539 0xfe2200000ULL,
1540 0xfe3200000ULL,
1541 0xfe4200000ULL,
1542 },
1543 .tcx_base = 0x820000000ULL,
1544 .slavio_base = 0xf00000000ULL,
1545 .ms_kb_base = 0xf00240000ULL,
1546 .serial_base = 0xf00200000ULL,
1547 .nvram_base = 0xf00280000ULL,
1548 .counter_base = 0xf00300000ULL,
1549 .espdma_base = 0x800081000ULL,
1550 .esp_base = 0x800080000ULL,
1551 .ledma_base = 0x800040000ULL,
1552 .le_base = 0x800060000ULL,
1553 .sbi_base = 0xf02800000ULL,
1554 .nvram_machine_id = 0x80,
1555 .machine_id = ss2000_id,
1556 .iounit_version = 0x03000000,
1557 .max_mem = 0xf00000000ULL,
1558 .default_cpu_model = "TI SuperSparc II",
1559 },
1560 };
1561
1562 static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq)
1563 {
1564 DeviceState *dev;
1565 SysBusDevice *s;
1566 unsigned int i;
1567
1568 dev = qdev_create(NULL, "sbi");
1569 qdev_init_nofail(dev);
1570
1571 s = SYS_BUS_DEVICE(dev);
1572
1573 for (i = 0; i < MAX_CPUS; i++) {
1574 sysbus_connect_irq(s, i, *parent_irq[i]);
1575 }
1576
1577 sysbus_mmio_map(s, 0, addr);
1578
1579 return dev;
1580 }
1581
1582 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1583 const char *boot_device,
1584 const char *kernel_filename,
1585 const char *kernel_cmdline,
1586 const char *initrd_filename, const char *cpu_model)
1587 {
1588 unsigned int i;
1589 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1590 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1591 espdma_irq, ledma_irq;
1592 qemu_irq esp_reset, dma_enable;
1593 unsigned long kernel_size;
1594 void *fw_cfg;
1595 DeviceState *dev;
1596
1597 /* init CPUs */
1598 if (!cpu_model)
1599 cpu_model = hwdef->default_cpu_model;
1600
1601 for(i = 0; i < smp_cpus; i++) {
1602 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1603 }
1604
1605 for (i = smp_cpus; i < MAX_CPUS; i++)
1606 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1607
1608 /* set up devices */
1609 ram_init(0, RAM_size, hwdef->max_mem);
1610
1611 prom_init(hwdef->slavio_base, bios_name);
1612
1613 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1614
1615 for (i = 0; i < 32; i++) {
1616 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1617 }
1618 for (i = 0; i < MAX_CPUS; i++) {
1619 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1620 }
1621
1622 for (i = 0; i < MAX_IOUNITS; i++)
1623 if (hwdef->iounit_bases[i] != (hwaddr)-1)
1624 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1625 hwdef->iounit_version,
1626 sbi_irq[0]);
1627
1628 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1629 iounits[0], &espdma_irq, 0);
1630
1631 /* should be lebuffer instead */
1632 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1633 iounits[0], &ledma_irq, 0);
1634
1635 if (graphic_depth != 8 && graphic_depth != 24) {
1636 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1637 exit (1);
1638 }
1639 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1640 graphic_depth);
1641
1642 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1643
1644 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1645
1646 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1647
1648 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1649 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1650 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1651 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1652 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1653 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1654
1655 if (drive_get_max_bus(IF_SCSI) > 0) {
1656 fprintf(stderr, "qemu: too many SCSI bus\n");
1657 exit(1);
1658 }
1659
1660 esp_init(hwdef->esp_base, 2,
1661 espdma_memory_read, espdma_memory_write,
1662 espdma, espdma_irq, &esp_reset, &dma_enable);
1663
1664 qdev_connect_gpio_out(espdma, 0, esp_reset);
1665 qdev_connect_gpio_out(espdma, 1, dma_enable);
1666
1667 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1668 RAM_size);
1669
1670 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1671 boot_device, RAM_size, kernel_size, graphic_width,
1672 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1673 "Sun4d");
1674
1675 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1676 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1677 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1678 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1679 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1680 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1681 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1682 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1683 if (kernel_cmdline) {
1684 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1685 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1686 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1687 } else {
1688 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1689 }
1690 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1691 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1692 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1693 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1694 }
1695
1696 /* SPARCserver 1000 hardware initialisation */
1697 static void ss1000_init(QEMUMachineInitArgs *args)
1698 {
1699 ram_addr_t RAM_size = args->ram_size;
1700 const char *cpu_model = args->cpu_model;
1701 const char *kernel_filename = args->kernel_filename;
1702 const char *kernel_cmdline = args->kernel_cmdline;
1703 const char *initrd_filename = args->initrd_filename;
1704 const char *boot_device = args->boot_device;
1705 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1706 kernel_cmdline, initrd_filename, cpu_model);
1707 }
1708
1709 /* SPARCcenter 2000 hardware initialisation */
1710 static void ss2000_init(QEMUMachineInitArgs *args)
1711 {
1712 ram_addr_t RAM_size = args->ram_size;
1713 const char *cpu_model = args->cpu_model;
1714 const char *kernel_filename = args->kernel_filename;
1715 const char *kernel_cmdline = args->kernel_cmdline;
1716 const char *initrd_filename = args->initrd_filename;
1717 const char *boot_device = args->boot_device;
1718 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1719 kernel_cmdline, initrd_filename, cpu_model);
1720 }
1721
1722 static QEMUMachine ss1000_machine = {
1723 .name = "SS-1000",
1724 .desc = "Sun4d platform, SPARCserver 1000",
1725 .init = ss1000_init,
1726 .block_default_type = IF_SCSI,
1727 .max_cpus = 8,
1728 DEFAULT_MACHINE_OPTIONS,
1729 };
1730
1731 static QEMUMachine ss2000_machine = {
1732 .name = "SS-2000",
1733 .desc = "Sun4d platform, SPARCcenter 2000",
1734 .init = ss2000_init,
1735 .block_default_type = IF_SCSI,
1736 .max_cpus = 20,
1737 DEFAULT_MACHINE_OPTIONS,
1738 };
1739
1740 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1741 /* SS-2 */
1742 {
1743 .iommu_base = 0xf8000000,
1744 .tcx_base = 0xfe000000,
1745 .slavio_base = 0xf6000000,
1746 .intctl_base = 0xf5000000,
1747 .counter_base = 0xf3000000,
1748 .ms_kb_base = 0xf0000000,
1749 .serial_base = 0xf1000000,
1750 .nvram_base = 0xf2000000,
1751 .fd_base = 0xf7200000,
1752 .dma_base = 0xf8400000,
1753 .esp_base = 0xf8800000,
1754 .le_base = 0xf8c00000,
1755 .aux1_base = 0xf7400003,
1756 .nvram_machine_id = 0x55,
1757 .machine_id = ss2_id,
1758 .max_mem = 0x10000000,
1759 .default_cpu_model = "Cypress CY7C601",
1760 },
1761 };
1762
1763 static DeviceState *sun4c_intctl_init(hwaddr addr,
1764 qemu_irq *parent_irq)
1765 {
1766 DeviceState *dev;
1767 SysBusDevice *s;
1768 unsigned int i;
1769
1770 dev = qdev_create(NULL, "sun4c_intctl");
1771 qdev_init_nofail(dev);
1772
1773 s = SYS_BUS_DEVICE(dev);
1774
1775 for (i = 0; i < MAX_PILS; i++) {
1776 sysbus_connect_irq(s, i, parent_irq[i]);
1777 }
1778 sysbus_mmio_map(s, 0, addr);
1779
1780 return dev;
1781 }
1782
1783 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1784 const char *boot_device,
1785 const char *kernel_filename,
1786 const char *kernel_cmdline,
1787 const char *initrd_filename, const char *cpu_model)
1788 {
1789 void *iommu, *espdma, *ledma, *nvram;
1790 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1791 qemu_irq esp_reset, dma_enable;
1792 qemu_irq fdc_tc;
1793 unsigned long kernel_size;
1794 DriveInfo *fd[MAX_FD];
1795 void *fw_cfg;
1796 DeviceState *dev;
1797 unsigned int i;
1798
1799 /* init CPU */
1800 if (!cpu_model)
1801 cpu_model = hwdef->default_cpu_model;
1802
1803 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1804
1805 /* set up devices */
1806 ram_init(0, RAM_size, hwdef->max_mem);
1807
1808 prom_init(hwdef->slavio_base, bios_name);
1809
1810 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1811
1812 for (i = 0; i < 8; i++) {
1813 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1814 }
1815
1816 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1817 slavio_irq[1]);
1818
1819 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1820 iommu, &espdma_irq, 0);
1821
1822 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1823 slavio_irq[3], iommu, &ledma_irq, 1);
1824
1825 if (graphic_depth != 8 && graphic_depth != 24) {
1826 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1827 exit (1);
1828 }
1829 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1830 graphic_depth);
1831
1832 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1833
1834 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1835
1836 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1837 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1838 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1839 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1840 escc_init(hwdef->serial_base, slavio_irq[1],
1841 slavio_irq[1], serial_hds[0], serial_hds[1],
1842 ESCC_CLOCK, 1);
1843
1844 if (hwdef->fd_base != (hwaddr)-1) {
1845 /* there is zero or one floppy drive */
1846 memset(fd, 0, sizeof(fd));
1847 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1848 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1849 &fdc_tc);
1850 } else {
1851 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
1852 }
1853
1854 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1855
1856 if (drive_get_max_bus(IF_SCSI) > 0) {
1857 fprintf(stderr, "qemu: too many SCSI bus\n");
1858 exit(1);
1859 }
1860
1861 esp_init(hwdef->esp_base, 2,
1862 espdma_memory_read, espdma_memory_write,
1863 espdma, espdma_irq, &esp_reset, &dma_enable);
1864
1865 qdev_connect_gpio_out(espdma, 0, esp_reset);
1866 qdev_connect_gpio_out(espdma, 1, dma_enable);
1867
1868 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1869 RAM_size);
1870
1871 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1872 boot_device, RAM_size, kernel_size, graphic_width,
1873 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1874 "Sun4c");
1875
1876 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1877 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1878 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1879 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1880 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1881 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1882 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1883 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1884 if (kernel_cmdline) {
1885 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1886 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1887 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1888 } else {
1889 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1890 }
1891 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1892 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1893 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1894 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1895 }
1896
1897 /* SPARCstation 2 hardware initialisation */
1898 static void ss2_init(QEMUMachineInitArgs *args)
1899 {
1900 ram_addr_t RAM_size = args->ram_size;
1901 const char *cpu_model = args->cpu_model;
1902 const char *kernel_filename = args->kernel_filename;
1903 const char *kernel_cmdline = args->kernel_cmdline;
1904 const char *initrd_filename = args->initrd_filename;
1905 const char *boot_device = args->boot_device;
1906 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1907 kernel_cmdline, initrd_filename, cpu_model);
1908 }
1909
1910 static QEMUMachine ss2_machine = {
1911 .name = "SS-2",
1912 .desc = "Sun4c platform, SPARCstation 2",
1913 .init = ss2_init,
1914 .block_default_type = IF_SCSI,
1915 DEFAULT_MACHINE_OPTIONS,
1916 };
1917
1918 static void sun4m_register_types(void)
1919 {
1920 type_register_static(&idreg_info);
1921 type_register_static(&afx_info);
1922 type_register_static(&prom_info);
1923 type_register_static(&ram_info);
1924 }
1925
1926 static void ss2_machine_init(void)
1927 {
1928 qemu_register_machine(&ss5_machine);
1929 qemu_register_machine(&ss10_machine);
1930 qemu_register_machine(&ss600mp_machine);
1931 qemu_register_machine(&ss20_machine);
1932 qemu_register_machine(&voyager_machine);
1933 qemu_register_machine(&ss_lx_machine);
1934 qemu_register_machine(&ss4_machine);
1935 qemu_register_machine(&scls_machine);
1936 qemu_register_machine(&sbook_machine);
1937 qemu_register_machine(&ss1000_machine);
1938 qemu_register_machine(&ss2000_machine);
1939 qemu_register_machine(&ss2_machine);
1940 }
1941
1942 type_init(sun4m_register_types)
1943 machine_init(ss2_machine_init);
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