hw/sparc64/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "qemu/error-report.h"
  26 #include "qapi/error.h"
  27 #include "qemu-common.h"
  28 #include "cpu.h"
  29 #include "hw/hw.h"
  30 #include "hw/pci/pci.h"
  31 #include "hw/pci/pci_bridge.h"
  32 #include "hw/pci/pci_bus.h"
  33 #include "hw/pci/pci_host.h"
  34 #include "hw/pci-host/sabre.h"
  35 #include "hw/i386/pc.h"
  36 #include "hw/char/serial.h"
  37 #include "hw/char/parallel.h"
  38 #include "hw/timer/m48t59.h"
  39 #include "hw/block/fdc.h"
  40 #include "net/net.h"
  41 #include "qemu/timer.h"
  42 #include "sysemu/sysemu.h"
  43 #include "hw/boards.h"
  44 #include "hw/nvram/sun_nvram.h"
  45 #include "hw/nvram/chrp_nvram.h"
  46 #include "hw/sparc/sparc64.h"
  47 #include "hw/nvram/fw_cfg.h"
  48 #include "hw/sysbus.h"
  49 #include "hw/ide.h"
  50 #include "hw/ide/pci.h"
  51 #include "hw/loader.h"
  52 #include "elf.h"
  53 #include "trace.h"
  54 #include "qemu/cutils.h"
  55
  56 #define KERNEL_LOAD_ADDR     0x00404000
  57 #define CMDLINE_ADDR         0x003ff000
  58 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  59 #define PROM_VADDR           0x000ffd00000ULL
  60 #define PBM_SPECIAL_BASE     0x1fe00000000ULL
  61 #define PBM_MEM_BASE         0x1ff00000000ULL
  62 #define PBM_PCI_IO_BASE      (PBM_SPECIAL_BASE + 0x02000000ULL)
  63 #define PROM_FILENAME        "openbios-sparc64"
  64 #define NVRAM_SIZE           0x2000
  65 #define MAX_IDE_BUS          2
  66 #define BIOS_CFG_IOPORT      0x510
  67 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  68 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  69 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  70
  71 #define IVEC_MAX             0x40
  72
  73 struct hwdef {
  74     uint16_t machine_id;
  75     uint64_t prom_addr;
  76     uint64_t console_serial_base;
  77 };
  78
  79 typedef struct EbusState {
  80     /*< private >*/
  81     PCIDevice parent_obj;
  82
  83     ISABus *isa_bus;
  84     qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
  85     uint64_t console_serial_base;
  86     MemoryRegion bar0;
  87     MemoryRegion bar1;
  88 } EbusState;
  89
  90 #define TYPE_EBUS "ebus"
  91 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
  92
  93 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
  94                             Error **errp)
  95 {
  96     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  97 }
  98
  99 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
 100                                   const char *arch, ram_addr_t RAM_size,
 101                                   const char *boot_devices,
 102                                   uint32_t kernel_image, uint32_t kernel_size,
 103                                   const char *cmdline,
 104                                   uint32_t initrd_image, uint32_t initrd_size,
 105                                   uint32_t NVRAM_image,
 106                                   int width, int height, int depth,
 107                                   const uint8_t *macaddr)
 108 {
 109     unsigned int i;
 110     int sysp_end;
 111     uint8_t image[0x1ff0];
 112     NvramClass *k = NVRAM_GET_CLASS(nvram);
 113
 114     memset(image, '\0', sizeof(image));
 115
 116     /* OpenBIOS nvram variables partition */
 117     sysp_end = chrp_nvram_create_system_partition(image, 0);
 118
 119     /* Free space partition */
 120     chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
 121
 122     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 123
 124     for (i = 0; i < sizeof(image); i++) {
 125         (k->write)(nvram, i, image[i]);
 126     }
 127
 128     return 0;
 129 }
 130
 131 static uint64_t sun4u_load_kernel(const char *kernel_filename,
 132                                   const char *initrd_filename,
 133                                   ram_addr_t RAM_size, uint64_t *initrd_size,
 134                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
 135                                   uint64_t *kernel_entry)
 136 {
 137     int linux_boot;
 138     unsigned int i;
 139     long kernel_size;
 140     uint8_t *ptr;
 141     uint64_t kernel_top;
 142
 143     linux_boot = (kernel_filename != NULL);
 144
 145     kernel_size = 0;
 146     if (linux_boot) {
 147         int bswap_needed;
 148
 149 #ifdef BSWAP_NEEDED
 150         bswap_needed = 1;
 151 #else
 152         bswap_needed = 0;
 153 #endif
 154         kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
 155                                kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
 156         if (kernel_size < 0) {
 157             *kernel_addr = KERNEL_LOAD_ADDR;
 158             *kernel_entry = KERNEL_LOAD_ADDR;
 159             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 160                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 161                                     TARGET_PAGE_SIZE);
 162         }
 163         if (kernel_size < 0) {
 164             kernel_size = load_image_targphys(kernel_filename,
 165                                               KERNEL_LOAD_ADDR,
 166                                               RAM_size - KERNEL_LOAD_ADDR);
 167         }
 168         if (kernel_size < 0) {
 169             error_report("could not load kernel '%s'", kernel_filename);
 170             exit(1);
 171         }
 172         /* load initrd above kernel */
 173         *initrd_size = 0;
 174         if (initrd_filename) {
 175             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
 176
 177             *initrd_size = load_image_targphys(initrd_filename,
 178                                                *initrd_addr,
 179                                                RAM_size - *initrd_addr);
 180             if ((int)*initrd_size < 0) {
 181                 error_report("could not load initial ram disk '%s'",
 182                              initrd_filename);
 183                 exit(1);
 184             }
 185         }
 186         if (*initrd_size > 0) {
 187             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 188                 ptr = rom_ptr(*kernel_addr + i);
 189                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 190                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
 191                     stl_p(ptr + 28, *initrd_size);
 192                     break;
 193                 }
 194             }
 195         }
 196     }
 197     return kernel_size;
 198 }
 199
 200 typedef struct ResetData {
 201     SPARCCPU *cpu;
 202     uint64_t prom_addr;
 203 } ResetData;
 204
 205 #define TYPE_SUN4U_POWER "power"
 206 #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER)
 207
 208 typedef struct PowerDevice {
 209     SysBusDevice parent_obj;
 210
 211     MemoryRegion power_mmio;
 212 } PowerDevice;
 213
 214 /* Power */
 215 static void power_mem_write(void *opaque, hwaddr addr,
 216                             uint64_t val, unsigned size)
 217 {
 218     /* According to a real Ultra 5, bit 24 controls the power */
 219     if (val & 0x1000000) {
 220         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 221     }
 222 }
 223
 224 static const MemoryRegionOps power_mem_ops = {
 225     .write = power_mem_write,
 226     .endianness = DEVICE_NATIVE_ENDIAN,
 227     .valid = {
 228         .min_access_size = 4,
 229         .max_access_size = 4,
 230     },
 231 };
 232
 233 static void power_realize(DeviceState *dev, Error **errp)
 234 {
 235     PowerDevice *d = SUN4U_POWER(dev);
 236     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 237
 238     memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
 239                           "power", sizeof(uint32_t));
 240
 241     sysbus_init_mmio(sbd, &d->power_mmio);
 242 }
 243
 244 static void power_class_init(ObjectClass *klass, void *data)
 245 {
 246     DeviceClass *dc = DEVICE_CLASS(klass);
 247
 248     dc->realize = power_realize;
 249 }
 250
 251 static const TypeInfo power_info = {
 252     .name          = TYPE_SUN4U_POWER,
 253     .parent        = TYPE_SYS_BUS_DEVICE,
 254     .instance_size = sizeof(PowerDevice),
 255     .class_init    = power_class_init,
 256 };
 257
 258 static void ebus_isa_irq_handler(void *opaque, int n, int level)
 259 {
 260     EbusState *s = EBUS(opaque);
 261     qemu_irq irq = s->isa_bus_irqs[n];
 262
 263     /* Pass ISA bus IRQs onto their gpio equivalent */
 264     trace_ebus_isa_irq_handler(n, level);
 265     if (irq) {
 266         qemu_set_irq(irq, level);
 267     }
 268 }
 269
 270 /* EBUS (Eight bit bus) bridge */
 271 static void ebus_realize(PCIDevice *pci_dev, Error **errp)
 272 {
 273     EbusState *s = EBUS(pci_dev);
 274     SysBusDevice *sbd;
 275     DeviceState *dev;
 276     qemu_irq *isa_irq;
 277     DriveInfo *fd[MAX_FD];
 278     int i;
 279
 280     s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
 281                              pci_address_space_io(pci_dev), errp);
 282     if (!s->isa_bus) {
 283         error_setg(errp, "unable to instantiate EBUS ISA bus");
 284         return;
 285     }
 286
 287     /* ISA bus */
 288     isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
 289     isa_bus_irqs(s->isa_bus, isa_irq);
 290     qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
 291                              ISA_NUM_IRQS);
 292
 293     /* Serial ports */
 294     i = 0;
 295     if (s->console_serial_base) {
 296         serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
 297                        0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
 298         i++;
 299     }
 300     serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS);
 301
 302     /* Parallel ports */
 303     parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
 304
 305     /* Keyboard */
 306     isa_create_simple(s->isa_bus, "i8042");
 307
 308     /* Floppy */
 309     for (i = 0; i < MAX_FD; i++) {
 310         fd[i] = drive_get(IF_FLOPPY, 0, i);
 311     }
 312     dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
 313     if (fd[0]) {
 314         qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
 315                             &error_abort);
 316     }
 317     if (fd[1]) {
 318         qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
 319                             &error_abort);
 320     }
 321     qdev_prop_set_uint32(dev, "dma", -1);
 322     qdev_init_nofail(dev);
 323
 324     /* Power */
 325     dev = qdev_create(NULL, TYPE_SUN4U_POWER);
 326     qdev_init_nofail(dev);
 327     sbd = SYS_BUS_DEVICE(dev);
 328     memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
 329                                 sysbus_mmio_get_region(sbd, 0));
 330
 331     /* PCI */
 332     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 333     pci_dev->config[0x05] = 0x00;
 334     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 335     pci_dev->config[0x07] = 0x03; // status = medium devsel
 336     pci_dev->config[0x09] = 0x00; // programming i/f
 337     pci_dev->config[0x0D] = 0x0a; // latency_timer
 338
 339     memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
 340                              0, 0x1000000);
 341     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 342     memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
 343                              0, 0x8000);
 344     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
 345 }
 346
 347 static Property ebus_properties[] = {
 348     DEFINE_PROP_UINT64("console-serial-base", EbusState,
 349                        console_serial_base, 0),
 350     DEFINE_PROP_END_OF_LIST(),
 351 };
 352
 353 static void ebus_class_init(ObjectClass *klass, void *data)
 354 {
 355     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 356     DeviceClass *dc = DEVICE_CLASS(klass);
 357
 358     k->realize = ebus_realize;
 359     k->vendor_id = PCI_VENDOR_ID_SUN;
 360     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 361     k->revision = 0x01;
 362     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 363     dc->props = ebus_properties;
 364 }
 365
 366 static const TypeInfo ebus_info = {
 367     .name          = TYPE_EBUS,
 368     .parent        = TYPE_PCI_DEVICE,
 369     .class_init    = ebus_class_init,
 370     .instance_size = sizeof(EbusState),
 371     .interfaces = (InterfaceInfo[]) {
 372         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 373         { },
 374     },
 375 };
 376
 377 #define TYPE_OPENPROM "openprom"
 378 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
 379
 380 typedef struct PROMState {
 381     SysBusDevice parent_obj;
 382
 383     MemoryRegion prom;
 384 } PROMState;
 385
 386 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 387 {
 388     hwaddr *base_addr = (hwaddr *)opaque;
 389     return addr + *base_addr - PROM_VADDR;
 390 }
 391
 392 /* Boot PROM (OpenBIOS) */
 393 static void prom_init(hwaddr addr, const char *bios_name)
 394 {
 395     DeviceState *dev;
 396     SysBusDevice *s;
 397     char *filename;
 398     int ret;
 399
 400     dev = qdev_create(NULL, TYPE_OPENPROM);
 401     qdev_init_nofail(dev);
 402     s = SYS_BUS_DEVICE(dev);
 403
 404     sysbus_mmio_map(s, 0, addr);
 405
 406     /* load boot prom */
 407     if (bios_name == NULL) {
 408         bios_name = PROM_FILENAME;
 409     }
 410     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 411     if (filename) {
 412         ret = load_elf(filename, translate_prom_address, &addr,
 413                        NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
 414         if (ret < 0 || ret > PROM_SIZE_MAX) {
 415             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 416         }
 417         g_free(filename);
 418     } else {
 419         ret = -1;
 420     }
 421     if (ret < 0 || ret > PROM_SIZE_MAX) {
 422         error_report("could not load prom '%s'", bios_name);
 423         exit(1);
 424     }
 425 }
 426
 427 static void prom_init1(Object *obj)
 428 {
 429     PROMState *s = OPENPROM(obj);
 430     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 431
 432     memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX,
 433                            &error_fatal);
 434     vmstate_register_ram_global(&s->prom);
 435     memory_region_set_readonly(&s->prom, true);
 436     sysbus_init_mmio(dev, &s->prom);
 437 }
 438
 439 static Property prom_properties[] = {
 440     {/* end of property list */},
 441 };
 442
 443 static void prom_class_init(ObjectClass *klass, void *data)
 444 {
 445     DeviceClass *dc = DEVICE_CLASS(klass);
 446
 447     dc->props = prom_properties;
 448 }
 449
 450 static const TypeInfo prom_info = {
 451     .name          = TYPE_OPENPROM,
 452     .parent        = TYPE_SYS_BUS_DEVICE,
 453     .instance_size = sizeof(PROMState),
 454     .class_init    = prom_class_init,
 455     .instance_init = prom_init1,
 456 };
 457
 458
 459 #define TYPE_SUN4U_MEMORY "memory"
 460 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
 461
 462 typedef struct RamDevice {
 463     SysBusDevice parent_obj;
 464
 465     MemoryRegion ram;
 466     uint64_t size;
 467 } RamDevice;
 468
 469 /* System RAM */
 470 static void ram_realize(DeviceState *dev, Error **errp)
 471 {
 472     RamDevice *d = SUN4U_RAM(dev);
 473     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 474
 475     memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
 476                            &error_fatal);
 477     vmstate_register_ram_global(&d->ram);
 478     sysbus_init_mmio(sbd, &d->ram);
 479 }
 480
 481 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
 482 {
 483     DeviceState *dev;
 484     SysBusDevice *s;
 485     RamDevice *d;
 486
 487     /* allocate RAM */
 488     dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
 489     s = SYS_BUS_DEVICE(dev);
 490
 491     d = SUN4U_RAM(dev);
 492     d->size = RAM_size;
 493     qdev_init_nofail(dev);
 494
 495     sysbus_mmio_map(s, 0, addr);
 496 }
 497
 498 static Property ram_properties[] = {
 499     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 500     DEFINE_PROP_END_OF_LIST(),
 501 };
 502
 503 static void ram_class_init(ObjectClass *klass, void *data)
 504 {
 505     DeviceClass *dc = DEVICE_CLASS(klass);
 506
 507     dc->realize = ram_realize;
 508     dc->props = ram_properties;
 509 }
 510
 511 static const TypeInfo ram_info = {
 512     .name          = TYPE_SUN4U_MEMORY,
 513     .parent        = TYPE_SYS_BUS_DEVICE,
 514     .instance_size = sizeof(RamDevice),
 515     .class_init    = ram_class_init,
 516 };
 517
 518 static void sun4uv_init(MemoryRegion *address_space_mem,
 519                         MachineState *machine,
 520                         const struct hwdef *hwdef)
 521 {
 522     SPARCCPU *cpu;
 523     Nvram *nvram;
 524     unsigned int i;
 525     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
 526     SabreState *sabre;
 527     PCIBus *pci_bus, *pci_busA, *pci_busB;
 528     PCIDevice *ebus, *pci_dev;
 529     SysBusDevice *s;
 530     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 531     DeviceState *iommu, *dev;
 532     FWCfgState *fw_cfg;
 533     NICInfo *nd;
 534     MACAddr macaddr;
 535     bool onboard_nic;
 536
 537     /* init CPUs */
 538     cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
 539
 540     /* IOMMU */
 541     iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
 542     qdev_init_nofail(iommu);
 543
 544     /* set up devices */
 545     ram_init(0, machine->ram_size);
 546
 547     prom_init(hwdef->prom_addr, bios_name);
 548
 549     /* Init sabre (PCI host bridge) */
 550     sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
 551     qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
 552     qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
 553     object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
 554                              &error_abort);
 555     qdev_init_nofail(DEVICE(sabre));
 556
 557     /* Wire up PCI interrupts to CPU */
 558     for (i = 0; i < IVEC_MAX; i++) {
 559         qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
 560             qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
 561     }
 562
 563     pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
 564     pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
 565     pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
 566
 567     /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
 568        reserved (leaving no slots free after on-board devices) however slots
 569        0-3 are free on busB */
 570     pci_bus->slot_reserved_mask = 0xfffffffc;
 571     pci_busA->slot_reserved_mask = 0xfffffff1;
 572     pci_busB->slot_reserved_mask = 0xfffffff0;
 573
 574     ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
 575     qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
 576                          hwdef->console_serial_base);
 577     qdev_init_nofail(DEVICE(ebus));
 578
 579     /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
 580     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
 581         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
 582     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
 583         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
 584     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
 585         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
 586     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
 587         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
 588     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
 589         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
 590
 591     pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
 592
 593     memset(&macaddr, 0, sizeof(MACAddr));
 594     onboard_nic = false;
 595     for (i = 0; i < nb_nics; i++) {
 596         nd = &nd_table[i];
 597
 598         if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
 599             if (!onboard_nic) {
 600                 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
 601                                                    true, "sunhme");
 602                 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
 603                 onboard_nic = true;
 604             } else {
 605                 pci_dev = pci_create(pci_busB, -1, "sunhme");
 606             }
 607         } else {
 608             pci_dev = pci_create(pci_busB, -1, nd->model);
 609         }
 610
 611         dev = &pci_dev->qdev;
 612         qdev_set_nic_properties(dev, nd);
 613         qdev_init_nofail(dev);
 614     }
 615
 616     /* If we don't have an onboard NIC, grab a default MAC address so that
 617      * we have a valid machine id */
 618     if (!onboard_nic) {
 619         qemu_macaddr_default_if_unset(&macaddr);
 620     }
 621
 622     ide_drive_get(hd, ARRAY_SIZE(hd));
 623
 624     pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
 625     qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
 626     qdev_init_nofail(&pci_dev->qdev);
 627     pci_ide_create_devs(pci_dev, hd);
 628
 629     /* Map NVRAM into I/O (ebus) space */
 630     nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
 631     s = SYS_BUS_DEVICE(nvram);
 632     memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
 633                                 sysbus_mmio_get_region(s, 0));
 634
 635     initrd_size = 0;
 636     initrd_addr = 0;
 637     kernel_size = sun4u_load_kernel(machine->kernel_filename,
 638                                     machine->initrd_filename,
 639                                     ram_size, &initrd_size, &initrd_addr,
 640                                     &kernel_addr, &kernel_entry);
 641
 642     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
 643                            machine->boot_order,
 644                            kernel_addr, kernel_size,
 645                            machine->kernel_cmdline,
 646                            initrd_addr, initrd_size,
 647                            /* XXX: need an option to load a NVRAM image */
 648                            0,
 649                            graphic_width, graphic_height, graphic_depth,
 650                            (uint8_t *)&macaddr);
 651
 652     dev = qdev_create(NULL, TYPE_FW_CFG_IO);
 653     qdev_prop_set_bit(dev, "dma_enabled", false);
 654     object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
 655     qdev_init_nofail(dev);
 656     memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
 657                                 &FW_CFG_IO(dev)->comb_iomem);
 658
 659     fw_cfg = FW_CFG(dev);
 660     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
 661     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
 662     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 663     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 664     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
 665     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 666     if (machine->kernel_cmdline) {
 667         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 668                        strlen(machine->kernel_cmdline) + 1);
 669         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
 670     } else {
 671         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 672     }
 673     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 674     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 675     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
 676
 677     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 678     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 679     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 680
 681     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 682 }
 683
 684 enum {
 685     sun4u_id = 0,
 686     sun4v_id = 64,
 687 };
 688
 689 static const struct hwdef hwdefs[] = {
 690     /* Sun4u generic PC-like machine */
 691     {
 692         .machine_id = sun4u_id,
 693         .prom_addr = 0x1fff0000000ULL,
 694         .console_serial_base = 0,
 695     },
 696     /* Sun4v generic PC-like machine */
 697     {
 698         .machine_id = sun4v_id,
 699         .prom_addr = 0x1fff0000000ULL,
 700         .console_serial_base = 0,
 701     },
 702 };
 703
 704 /* Sun4u hardware initialisation */
 705 static void sun4u_init(MachineState *machine)
 706 {
 707     sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
 708 }
 709
 710 /* Sun4v hardware initialisation */
 711 static void sun4v_init(MachineState *machine)
 712 {
 713     sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
 714 }
 715
 716 static void sun4u_class_init(ObjectClass *oc, void *data)
 717 {
 718     MachineClass *mc = MACHINE_CLASS(oc);
 719
 720     mc->desc = "Sun4u platform";
 721     mc->init = sun4u_init;
 722     mc->block_default_type = IF_IDE;
 723     mc->max_cpus = 1; /* XXX for now */
 724     mc->is_default = 1;
 725     mc->default_boot_order = "c";
 726     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
 727 }
 728
 729 static const TypeInfo sun4u_type = {
 730     .name = MACHINE_TYPE_NAME("sun4u"),
 731     .parent = TYPE_MACHINE,
 732     .class_init = sun4u_class_init,
 733 };
 734
 735 static void sun4v_class_init(ObjectClass *oc, void *data)
 736 {
 737     MachineClass *mc = MACHINE_CLASS(oc);
 738
 739     mc->desc = "Sun4v platform";
 740     mc->init = sun4v_init;
 741     mc->block_default_type = IF_IDE;
 742     mc->max_cpus = 1; /* XXX for now */
 743     mc->default_boot_order = "c";
 744     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
 745 }
 746
 747 static const TypeInfo sun4v_type = {
 748     .name = MACHINE_TYPE_NAME("sun4v"),
 749     .parent = TYPE_MACHINE,
 750     .class_init = sun4v_class_init,
 751 };
 752
 753 static void sun4u_register_types(void)
 754 {
 755     type_register_static(&power_info);
 756     type_register_static(&ebus_info);
 757     type_register_static(&prom_info);
 758     type_register_static(&ram_info);
 759
 760     type_register_static(&sun4u_type);
 761     type_register_static(&sun4v_type);
 762 }
 763
 764 type_init(sun4u_register_types)