hw/sparc64/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "qemu/error-report.h"
  26 #include "qapi/error.h"
  27 #include "qemu-common.h"
  28 #include "cpu.h"
  29 #include "hw/hw.h"
  30 #include "hw/pci/pci.h"
  31 #include "hw/pci/pci_bridge.h"
  32 #include "hw/pci/pci_bus.h"
  33 #include "hw/pci/pci_host.h"
  34 #include "hw/pci-host/sabre.h"
  35 #include "hw/i386/pc.h"
  36 #include "hw/char/serial.h"
  37 #include "hw/char/parallel.h"
  38 #include "hw/timer/m48t59.h"
  39 #include "hw/block/fdc.h"
  40 #include "net/net.h"
  41 #include "qemu/timer.h"
  42 #include "sysemu/sysemu.h"
  43 #include "hw/boards.h"
  44 #include "hw/nvram/sun_nvram.h"
  45 #include "hw/nvram/chrp_nvram.h"
  46 #include "hw/sparc/sparc64.h"
  47 #include "hw/nvram/fw_cfg.h"
  48 #include "hw/sysbus.h"
  49 #include "hw/ide.h"
  50 #include "hw/ide/pci.h"
  51 #include "hw/loader.h"
  52 #include "elf.h"
  53 #include "trace.h"
  54 #include "qemu/cutils.h"
  55
  56 #define KERNEL_LOAD_ADDR     0x00404000
  57 #define CMDLINE_ADDR         0x003ff000
  58 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  59 #define PROM_VADDR           0x000ffd00000ULL
  60 #define PBM_SPECIAL_BASE     0x1fe00000000ULL
  61 #define PBM_MEM_BASE         0x1ff00000000ULL
  62 #define PBM_PCI_IO_BASE      (PBM_SPECIAL_BASE + 0x02000000ULL)
  63 #define PROM_FILENAME        "openbios-sparc64"
  64 #define NVRAM_SIZE           0x2000
  65 #define MAX_IDE_BUS          2
  66 #define BIOS_CFG_IOPORT      0x510
  67 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  68 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  69 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  70
  71 #define IVEC_MAX             0x40
  72
  73 struct hwdef {
  74     uint16_t machine_id;
  75     uint64_t prom_addr;
  76     uint64_t console_serial_base;
  77 };
  78
  79 typedef struct EbusState {
  80     /*< private >*/
  81     PCIDevice parent_obj;
  82
  83     ISABus *isa_bus;
  84     qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
  85     uint64_t console_serial_base;
  86     MemoryRegion bar0;
  87     MemoryRegion bar1;
  88 } EbusState;
  89
  90 #define TYPE_EBUS "ebus"
  91 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
  92
  93 void DMA_init(ISABus *bus, int high_page_enable)
  94 {
  95 }
  96
  97 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
  98                             Error **errp)
  99 {
 100     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 101 }
 102
 103 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
 104                                   const char *arch, ram_addr_t RAM_size,
 105                                   const char *boot_devices,
 106                                   uint32_t kernel_image, uint32_t kernel_size,
 107                                   const char *cmdline,
 108                                   uint32_t initrd_image, uint32_t initrd_size,
 109                                   uint32_t NVRAM_image,
 110                                   int width, int height, int depth,
 111                                   const uint8_t *macaddr)
 112 {
 113     unsigned int i;
 114     int sysp_end;
 115     uint8_t image[0x1ff0];
 116     NvramClass *k = NVRAM_GET_CLASS(nvram);
 117
 118     memset(image, '\0', sizeof(image));
 119
 120     /* OpenBIOS nvram variables partition */
 121     sysp_end = chrp_nvram_create_system_partition(image, 0);
 122
 123     /* Free space partition */
 124     chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
 125
 126     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 127
 128     for (i = 0; i < sizeof(image); i++) {
 129         (k->write)(nvram, i, image[i]);
 130     }
 131
 132     return 0;
 133 }
 134
 135 static uint64_t sun4u_load_kernel(const char *kernel_filename,
 136                                   const char *initrd_filename,
 137                                   ram_addr_t RAM_size, uint64_t *initrd_size,
 138                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
 139                                   uint64_t *kernel_entry)
 140 {
 141     int linux_boot;
 142     unsigned int i;
 143     long kernel_size;
 144     uint8_t *ptr;
 145     uint64_t kernel_top;
 146
 147     linux_boot = (kernel_filename != NULL);
 148
 149     kernel_size = 0;
 150     if (linux_boot) {
 151         int bswap_needed;
 152
 153 #ifdef BSWAP_NEEDED
 154         bswap_needed = 1;
 155 #else
 156         bswap_needed = 0;
 157 #endif
 158         kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
 159                                kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
 160         if (kernel_size < 0) {
 161             *kernel_addr = KERNEL_LOAD_ADDR;
 162             *kernel_entry = KERNEL_LOAD_ADDR;
 163             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 164                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 165                                     TARGET_PAGE_SIZE);
 166         }
 167         if (kernel_size < 0) {
 168             kernel_size = load_image_targphys(kernel_filename,
 169                                               KERNEL_LOAD_ADDR,
 170                                               RAM_size - KERNEL_LOAD_ADDR);
 171         }
 172         if (kernel_size < 0) {
 173             error_report("could not load kernel '%s'", kernel_filename);
 174             exit(1);
 175         }
 176         /* load initrd above kernel */
 177         *initrd_size = 0;
 178         if (initrd_filename) {
 179             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
 180
 181             *initrd_size = load_image_targphys(initrd_filename,
 182                                                *initrd_addr,
 183                                                RAM_size - *initrd_addr);
 184             if ((int)*initrd_size < 0) {
 185                 error_report("could not load initial ram disk '%s'",
 186                              initrd_filename);
 187                 exit(1);
 188             }
 189         }
 190         if (*initrd_size > 0) {
 191             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 192                 ptr = rom_ptr(*kernel_addr + i);
 193                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 194                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
 195                     stl_p(ptr + 28, *initrd_size);
 196                     break;
 197                 }
 198             }
 199         }
 200     }
 201     return kernel_size;
 202 }
 203
 204 typedef struct ResetData {
 205     SPARCCPU *cpu;
 206     uint64_t prom_addr;
 207 } ResetData;
 208
 209 #define TYPE_SUN4U_POWER "power"
 210 #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER)
 211
 212 typedef struct PowerDevice {
 213     SysBusDevice parent_obj;
 214
 215     MemoryRegion power_mmio;
 216 } PowerDevice;
 217
 218 /* Power */
 219 static void power_mem_write(void *opaque, hwaddr addr,
 220                             uint64_t val, unsigned size)
 221 {
 222     /* According to a real Ultra 5, bit 24 controls the power */
 223     if (val & 0x1000000) {
 224         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 225     }
 226 }
 227
 228 static const MemoryRegionOps power_mem_ops = {
 229     .write = power_mem_write,
 230     .endianness = DEVICE_NATIVE_ENDIAN,
 231     .valid = {
 232         .min_access_size = 4,
 233         .max_access_size = 4,
 234     },
 235 };
 236
 237 static void power_realize(DeviceState *dev, Error **errp)
 238 {
 239     PowerDevice *d = SUN4U_POWER(dev);
 240     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 241
 242     memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
 243                           "power", sizeof(uint32_t));
 244
 245     sysbus_init_mmio(sbd, &d->power_mmio);
 246 }
 247
 248 static void power_class_init(ObjectClass *klass, void *data)
 249 {
 250     DeviceClass *dc = DEVICE_CLASS(klass);
 251
 252     dc->realize = power_realize;
 253 }
 254
 255 static const TypeInfo power_info = {
 256     .name          = TYPE_SUN4U_POWER,
 257     .parent        = TYPE_SYS_BUS_DEVICE,
 258     .instance_size = sizeof(PowerDevice),
 259     .class_init    = power_class_init,
 260 };
 261
 262 static void ebus_isa_irq_handler(void *opaque, int n, int level)
 263 {
 264     EbusState *s = EBUS(opaque);
 265     qemu_irq irq = s->isa_bus_irqs[n];
 266
 267     /* Pass ISA bus IRQs onto their gpio equivalent */
 268     trace_ebus_isa_irq_handler(n, level);
 269     if (irq) {
 270         qemu_set_irq(irq, level);
 271     }
 272 }
 273
 274 /* EBUS (Eight bit bus) bridge */
 275 static void ebus_realize(PCIDevice *pci_dev, Error **errp)
 276 {
 277     EbusState *s = EBUS(pci_dev);
 278     SysBusDevice *sbd;
 279     DeviceState *dev;
 280     qemu_irq *isa_irq;
 281     DriveInfo *fd[MAX_FD];
 282     int i;
 283
 284     s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
 285                              pci_address_space_io(pci_dev), errp);
 286     if (!s->isa_bus) {
 287         error_setg(errp, "unable to instantiate EBUS ISA bus");
 288         return;
 289     }
 290
 291     /* ISA bus */
 292     isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
 293     isa_bus_irqs(s->isa_bus, isa_irq);
 294     qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
 295                              ISA_NUM_IRQS);
 296
 297     /* Serial ports */
 298     i = 0;
 299     if (s->console_serial_base) {
 300         serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
 301                        0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
 302         i++;
 303     }
 304     serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS);
 305
 306     /* Parallel ports */
 307     parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
 308
 309     /* Keyboard */
 310     isa_create_simple(s->isa_bus, "i8042");
 311
 312     /* Floppy */
 313     for (i = 0; i < MAX_FD; i++) {
 314         fd[i] = drive_get(IF_FLOPPY, 0, i);
 315     }
 316     dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
 317     if (fd[0]) {
 318         qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
 319                             &error_abort);
 320     }
 321     if (fd[1]) {
 322         qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
 323                             &error_abort);
 324     }
 325     qdev_prop_set_uint32(dev, "dma", -1);
 326     qdev_init_nofail(dev);
 327
 328     /* Power */
 329     dev = qdev_create(NULL, TYPE_SUN4U_POWER);
 330     qdev_init_nofail(dev);
 331     sbd = SYS_BUS_DEVICE(dev);
 332     memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
 333                                 sysbus_mmio_get_region(sbd, 0));
 334
 335     /* PCI */
 336     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 337     pci_dev->config[0x05] = 0x00;
 338     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 339     pci_dev->config[0x07] = 0x03; // status = medium devsel
 340     pci_dev->config[0x09] = 0x00; // programming i/f
 341     pci_dev->config[0x0D] = 0x0a; // latency_timer
 342
 343     memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
 344                              0, 0x1000000);
 345     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 346     memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
 347                              0, 0x8000);
 348     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
 349 }
 350
 351 static Property ebus_properties[] = {
 352     DEFINE_PROP_UINT64("console-serial-base", EbusState,
 353                        console_serial_base, 0),
 354     DEFINE_PROP_END_OF_LIST(),
 355 };
 356
 357 static void ebus_class_init(ObjectClass *klass, void *data)
 358 {
 359     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 360     DeviceClass *dc = DEVICE_CLASS(klass);
 361
 362     k->realize = ebus_realize;
 363     k->vendor_id = PCI_VENDOR_ID_SUN;
 364     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 365     k->revision = 0x01;
 366     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 367     dc->props = ebus_properties;
 368 }
 369
 370 static const TypeInfo ebus_info = {
 371     .name          = TYPE_EBUS,
 372     .parent        = TYPE_PCI_DEVICE,
 373     .class_init    = ebus_class_init,
 374     .instance_size = sizeof(EbusState),
 375     .interfaces = (InterfaceInfo[]) {
 376         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 377         { },
 378     },
 379 };
 380
 381 #define TYPE_OPENPROM "openprom"
 382 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
 383
 384 typedef struct PROMState {
 385     SysBusDevice parent_obj;
 386
 387     MemoryRegion prom;
 388 } PROMState;
 389
 390 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 391 {
 392     hwaddr *base_addr = (hwaddr *)opaque;
 393     return addr + *base_addr - PROM_VADDR;
 394 }
 395
 396 /* Boot PROM (OpenBIOS) */
 397 static void prom_init(hwaddr addr, const char *bios_name)
 398 {
 399     DeviceState *dev;
 400     SysBusDevice *s;
 401     char *filename;
 402     int ret;
 403
 404     dev = qdev_create(NULL, TYPE_OPENPROM);
 405     qdev_init_nofail(dev);
 406     s = SYS_BUS_DEVICE(dev);
 407
 408     sysbus_mmio_map(s, 0, addr);
 409
 410     /* load boot prom */
 411     if (bios_name == NULL) {
 412         bios_name = PROM_FILENAME;
 413     }
 414     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 415     if (filename) {
 416         ret = load_elf(filename, translate_prom_address, &addr,
 417                        NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
 418         if (ret < 0 || ret > PROM_SIZE_MAX) {
 419             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 420         }
 421         g_free(filename);
 422     } else {
 423         ret = -1;
 424     }
 425     if (ret < 0 || ret > PROM_SIZE_MAX) {
 426         error_report("could not load prom '%s'", bios_name);
 427         exit(1);
 428     }
 429 }
 430
 431 static void prom_init1(Object *obj)
 432 {
 433     PROMState *s = OPENPROM(obj);
 434     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 435
 436     memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX,
 437                            &error_fatal);
 438     vmstate_register_ram_global(&s->prom);
 439     memory_region_set_readonly(&s->prom, true);
 440     sysbus_init_mmio(dev, &s->prom);
 441 }
 442
 443 static Property prom_properties[] = {
 444     {/* end of property list */},
 445 };
 446
 447 static void prom_class_init(ObjectClass *klass, void *data)
 448 {
 449     DeviceClass *dc = DEVICE_CLASS(klass);
 450
 451     dc->props = prom_properties;
 452 }
 453
 454 static const TypeInfo prom_info = {
 455     .name          = TYPE_OPENPROM,
 456     .parent        = TYPE_SYS_BUS_DEVICE,
 457     .instance_size = sizeof(PROMState),
 458     .class_init    = prom_class_init,
 459     .instance_init = prom_init1,
 460 };
 461
 462
 463 #define TYPE_SUN4U_MEMORY "memory"
 464 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
 465
 466 typedef struct RamDevice {
 467     SysBusDevice parent_obj;
 468
 469     MemoryRegion ram;
 470     uint64_t size;
 471 } RamDevice;
 472
 473 /* System RAM */
 474 static void ram_realize(DeviceState *dev, Error **errp)
 475 {
 476     RamDevice *d = SUN4U_RAM(dev);
 477     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 478
 479     memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
 480                            &error_fatal);
 481     vmstate_register_ram_global(&d->ram);
 482     sysbus_init_mmio(sbd, &d->ram);
 483 }
 484
 485 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
 486 {
 487     DeviceState *dev;
 488     SysBusDevice *s;
 489     RamDevice *d;
 490
 491     /* allocate RAM */
 492     dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
 493     s = SYS_BUS_DEVICE(dev);
 494
 495     d = SUN4U_RAM(dev);
 496     d->size = RAM_size;
 497     qdev_init_nofail(dev);
 498
 499     sysbus_mmio_map(s, 0, addr);
 500 }
 501
 502 static Property ram_properties[] = {
 503     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 504     DEFINE_PROP_END_OF_LIST(),
 505 };
 506
 507 static void ram_class_init(ObjectClass *klass, void *data)
 508 {
 509     DeviceClass *dc = DEVICE_CLASS(klass);
 510
 511     dc->realize = ram_realize;
 512     dc->props = ram_properties;
 513 }
 514
 515 static const TypeInfo ram_info = {
 516     .name          = TYPE_SUN4U_MEMORY,
 517     .parent        = TYPE_SYS_BUS_DEVICE,
 518     .instance_size = sizeof(RamDevice),
 519     .class_init    = ram_class_init,
 520 };
 521
 522 static void sun4uv_init(MemoryRegion *address_space_mem,
 523                         MachineState *machine,
 524                         const struct hwdef *hwdef)
 525 {
 526     SPARCCPU *cpu;
 527     Nvram *nvram;
 528     unsigned int i;
 529     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
 530     SabreState *sabre;
 531     PCIBus *pci_bus, *pci_busA, *pci_busB;
 532     PCIDevice *ebus, *pci_dev;
 533     SysBusDevice *s;
 534     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 535     DeviceState *iommu, *dev;
 536     FWCfgState *fw_cfg;
 537     NICInfo *nd;
 538     MACAddr macaddr;
 539     bool onboard_nic;
 540
 541     /* init CPUs */
 542     cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
 543
 544     /* IOMMU */
 545     iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
 546     qdev_init_nofail(iommu);
 547
 548     /* set up devices */
 549     ram_init(0, machine->ram_size);
 550
 551     prom_init(hwdef->prom_addr, bios_name);
 552
 553     /* Init sabre (PCI host bridge) */
 554     sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
 555     qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
 556     qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
 557     object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
 558                              &error_abort);
 559     qdev_init_nofail(DEVICE(sabre));
 560
 561     /* Wire up PCI interrupts to CPU */
 562     for (i = 0; i < IVEC_MAX; i++) {
 563         qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
 564             qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
 565     }
 566
 567     pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
 568     pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
 569     pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
 570
 571     /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
 572        reserved (leaving no slots free after on-board devices) however slots
 573        0-3 are free on busB */
 574     pci_bus->slot_reserved_mask = 0xfffffffc;
 575     pci_busA->slot_reserved_mask = 0xfffffff1;
 576     pci_busB->slot_reserved_mask = 0xfffffff0;
 577
 578     ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
 579     qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
 580                          hwdef->console_serial_base);
 581     qdev_init_nofail(DEVICE(ebus));
 582
 583     /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
 584     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
 585         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
 586     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
 587         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
 588     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
 589         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
 590     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
 591         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
 592     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
 593         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
 594
 595     pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
 596
 597     memset(&macaddr, 0, sizeof(MACAddr));
 598     onboard_nic = false;
 599     for (i = 0; i < nb_nics; i++) {
 600         nd = &nd_table[i];
 601
 602         if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
 603             if (!onboard_nic) {
 604                 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
 605                                                    true, "sunhme");
 606                 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
 607                 onboard_nic = true;
 608             } else {
 609                 pci_dev = pci_create(pci_busB, -1, "sunhme");
 610             }
 611         } else {
 612             pci_dev = pci_create(pci_busB, -1, nd->model);
 613         }
 614
 615         dev = &pci_dev->qdev;
 616         qdev_set_nic_properties(dev, nd);
 617         qdev_init_nofail(dev);
 618     }
 619
 620     /* If we don't have an onboard NIC, grab a default MAC address so that
 621      * we have a valid machine id */
 622     if (!onboard_nic) {
 623         qemu_macaddr_default_if_unset(&macaddr);
 624     }
 625
 626     ide_drive_get(hd, ARRAY_SIZE(hd));
 627
 628     pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
 629     qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
 630     qdev_init_nofail(&pci_dev->qdev);
 631     pci_ide_create_devs(pci_dev, hd);
 632
 633     /* Map NVRAM into I/O (ebus) space */
 634     nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
 635     s = SYS_BUS_DEVICE(nvram);
 636     memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
 637                                 sysbus_mmio_get_region(s, 0));
 638
 639     initrd_size = 0;
 640     initrd_addr = 0;
 641     kernel_size = sun4u_load_kernel(machine->kernel_filename,
 642                                     machine->initrd_filename,
 643                                     ram_size, &initrd_size, &initrd_addr,
 644                                     &kernel_addr, &kernel_entry);
 645
 646     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
 647                            machine->boot_order,
 648                            kernel_addr, kernel_size,
 649                            machine->kernel_cmdline,
 650                            initrd_addr, initrd_size,
 651                            /* XXX: need an option to load a NVRAM image */
 652                            0,
 653                            graphic_width, graphic_height, graphic_depth,
 654                            (uint8_t *)&macaddr);
 655
 656     dev = qdev_create(NULL, TYPE_FW_CFG_IO);
 657     qdev_prop_set_bit(dev, "dma_enabled", false);
 658     object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
 659     qdev_init_nofail(dev);
 660     memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
 661                                 &FW_CFG_IO(dev)->comb_iomem);
 662
 663     fw_cfg = FW_CFG(dev);
 664     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
 665     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
 666     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 667     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 668     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
 669     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 670     if (machine->kernel_cmdline) {
 671         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 672                        strlen(machine->kernel_cmdline) + 1);
 673         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
 674     } else {
 675         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 676     }
 677     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 678     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 679     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
 680
 681     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 682     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 683     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 684
 685     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 686 }
 687
 688 enum {
 689     sun4u_id = 0,
 690     sun4v_id = 64,
 691 };
 692
 693 static const struct hwdef hwdefs[] = {
 694     /* Sun4u generic PC-like machine */
 695     {
 696         .machine_id = sun4u_id,
 697         .prom_addr = 0x1fff0000000ULL,
 698         .console_serial_base = 0,
 699     },
 700     /* Sun4v generic PC-like machine */
 701     {
 702         .machine_id = sun4v_id,
 703         .prom_addr = 0x1fff0000000ULL,
 704         .console_serial_base = 0,
 705     },
 706 };
 707
 708 /* Sun4u hardware initialisation */
 709 static void sun4u_init(MachineState *machine)
 710 {
 711     sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
 712 }
 713
 714 /* Sun4v hardware initialisation */
 715 static void sun4v_init(MachineState *machine)
 716 {
 717     sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
 718 }
 719
 720 static void sun4u_class_init(ObjectClass *oc, void *data)
 721 {
 722     MachineClass *mc = MACHINE_CLASS(oc);
 723
 724     mc->desc = "Sun4u platform";
 725     mc->init = sun4u_init;
 726     mc->block_default_type = IF_IDE;
 727     mc->max_cpus = 1; /* XXX for now */
 728     mc->is_default = 1;
 729     mc->default_boot_order = "c";
 730     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
 731 }
 732
 733 static const TypeInfo sun4u_type = {
 734     .name = MACHINE_TYPE_NAME("sun4u"),
 735     .parent = TYPE_MACHINE,
 736     .class_init = sun4u_class_init,
 737 };
 738
 739 static void sun4v_class_init(ObjectClass *oc, void *data)
 740 {
 741     MachineClass *mc = MACHINE_CLASS(oc);
 742
 743     mc->desc = "Sun4v platform";
 744     mc->init = sun4v_init;
 745     mc->block_default_type = IF_IDE;
 746     mc->max_cpus = 1; /* XXX for now */
 747     mc->default_boot_order = "c";
 748     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
 749 }
 750
 751 static const TypeInfo sun4v_type = {
 752     .name = MACHINE_TYPE_NAME("sun4v"),
 753     .parent = TYPE_MACHINE,
 754     .class_init = sun4v_class_init,
 755 };
 756
 757 static void sun4u_register_types(void)
 758 {
 759     type_register_static(&power_info);
 760     type_register_static(&ebus_info);
 761     type_register_static(&prom_info);
 762     type_register_static(&ram_info);
 763
 764     type_register_static(&sun4u_type);
 765     type_register_static(&sun4v_type);
 766 }
 767
 768 type_init(sun4u_register_types)