hw/sparc64/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "qemu/error-report.h"
  28 #include "qapi/error.h"
  29 #include "qemu-common.h"
  30 #include "cpu.h"
  31 #include "hw/pci/pci.h"
  32 #include "hw/pci/pci_bridge.h"
  33 #include "hw/pci/pci_bus.h"
  34 #include "hw/pci/pci_host.h"
  35 #include "hw/qdev-properties.h"
  36 #include "hw/pci-host/sabre.h"
  37 #include "hw/char/serial.h"
  38 #include "hw/char/parallel.h"
  39 #include "hw/rtc/m48t59.h"
  40 #include "migration/vmstate.h"
  41 #include "hw/input/i8042.h"
  42 #include "hw/block/fdc.h"
  43 #include "net/net.h"
  44 #include "qemu/timer.h"
  45 #include "sysemu/runstate.h"
  46 #include "sysemu/sysemu.h"
  47 #include "hw/boards.h"
  48 #include "hw/nvram/sun_nvram.h"
  49 #include "hw/nvram/chrp_nvram.h"
  50 #include "hw/sparc/sparc64.h"
  51 #include "hw/nvram/fw_cfg.h"
  52 #include "hw/sysbus.h"
  53 #include "hw/ide/pci.h"
  54 #include "hw/loader.h"
  55 #include "hw/fw-path-provider.h"
  56 #include "elf.h"
  57 #include "trace.h"
  58 #include "qom/object.h"
  59
  60 #define KERNEL_LOAD_ADDR     0x00404000
  61 #define CMDLINE_ADDR         0x003ff000
  62 #define PROM_SIZE_MAX        (4 * MiB)
  63 #define PROM_VADDR           0x000ffd00000ULL
  64 #define PBM_SPECIAL_BASE     0x1fe00000000ULL
  65 #define PBM_MEM_BASE         0x1ff00000000ULL
  66 #define PBM_PCI_IO_BASE      (PBM_SPECIAL_BASE + 0x02000000ULL)
  67 #define PROM_FILENAME        "openbios-sparc64"
  68 #define NVRAM_SIZE           0x2000
  69 #define MAX_IDE_BUS          2
  70 #define BIOS_CFG_IOPORT      0x510
  71 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  72 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  73 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  74
  75 #define IVEC_MAX             0x40
  76
  77 struct hwdef {
  78     uint16_t machine_id;
  79     uint64_t prom_addr;
  80     uint64_t console_serial_base;
  81 };
  82
  83 struct EbusState {
  84     /*< private >*/
  85     PCIDevice parent_obj;
  86
  87     ISABus *isa_bus;
  88     qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
  89     uint64_t console_serial_base;
  90     MemoryRegion bar0;
  91     MemoryRegion bar1;
  92 };
  93 typedef struct EbusState EbusState;
  94
  95 #define TYPE_EBUS "ebus"
  96 DECLARE_INSTANCE_CHECKER(EbusState, EBUS,
  97                          TYPE_EBUS)
  98
  99 const char *fw_cfg_arch_key_name(uint16_t key)
 100 {
 101     static const struct {
 102         uint16_t key;
 103         const char *name;
 104     } fw_cfg_arch_wellknown_keys[] = {
 105         {FW_CFG_SPARC64_WIDTH, "width"},
 106         {FW_CFG_SPARC64_HEIGHT, "height"},
 107         {FW_CFG_SPARC64_DEPTH, "depth"},
 108     };
 109
 110     for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
 111         if (fw_cfg_arch_wellknown_keys[i].key == key) {
 112             return fw_cfg_arch_wellknown_keys[i].name;
 113         }
 114     }
 115     return NULL;
 116 }
 117
 118 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
 119                             Error **errp)
 120 {
 121     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 122 }
 123
 124 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
 125                                   const char *arch, ram_addr_t RAM_size,
 126                                   const char *boot_devices,
 127                                   uint32_t kernel_image, uint32_t kernel_size,
 128                                   const char *cmdline,
 129                                   uint32_t initrd_image, uint32_t initrd_size,
 130                                   uint32_t NVRAM_image,
 131                                   int width, int height, int depth,
 132                                   const uint8_t *macaddr)
 133 {
 134     unsigned int i;
 135     int sysp_end;
 136     uint8_t image[0x1ff0];
 137     NvramClass *k = NVRAM_GET_CLASS(nvram);
 138
 139     memset(image, '\0', sizeof(image));
 140
 141     /* OpenBIOS nvram variables partition */
 142     sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
 143
 144     /* Free space partition */
 145     chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
 146
 147     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 148
 149     for (i = 0; i < sizeof(image); i++) {
 150         (k->write)(nvram, i, image[i]);
 151     }
 152
 153     return 0;
 154 }
 155
 156 static uint64_t sun4u_load_kernel(const char *kernel_filename,
 157                                   const char *initrd_filename,
 158                                   ram_addr_t RAM_size, uint64_t *initrd_size,
 159                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
 160                                   uint64_t *kernel_entry)
 161 {
 162     int linux_boot;
 163     unsigned int i;
 164     long kernel_size;
 165     uint8_t *ptr;
 166     uint64_t kernel_top = 0;
 167
 168     linux_boot = (kernel_filename != NULL);
 169
 170     kernel_size = 0;
 171     if (linux_boot) {
 172         int bswap_needed;
 173
 174 #ifdef BSWAP_NEEDED
 175         bswap_needed = 1;
 176 #else
 177         bswap_needed = 0;
 178 #endif
 179         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry,
 180                                kernel_addr, &kernel_top, NULL, 1, EM_SPARCV9, 0,
 181                                0);
 182         if (kernel_size < 0) {
 183             *kernel_addr = KERNEL_LOAD_ADDR;
 184             *kernel_entry = KERNEL_LOAD_ADDR;
 185             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 186                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 187                                     TARGET_PAGE_SIZE);
 188         }
 189         if (kernel_size < 0) {
 190             kernel_size = load_image_targphys(kernel_filename,
 191                                               KERNEL_LOAD_ADDR,
 192                                               RAM_size - KERNEL_LOAD_ADDR);
 193         }
 194         if (kernel_size < 0) {
 195             error_report("could not load kernel '%s'", kernel_filename);
 196             exit(1);
 197         }
 198         /* load initrd above kernel */
 199         *initrd_size = 0;
 200         if (initrd_filename && kernel_top) {
 201             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
 202
 203             *initrd_size = load_image_targphys(initrd_filename,
 204                                                *initrd_addr,
 205                                                RAM_size - *initrd_addr);
 206             if ((int)*initrd_size < 0) {
 207                 error_report("could not load initial ram disk '%s'",
 208                              initrd_filename);
 209                 exit(1);
 210             }
 211         }
 212         if (*initrd_size > 0) {
 213             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 214                 ptr = rom_ptr(*kernel_addr + i, 32);
 215                 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 216                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
 217                     stl_p(ptr + 28, *initrd_size);
 218                     break;
 219                 }
 220             }
 221         }
 222     }
 223     return kernel_size;
 224 }
 225
 226 typedef struct ResetData {
 227     SPARCCPU *cpu;
 228     uint64_t prom_addr;
 229 } ResetData;
 230
 231 #define TYPE_SUN4U_POWER "power"
 232 typedef struct PowerDevice PowerDevice;
 233 DECLARE_INSTANCE_CHECKER(PowerDevice, SUN4U_POWER,
 234                          TYPE_SUN4U_POWER)
 235
 236 struct PowerDevice {
 237     SysBusDevice parent_obj;
 238
 239     MemoryRegion power_mmio;
 240 };
 241
 242 /* Power */
 243 static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
 244 {
 245     return 0;
 246 }
 247
 248 static void power_mem_write(void *opaque, hwaddr addr,
 249                             uint64_t val, unsigned size)
 250 {
 251     /* According to a real Ultra 5, bit 24 controls the power */
 252     if (val & 0x1000000) {
 253         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 254     }
 255 }
 256
 257 static const MemoryRegionOps power_mem_ops = {
 258     .read = power_mem_read,
 259     .write = power_mem_write,
 260     .endianness = DEVICE_NATIVE_ENDIAN,
 261     .valid = {
 262         .min_access_size = 4,
 263         .max_access_size = 4,
 264     },
 265 };
 266
 267 static void power_realize(DeviceState *dev, Error **errp)
 268 {
 269     PowerDevice *d = SUN4U_POWER(dev);
 270     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 271
 272     memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
 273                           "power", sizeof(uint32_t));
 274
 275     sysbus_init_mmio(sbd, &d->power_mmio);
 276 }
 277
 278 static void power_class_init(ObjectClass *klass, void *data)
 279 {
 280     DeviceClass *dc = DEVICE_CLASS(klass);
 281
 282     dc->realize = power_realize;
 283 }
 284
 285 static const TypeInfo power_info = {
 286     .name          = TYPE_SUN4U_POWER,
 287     .parent        = TYPE_SYS_BUS_DEVICE,
 288     .instance_size = sizeof(PowerDevice),
 289     .class_init    = power_class_init,
 290 };
 291
 292 static void ebus_isa_irq_handler(void *opaque, int n, int level)
 293 {
 294     EbusState *s = EBUS(opaque);
 295     qemu_irq irq = s->isa_bus_irqs[n];
 296
 297     /* Pass ISA bus IRQs onto their gpio equivalent */
 298     trace_ebus_isa_irq_handler(n, level);
 299     if (irq) {
 300         qemu_set_irq(irq, level);
 301     }
 302 }
 303
 304 /* EBUS (Eight bit bus) bridge */
 305 static void ebus_realize(PCIDevice *pci_dev, Error **errp)
 306 {
 307     EbusState *s = EBUS(pci_dev);
 308     ISADevice *isa_dev;
 309     SysBusDevice *sbd;
 310     DeviceState *dev;
 311     qemu_irq *isa_irq;
 312     DriveInfo *fd[MAX_FD];
 313     int i;
 314
 315     s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
 316                              pci_address_space_io(pci_dev), errp);
 317     if (!s->isa_bus) {
 318         error_setg(errp, "unable to instantiate EBUS ISA bus");
 319         return;
 320     }
 321
 322     /* ISA bus */
 323     isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
 324     isa_bus_irqs(s->isa_bus, isa_irq);
 325     qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
 326                              ISA_NUM_IRQS);
 327
 328     /* Serial ports */
 329     i = 0;
 330     if (s->console_serial_base) {
 331         serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
 332                        0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
 333         i++;
 334     }
 335     serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
 336
 337     /* Parallel ports */
 338     parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
 339
 340     /* Keyboard */
 341     isa_create_simple(s->isa_bus, "i8042");
 342
 343     /* Floppy */
 344     for (i = 0; i < MAX_FD; i++) {
 345         fd[i] = drive_get(IF_FLOPPY, 0, i);
 346     }
 347     isa_dev = isa_new(TYPE_ISA_FDC);
 348     dev = DEVICE(isa_dev);
 349     qdev_prop_set_uint32(dev, "dma", -1);
 350     isa_realize_and_unref(isa_dev, s->isa_bus, &error_fatal);
 351     isa_fdc_init_drives(isa_dev, fd);
 352
 353     /* Power */
 354     dev = qdev_new(TYPE_SUN4U_POWER);
 355     sbd = SYS_BUS_DEVICE(dev);
 356     sysbus_realize_and_unref(sbd, &error_fatal);
 357     memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
 358                                 sysbus_mmio_get_region(sbd, 0));
 359
 360     /* PCI */
 361     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 362     pci_dev->config[0x05] = 0x00;
 363     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 364     pci_dev->config[0x07] = 0x03; // status = medium devsel
 365     pci_dev->config[0x09] = 0x00; // programming i/f
 366     pci_dev->config[0x0D] = 0x0a; // latency_timer
 367
 368     memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
 369                              0, 0x1000000);
 370     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 371     memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
 372                              0, 0x8000);
 373     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
 374 }
 375
 376 static Property ebus_properties[] = {
 377     DEFINE_PROP_UINT64("console-serial-base", EbusState,
 378                        console_serial_base, 0),
 379     DEFINE_PROP_END_OF_LIST(),
 380 };
 381
 382 static void ebus_class_init(ObjectClass *klass, void *data)
 383 {
 384     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 385     DeviceClass *dc = DEVICE_CLASS(klass);
 386
 387     k->realize = ebus_realize;
 388     k->vendor_id = PCI_VENDOR_ID_SUN;
 389     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 390     k->revision = 0x01;
 391     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 392     device_class_set_props(dc, ebus_properties);
 393 }
 394
 395 static const TypeInfo ebus_info = {
 396     .name          = TYPE_EBUS,
 397     .parent        = TYPE_PCI_DEVICE,
 398     .class_init    = ebus_class_init,
 399     .instance_size = sizeof(EbusState),
 400     .interfaces = (InterfaceInfo[]) {
 401         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 402         { },
 403     },
 404 };
 405
 406 #define TYPE_OPENPROM "openprom"
 407 typedef struct PROMState PROMState;
 408 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM,
 409                          TYPE_OPENPROM)
 410
 411 struct PROMState {
 412     SysBusDevice parent_obj;
 413
 414     MemoryRegion prom;
 415 };
 416
 417 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 418 {
 419     hwaddr *base_addr = (hwaddr *)opaque;
 420     return addr + *base_addr - PROM_VADDR;
 421 }
 422
 423 /* Boot PROM (OpenBIOS) */
 424 static void prom_init(hwaddr addr, const char *bios_name)
 425 {
 426     DeviceState *dev;
 427     SysBusDevice *s;
 428     char *filename;
 429     int ret;
 430
 431     dev = qdev_new(TYPE_OPENPROM);
 432     s = SYS_BUS_DEVICE(dev);
 433     sysbus_realize_and_unref(s, &error_fatal);
 434
 435     sysbus_mmio_map(s, 0, addr);
 436
 437     /* load boot prom */
 438     if (bios_name == NULL) {
 439         bios_name = PROM_FILENAME;
 440     }
 441     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 442     if (filename) {
 443         ret = load_elf(filename, NULL, translate_prom_address, &addr,
 444                        NULL, NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
 445         if (ret < 0 || ret > PROM_SIZE_MAX) {
 446             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 447         }
 448         g_free(filename);
 449     } else {
 450         ret = -1;
 451     }
 452     if (ret < 0 || ret > PROM_SIZE_MAX) {
 453         error_report("could not load prom '%s'", bios_name);
 454         exit(1);
 455     }
 456 }
 457
 458 static void prom_realize(DeviceState *ds, Error **errp)
 459 {
 460     PROMState *s = OPENPROM(ds);
 461     SysBusDevice *dev = SYS_BUS_DEVICE(ds);
 462     Error *local_err = NULL;
 463
 464     memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
 465                                      PROM_SIZE_MAX, &local_err);
 466     if (local_err) {
 467         error_propagate(errp, local_err);
 468         return;
 469     }
 470
 471     vmstate_register_ram_global(&s->prom);
 472     memory_region_set_readonly(&s->prom, true);
 473     sysbus_init_mmio(dev, &s->prom);
 474 }
 475
 476 static Property prom_properties[] = {
 477     {/* end of property list */},
 478 };
 479
 480 static void prom_class_init(ObjectClass *klass, void *data)
 481 {
 482     DeviceClass *dc = DEVICE_CLASS(klass);
 483
 484     device_class_set_props(dc, prom_properties);
 485     dc->realize = prom_realize;
 486 }
 487
 488 static const TypeInfo prom_info = {
 489     .name          = TYPE_OPENPROM,
 490     .parent        = TYPE_SYS_BUS_DEVICE,
 491     .instance_size = sizeof(PROMState),
 492     .class_init    = prom_class_init,
 493 };
 494
 495
 496 #define TYPE_SUN4U_MEMORY "memory"
 497 typedef struct RamDevice RamDevice;
 498 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4U_RAM,
 499                          TYPE_SUN4U_MEMORY)
 500
 501 struct RamDevice {
 502     SysBusDevice parent_obj;
 503
 504     MemoryRegion ram;
 505     uint64_t size;
 506 };
 507
 508 /* System RAM */
 509 static void ram_realize(DeviceState *dev, Error **errp)
 510 {
 511     RamDevice *d = SUN4U_RAM(dev);
 512     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 513
 514     memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
 515                            &error_fatal);
 516     vmstate_register_ram_global(&d->ram);
 517     sysbus_init_mmio(sbd, &d->ram);
 518 }
 519
 520 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
 521 {
 522     DeviceState *dev;
 523     SysBusDevice *s;
 524     RamDevice *d;
 525
 526     /* allocate RAM */
 527     dev = qdev_new(TYPE_SUN4U_MEMORY);
 528     s = SYS_BUS_DEVICE(dev);
 529
 530     d = SUN4U_RAM(dev);
 531     d->size = RAM_size;
 532     sysbus_realize_and_unref(s, &error_fatal);
 533
 534     sysbus_mmio_map(s, 0, addr);
 535 }
 536
 537 static Property ram_properties[] = {
 538     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 539     DEFINE_PROP_END_OF_LIST(),
 540 };
 541
 542 static void ram_class_init(ObjectClass *klass, void *data)
 543 {
 544     DeviceClass *dc = DEVICE_CLASS(klass);
 545
 546     dc->realize = ram_realize;
 547     device_class_set_props(dc, ram_properties);
 548 }
 549
 550 static const TypeInfo ram_info = {
 551     .name          = TYPE_SUN4U_MEMORY,
 552     .parent        = TYPE_SYS_BUS_DEVICE,
 553     .instance_size = sizeof(RamDevice),
 554     .class_init    = ram_class_init,
 555 };
 556
 557 static void sun4uv_init(MemoryRegion *address_space_mem,
 558                         MachineState *machine,
 559                         const struct hwdef *hwdef)
 560 {
 561     SPARCCPU *cpu;
 562     Nvram *nvram;
 563     unsigned int i;
 564     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
 565     SabreState *sabre;
 566     PCIBus *pci_bus, *pci_busA, *pci_busB;
 567     PCIDevice *ebus, *pci_dev;
 568     SysBusDevice *s;
 569     DeviceState *iommu, *dev;
 570     FWCfgState *fw_cfg;
 571     NICInfo *nd;
 572     MACAddr macaddr;
 573     bool onboard_nic;
 574
 575     /* init CPUs */
 576     cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
 577
 578     /* IOMMU */
 579     iommu = qdev_new(TYPE_SUN4U_IOMMU);
 580     sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu), &error_fatal);
 581
 582     /* set up devices */
 583     ram_init(0, machine->ram_size);
 584
 585     prom_init(hwdef->prom_addr, bios_name);
 586
 587     /* Init sabre (PCI host bridge) */
 588     sabre = SABRE(qdev_new(TYPE_SABRE));
 589     qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
 590     qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
 591     object_property_set_link(OBJECT(sabre), "iommu", OBJECT(iommu),
 592                              &error_abort);
 593     sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal);
 594
 595     /* Wire up PCI interrupts to CPU */
 596     for (i = 0; i < IVEC_MAX; i++) {
 597         qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
 598             qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
 599     }
 600
 601     pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
 602     pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
 603     pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
 604
 605     /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
 606        reserved (leaving no slots free after on-board devices) however slots
 607        0-3 are free on busB */
 608     pci_bus->slot_reserved_mask = 0xfffffffc;
 609     pci_busA->slot_reserved_mask = 0xfffffff1;
 610     pci_busB->slot_reserved_mask = 0xfffffff0;
 611
 612     ebus = pci_new_multifunction(PCI_DEVFN(1, 0), true, TYPE_EBUS);
 613     qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
 614                          hwdef->console_serial_base);
 615     pci_realize_and_unref(ebus, pci_busA, &error_fatal);
 616
 617     /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
 618     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
 619         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
 620     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
 621         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
 622     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
 623         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
 624     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
 625         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
 626     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
 627         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
 628
 629     switch (vga_interface_type) {
 630     case VGA_STD:
 631         pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
 632         break;
 633     case VGA_NONE:
 634         break;
 635     default:
 636         abort();   /* Should not happen - types are checked in vl.c already */
 637     }
 638
 639     memset(&macaddr, 0, sizeof(MACAddr));
 640     onboard_nic = false;
 641     for (i = 0; i < nb_nics; i++) {
 642         PCIBus *bus;
 643         nd = &nd_table[i];
 644
 645         if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
 646             if (!onboard_nic) {
 647                 pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1),
 648                                                    true, "sunhme");
 649                 bus = pci_busA;
 650                 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
 651                 onboard_nic = true;
 652             } else {
 653                 pci_dev = pci_new(-1, "sunhme");
 654                 bus = pci_busB;
 655             }
 656         } else {
 657             pci_dev = pci_new(-1, nd->model);
 658             bus = pci_busB;
 659         }
 660
 661         dev = &pci_dev->qdev;
 662         qdev_set_nic_properties(dev, nd);
 663         pci_realize_and_unref(pci_dev, bus, &error_fatal);
 664     }
 665
 666     /* If we don't have an onboard NIC, grab a default MAC address so that
 667      * we have a valid machine id */
 668     if (!onboard_nic) {
 669         qemu_macaddr_default_if_unset(&macaddr);
 670     }
 671
 672     pci_dev = pci_new(PCI_DEVFN(3, 0), "cmd646-ide");
 673     qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
 674     pci_realize_and_unref(pci_dev, pci_busA, &error_fatal);
 675     pci_ide_create_devs(pci_dev);
 676
 677     /* Map NVRAM into I/O (ebus) space */
 678     nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
 679     s = SYS_BUS_DEVICE(nvram);
 680     memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
 681                                 sysbus_mmio_get_region(s, 0));
 682
 683     initrd_size = 0;
 684     initrd_addr = 0;
 685     kernel_size = sun4u_load_kernel(machine->kernel_filename,
 686                                     machine->initrd_filename,
 687                                     ram_size, &initrd_size, &initrd_addr,
 688                                     &kernel_addr, &kernel_entry);
 689
 690     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
 691                            machine->boot_order,
 692                            kernel_addr, kernel_size,
 693                            machine->kernel_cmdline,
 694                            initrd_addr, initrd_size,
 695                            /* XXX: need an option to load a NVRAM image */
 696                            0,
 697                            graphic_width, graphic_height, graphic_depth,
 698                            (uint8_t *)&macaddr);
 699
 700     dev = qdev_new(TYPE_FW_CFG_IO);
 701     qdev_prop_set_bit(dev, "dma_enabled", false);
 702     object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev));
 703     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 704     memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
 705                                 &FW_CFG_IO(dev)->comb_iomem);
 706
 707     fw_cfg = FW_CFG(dev);
 708     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
 709     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
 710     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 711     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 712     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
 713     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 714     if (machine->kernel_cmdline) {
 715         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 716                        strlen(machine->kernel_cmdline) + 1);
 717         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
 718     } else {
 719         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 720     }
 721     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 722     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 723     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
 724
 725     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 726     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 727     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 728
 729     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 730 }
 731
 732 enum {
 733     sun4u_id = 0,
 734     sun4v_id = 64,
 735 };
 736
 737 /*
 738  * Implementation of an interface to adjust firmware path
 739  * for the bootindex property handling.
 740  */
 741 static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
 742                                DeviceState *dev)
 743 {
 744     PCIDevice *pci;
 745     IDEBus *ide_bus;
 746     IDEState *ide_s;
 747     int bus_id;
 748
 749     if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
 750         pci = PCI_DEVICE(dev);
 751
 752         if (PCI_FUNC(pci->devfn)) {
 753             return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
 754                                    PCI_FUNC(pci->devfn));
 755         } else {
 756             return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
 757         }
 758     }
 759
 760     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
 761          ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
 762          ide_s = idebus_active_if(ide_bus);
 763          bus_id = ide_bus->bus_id;
 764
 765          if (ide_s->drive_kind == IDE_CD) {
 766              return g_strdup_printf("ide@%x/cdrom", bus_id);
 767          }
 768
 769          return g_strdup_printf("ide@%x/disk", bus_id);
 770     }
 771
 772     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
 773         return g_strdup("disk");
 774     }
 775
 776     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
 777         return g_strdup("cdrom");
 778     }
 779
 780     if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
 781         return g_strdup("disk");
 782     }
 783
 784     return NULL;
 785 }
 786
 787 static const struct hwdef hwdefs[] = {
 788     /* Sun4u generic PC-like machine */
 789     {
 790         .machine_id = sun4u_id,
 791         .prom_addr = 0x1fff0000000ULL,
 792         .console_serial_base = 0,
 793     },
 794     /* Sun4v generic PC-like machine */
 795     {
 796         .machine_id = sun4v_id,
 797         .prom_addr = 0x1fff0000000ULL,
 798         .console_serial_base = 0,
 799     },
 800 };
 801
 802 /* Sun4u hardware initialisation */
 803 static void sun4u_init(MachineState *machine)
 804 {
 805     sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
 806 }
 807
 808 /* Sun4v hardware initialisation */
 809 static void sun4v_init(MachineState *machine)
 810 {
 811     sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
 812 }
 813
 814 static void sun4u_class_init(ObjectClass *oc, void *data)
 815 {
 816     MachineClass *mc = MACHINE_CLASS(oc);
 817     FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
 818
 819     mc->desc = "Sun4u platform";
 820     mc->init = sun4u_init;
 821     mc->block_default_type = IF_IDE;
 822     mc->max_cpus = 1; /* XXX for now */
 823     mc->is_default = true;
 824     mc->default_boot_order = "c";
 825     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
 826     mc->ignore_boot_device_suffixes = true;
 827     mc->default_display = "std";
 828     fwc->get_dev_path = sun4u_fw_dev_path;
 829 }
 830
 831 static const TypeInfo sun4u_type = {
 832     .name = MACHINE_TYPE_NAME("sun4u"),
 833     .parent = TYPE_MACHINE,
 834     .class_init = sun4u_class_init,
 835     .interfaces = (InterfaceInfo[]) {
 836         { TYPE_FW_PATH_PROVIDER },
 837         { }
 838     },
 839 };
 840
 841 static void sun4v_class_init(ObjectClass *oc, void *data)
 842 {
 843     MachineClass *mc = MACHINE_CLASS(oc);
 844
 845     mc->desc = "Sun4v platform";
 846     mc->init = sun4v_init;
 847     mc->block_default_type = IF_IDE;
 848     mc->max_cpus = 1; /* XXX for now */
 849     mc->default_boot_order = "c";
 850     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
 851     mc->default_display = "std";
 852 }
 853
 854 static const TypeInfo sun4v_type = {
 855     .name = MACHINE_TYPE_NAME("sun4v"),
 856     .parent = TYPE_MACHINE,
 857     .class_init = sun4v_class_init,
 858 };
 859
 860 static void sun4u_register_types(void)
 861 {
 862     type_register_static(&power_info);
 863     type_register_static(&ebus_info);
 864     type_register_static(&prom_info);
 865     type_register_static(&ram_info);
 866
 867     type_register_static(&sun4u_type);
 868     type_register_static(&sun4v_type);
 869 }
 870
 871 type_init(sun4u_register_types)