2 * QEMU Sun4u/Sun4v System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/error-report.h"
28 #include "qapi/error.h"
29 #include "qemu/datadir.h"
32 #include "hw/pci/pci.h"
33 #include "hw/pci/pci_bridge.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/qdev-properties.h"
36 #include "hw/pci-host/sabre.h"
37 #include "hw/char/serial.h"
38 #include "hw/char/parallel-isa.h"
39 #include "hw/rtc/m48t59.h"
40 #include "migration/vmstate.h"
41 #include "hw/input/i8042.h"
42 #include "hw/block/fdc.h"
44 #include "qemu/timer.h"
45 #include "sysemu/runstate.h"
46 #include "sysemu/sysemu.h"
47 #include "hw/boards.h"
48 #include "hw/nvram/sun_nvram.h"
49 #include "hw/nvram/chrp_nvram.h"
50 #include "hw/sparc/sparc64.h"
51 #include "hw/nvram/fw_cfg.h"
52 #include "hw/sysbus.h"
53 #include "hw/ide/pci.h"
54 #include "hw/loader.h"
55 #include "hw/fw-path-provider.h"
58 #include "qom/object.h"
60 #define KERNEL_LOAD_ADDR 0x00404000
61 #define CMDLINE_ADDR 0x003ff000
62 #define PROM_SIZE_MAX (4 * MiB)
63 #define PROM_VADDR 0x000ffd00000ULL
64 #define PBM_SPECIAL_BASE 0x1fe00000000ULL
65 #define PBM_MEM_BASE 0x1ff00000000ULL
66 #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
67 #define PROM_FILENAME "openbios-sparc64"
68 #define NVRAM_SIZE 0x2000
69 #define BIOS_CFG_IOPORT 0x510
70 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
71 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
72 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
79 uint64_t console_serial_base
;
87 qemu_irq
*isa_irqs_in
;
88 qemu_irq isa_irqs_out
[ISA_NUM_IRQS
];
89 uint64_t console_serial_base
;
94 #define TYPE_EBUS "ebus"
95 OBJECT_DECLARE_SIMPLE_TYPE(EbusState
, EBUS
)
97 const char *fw_cfg_arch_key_name(uint16_t key
)
102 } fw_cfg_arch_wellknown_keys
[] = {
103 {FW_CFG_SPARC64_WIDTH
, "width"},
104 {FW_CFG_SPARC64_HEIGHT
, "height"},
105 {FW_CFG_SPARC64_DEPTH
, "depth"},
108 for (size_t i
= 0; i
< ARRAY_SIZE(fw_cfg_arch_wellknown_keys
); i
++) {
109 if (fw_cfg_arch_wellknown_keys
[i
].key
== key
) {
110 return fw_cfg_arch_wellknown_keys
[i
].name
;
116 static void fw_cfg_boot_set(void *opaque
, const char *boot_device
,
119 fw_cfg_modify_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
122 static int sun4u_NVRAM_set_params(Nvram
*nvram
, uint16_t NVRAM_size
,
123 const char *arch
, ram_addr_t RAM_size
,
124 const char *boot_devices
,
125 uint32_t kernel_image
, uint32_t kernel_size
,
127 uint32_t initrd_image
, uint32_t initrd_size
,
128 uint32_t NVRAM_image
,
129 int width
, int height
, int depth
,
130 const uint8_t *macaddr
)
134 uint8_t image
[0x1ff0];
135 NvramClass
*k
= NVRAM_GET_CLASS(nvram
);
137 memset(image
, '\0', sizeof(image
));
139 /* OpenBIOS nvram variables partition */
140 sysp_end
= chrp_nvram_create_system_partition(image
, 0, 0x1fd0);
142 /* Free space partition */
143 chrp_nvram_create_free_partition(&image
[sysp_end
], 0x1fd0 - sysp_end
);
145 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
, 0x80);
147 for (i
= 0; i
< sizeof(image
); i
++) {
148 (k
->write
)(nvram
, i
, image
[i
]);
154 static uint64_t sun4u_load_kernel(const char *kernel_filename
,
155 const char *initrd_filename
,
156 ram_addr_t RAM_size
, uint64_t *initrd_size
,
157 uint64_t *initrd_addr
, uint64_t *kernel_addr
,
158 uint64_t *kernel_entry
)
164 uint64_t kernel_top
= 0;
166 linux_boot
= (kernel_filename
!= NULL
);
177 kernel_size
= load_elf(kernel_filename
, NULL
, NULL
, NULL
, kernel_entry
,
178 kernel_addr
, &kernel_top
, NULL
, 1, EM_SPARCV9
, 0,
180 if (kernel_size
< 0) {
181 *kernel_addr
= KERNEL_LOAD_ADDR
;
182 *kernel_entry
= KERNEL_LOAD_ADDR
;
183 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
184 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
187 if (kernel_size
< 0) {
188 kernel_size
= load_image_targphys(kernel_filename
,
190 RAM_size
- KERNEL_LOAD_ADDR
);
192 if (kernel_size
< 0) {
193 error_report("could not load kernel '%s'", kernel_filename
);
196 /* load initrd above kernel */
198 if (initrd_filename
&& kernel_top
) {
199 *initrd_addr
= TARGET_PAGE_ALIGN(kernel_top
);
201 *initrd_size
= load_image_targphys(initrd_filename
,
203 RAM_size
- *initrd_addr
);
204 if ((int)*initrd_size
< 0) {
205 error_report("could not load initial ram disk '%s'",
210 if (*initrd_size
> 0) {
211 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
212 ptr
= rom_ptr(*kernel_addr
+ i
, 32);
213 if (ptr
&& ldl_p(ptr
+ 8) == 0x48647253) { /* HdrS */
214 stl_p(ptr
+ 24, *initrd_addr
+ *kernel_addr
);
215 stl_p(ptr
+ 28, *initrd_size
);
224 typedef struct ResetData
{
229 #define TYPE_SUN4U_POWER "power"
230 OBJECT_DECLARE_SIMPLE_TYPE(PowerDevice
, SUN4U_POWER
)
233 SysBusDevice parent_obj
;
235 MemoryRegion power_mmio
;
239 static uint64_t power_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
244 static void power_mem_write(void *opaque
, hwaddr addr
,
245 uint64_t val
, unsigned size
)
247 /* According to a real Ultra 5, bit 24 controls the power */
248 if (val
& 0x1000000) {
249 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN
);
253 static const MemoryRegionOps power_mem_ops
= {
254 .read
= power_mem_read
,
255 .write
= power_mem_write
,
256 .endianness
= DEVICE_NATIVE_ENDIAN
,
258 .min_access_size
= 4,
259 .max_access_size
= 4,
263 static void power_realize(DeviceState
*dev
, Error
**errp
)
265 PowerDevice
*d
= SUN4U_POWER(dev
);
266 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
268 memory_region_init_io(&d
->power_mmio
, OBJECT(dev
), &power_mem_ops
, d
,
269 "power", sizeof(uint32_t));
271 sysbus_init_mmio(sbd
, &d
->power_mmio
);
274 static void power_class_init(ObjectClass
*klass
, void *data
)
276 DeviceClass
*dc
= DEVICE_CLASS(klass
);
278 dc
->realize
= power_realize
;
281 static const TypeInfo power_info
= {
282 .name
= TYPE_SUN4U_POWER
,
283 .parent
= TYPE_SYS_BUS_DEVICE
,
284 .instance_size
= sizeof(PowerDevice
),
285 .class_init
= power_class_init
,
288 static void ebus_isa_irq_handler(void *opaque
, int n
, int level
)
290 EbusState
*s
= EBUS(opaque
);
291 qemu_irq irq
= s
->isa_irqs_out
[n
];
293 /* Pass ISA bus IRQs onto their gpio equivalent */
294 trace_ebus_isa_irq_handler(n
, level
);
296 qemu_set_irq(irq
, level
);
300 /* EBUS (Eight bit bus) bridge */
301 static void ebus_realize(PCIDevice
*pci_dev
, Error
**errp
)
303 EbusState
*s
= EBUS(pci_dev
);
307 DriveInfo
*fd
[MAX_FD
];
310 s
->isa_bus
= isa_bus_new(DEVICE(pci_dev
), get_system_memory(),
311 pci_address_space_io(pci_dev
), errp
);
313 error_setg(errp
, "unable to instantiate EBUS ISA bus");
318 s
->isa_irqs_in
= qemu_allocate_irqs(ebus_isa_irq_handler
, s
, ISA_NUM_IRQS
);
319 isa_bus_register_input_irqs(s
->isa_bus
, s
->isa_irqs_in
);
320 qdev_init_gpio_out_named(DEVICE(s
), s
->isa_irqs_out
, "isa-irq",
325 if (s
->console_serial_base
) {
326 serial_mm_init(pci_address_space(pci_dev
), s
->console_serial_base
,
327 0, NULL
, 115200, serial_hd(i
), DEVICE_BIG_ENDIAN
);
330 serial_hds_isa_init(s
->isa_bus
, i
, MAX_ISA_SERIAL_PORTS
);
333 parallel_hds_isa_init(s
->isa_bus
, MAX_PARALLEL_PORTS
);
336 isa_create_simple(s
->isa_bus
, TYPE_I8042
);
339 for (i
= 0; i
< MAX_FD
; i
++) {
340 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
342 isa_dev
= isa_new(TYPE_ISA_FDC
);
343 dev
= DEVICE(isa_dev
);
344 qdev_prop_set_uint32(dev
, "dma", -1);
345 isa_realize_and_unref(isa_dev
, s
->isa_bus
, &error_fatal
);
346 isa_fdc_init_drives(isa_dev
, fd
);
349 dev
= qdev_new(TYPE_SUN4U_POWER
);
350 sbd
= SYS_BUS_DEVICE(dev
);
351 sysbus_realize_and_unref(sbd
, &error_fatal
);
352 memory_region_add_subregion(pci_address_space_io(pci_dev
), 0x7240,
353 sysbus_mmio_get_region(sbd
, 0));
356 pci_dev
->config
[0x04] = 0x06; // command = bus master, pci mem
357 pci_dev
->config
[0x05] = 0x00;
358 pci_dev
->config
[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
359 pci_dev
->config
[0x07] = 0x03; // status = medium devsel
360 pci_dev
->config
[0x09] = 0x00; // programming i/f
361 pci_dev
->config
[0x0D] = 0x0a; // latency_timer
364 * BAR0 is accessed by OpenBSD but not for ebus device access: allow any
365 * memory access to this region to succeed which allows the OpenBSD kernel
368 memory_region_init_io(&s
->bar0
, OBJECT(s
), &unassigned_io_ops
, s
,
370 pci_register_bar(pci_dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar0
);
371 memory_region_init_alias(&s
->bar1
, OBJECT(s
), "bar1",
372 pci_address_space_io(pci_dev
), 0, 0x8000);
373 pci_register_bar(pci_dev
, 1, PCI_BASE_ADDRESS_SPACE_IO
, &s
->bar1
);
376 static Property ebus_properties
[] = {
377 DEFINE_PROP_UINT64("console-serial-base", EbusState
,
378 console_serial_base
, 0),
379 DEFINE_PROP_END_OF_LIST(),
382 static void ebus_class_init(ObjectClass
*klass
, void *data
)
384 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
385 DeviceClass
*dc
= DEVICE_CLASS(klass
);
387 k
->realize
= ebus_realize
;
388 k
->vendor_id
= PCI_VENDOR_ID_SUN
;
389 k
->device_id
= PCI_DEVICE_ID_SUN_EBUS
;
391 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
392 device_class_set_props(dc
, ebus_properties
);
395 static const TypeInfo ebus_info
= {
397 .parent
= TYPE_PCI_DEVICE
,
398 .class_init
= ebus_class_init
,
399 .instance_size
= sizeof(EbusState
),
400 .interfaces
= (InterfaceInfo
[]) {
401 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
406 #define TYPE_OPENPROM "openprom"
407 typedef struct PROMState PROMState
;
408 DECLARE_INSTANCE_CHECKER(PROMState
, OPENPROM
,
412 SysBusDevice parent_obj
;
417 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
419 hwaddr
*base_addr
= (hwaddr
*)opaque
;
420 return addr
+ *base_addr
- PROM_VADDR
;
423 /* Boot PROM (OpenBIOS) */
424 static void prom_init(hwaddr addr
, const char *bios_name
)
431 dev
= qdev_new(TYPE_OPENPROM
);
432 s
= SYS_BUS_DEVICE(dev
);
433 sysbus_realize_and_unref(s
, &error_fatal
);
435 sysbus_mmio_map(s
, 0, addr
);
438 if (bios_name
== NULL
) {
439 bios_name
= PROM_FILENAME
;
441 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
443 ret
= load_elf(filename
, NULL
, translate_prom_address
, &addr
,
444 NULL
, NULL
, NULL
, NULL
, 1, EM_SPARCV9
, 0, 0);
445 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
446 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
452 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
453 error_report("could not load prom '%s'", bios_name
);
458 static void prom_realize(DeviceState
*ds
, Error
**errp
)
460 PROMState
*s
= OPENPROM(ds
);
461 SysBusDevice
*dev
= SYS_BUS_DEVICE(ds
);
463 if (!memory_region_init_ram_nomigrate(&s
->prom
, OBJECT(ds
), "sun4u.prom",
464 PROM_SIZE_MAX
, errp
)) {
468 vmstate_register_ram_global(&s
->prom
);
469 memory_region_set_readonly(&s
->prom
, true);
470 sysbus_init_mmio(dev
, &s
->prom
);
473 static Property prom_properties
[] = {
474 {/* end of property list */},
477 static void prom_class_init(ObjectClass
*klass
, void *data
)
479 DeviceClass
*dc
= DEVICE_CLASS(klass
);
481 device_class_set_props(dc
, prom_properties
);
482 dc
->realize
= prom_realize
;
485 static const TypeInfo prom_info
= {
486 .name
= TYPE_OPENPROM
,
487 .parent
= TYPE_SYS_BUS_DEVICE
,
488 .instance_size
= sizeof(PROMState
),
489 .class_init
= prom_class_init
,
493 #define TYPE_SUN4U_MEMORY "memory"
494 typedef struct RamDevice RamDevice
;
495 DECLARE_INSTANCE_CHECKER(RamDevice
, SUN4U_RAM
,
499 SysBusDevice parent_obj
;
506 static void ram_realize(DeviceState
*dev
, Error
**errp
)
508 RamDevice
*d
= SUN4U_RAM(dev
);
509 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
511 memory_region_init_ram_nomigrate(&d
->ram
, OBJECT(d
), "sun4u.ram", d
->size
,
513 vmstate_register_ram_global(&d
->ram
);
514 sysbus_init_mmio(sbd
, &d
->ram
);
517 static void ram_init(hwaddr addr
, ram_addr_t RAM_size
)
524 dev
= qdev_new(TYPE_SUN4U_MEMORY
);
525 s
= SYS_BUS_DEVICE(dev
);
529 sysbus_realize_and_unref(s
, &error_fatal
);
531 sysbus_mmio_map(s
, 0, addr
);
534 static Property ram_properties
[] = {
535 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
536 DEFINE_PROP_END_OF_LIST(),
539 static void ram_class_init(ObjectClass
*klass
, void *data
)
541 DeviceClass
*dc
= DEVICE_CLASS(klass
);
543 dc
->realize
= ram_realize
;
544 device_class_set_props(dc
, ram_properties
);
547 static const TypeInfo ram_info
= {
548 .name
= TYPE_SUN4U_MEMORY
,
549 .parent
= TYPE_SYS_BUS_DEVICE
,
550 .instance_size
= sizeof(RamDevice
),
551 .class_init
= ram_class_init
,
554 static void sun4uv_init(MemoryRegion
*address_space_mem
,
555 MachineState
*machine
,
556 const struct hwdef
*hwdef
)
558 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
562 uint64_t initrd_addr
, initrd_size
, kernel_addr
, kernel_size
, kernel_entry
;
564 PCIBus
*pci_bus
, *pci_busA
, *pci_busB
;
565 PCIDevice
*ebus
, *pci_dev
;
567 DeviceState
*iommu
, *dev
;
574 cpu
= sparc64_cpu_devinit(machine
->cpu_type
, hwdef
->prom_addr
);
577 iommu
= qdev_new(TYPE_SUN4U_IOMMU
);
578 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu
), &error_fatal
);
581 ram_init(0, machine
->ram_size
);
583 prom_init(hwdef
->prom_addr
, machine
->firmware
);
585 /* Init sabre (PCI host bridge) */
586 sabre
= SABRE(qdev_new(TYPE_SABRE
));
587 qdev_prop_set_uint64(DEVICE(sabre
), "special-base", PBM_SPECIAL_BASE
);
588 qdev_prop_set_uint64(DEVICE(sabre
), "mem-base", PBM_MEM_BASE
);
589 object_property_set_link(OBJECT(sabre
), "iommu", OBJECT(iommu
),
591 sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre
), &error_fatal
);
594 sysbus_mmio_map(SYS_BUS_DEVICE(sabre
), 0, PBM_SPECIAL_BASE
);
595 /* PCI configuration space */
596 sysbus_mmio_map(SYS_BUS_DEVICE(sabre
), 1, PBM_SPECIAL_BASE
+ 0x1000000ULL
);
598 sysbus_mmio_map(SYS_BUS_DEVICE(sabre
), 2, PBM_SPECIAL_BASE
+ 0x2000000ULL
);
600 /* Wire up PCI interrupts to CPU */
601 for (i
= 0; i
< IVEC_MAX
; i
++) {
602 qdev_connect_gpio_out_named(DEVICE(sabre
), "ivec-irq", i
,
603 qdev_get_gpio_in_named(DEVICE(cpu
), "ivec-irq", i
));
606 pci_bus
= PCI_HOST_BRIDGE(sabre
)->bus
;
607 pci_busA
= pci_bridge_get_sec_bus(sabre
->bridgeA
);
608 pci_busB
= pci_bridge_get_sec_bus(sabre
->bridgeB
);
610 /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
611 reserved (leaving no slots free after on-board devices) however slots
612 0-3 are free on busB */
613 pci_bus_set_slot_reserved_mask(pci_bus
, 0xfffffffc);
614 pci_bus_set_slot_reserved_mask(pci_busA
, 0xfffffff1);
615 pci_bus_set_slot_reserved_mask(pci_busB
, 0xfffffff0);
617 ebus
= pci_new_multifunction(PCI_DEVFN(1, 0), TYPE_EBUS
);
618 qdev_prop_set_uint64(DEVICE(ebus
), "console-serial-base",
619 hwdef
->console_serial_base
);
620 pci_realize_and_unref(ebus
, pci_busA
, &error_fatal
);
622 /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
623 qdev_connect_gpio_out_named(DEVICE(ebus
), "isa-irq", 7,
624 qdev_get_gpio_in_named(DEVICE(sabre
), "pbm-irq", OBIO_LPT_IRQ
));
625 qdev_connect_gpio_out_named(DEVICE(ebus
), "isa-irq", 6,
626 qdev_get_gpio_in_named(DEVICE(sabre
), "pbm-irq", OBIO_FDD_IRQ
));
627 qdev_connect_gpio_out_named(DEVICE(ebus
), "isa-irq", 1,
628 qdev_get_gpio_in_named(DEVICE(sabre
), "pbm-irq", OBIO_KBD_IRQ
));
629 qdev_connect_gpio_out_named(DEVICE(ebus
), "isa-irq", 12,
630 qdev_get_gpio_in_named(DEVICE(sabre
), "pbm-irq", OBIO_MSE_IRQ
));
631 qdev_connect_gpio_out_named(DEVICE(ebus
), "isa-irq", 4,
632 qdev_get_gpio_in_named(DEVICE(sabre
), "pbm-irq", OBIO_SER_IRQ
));
634 switch (vga_interface_type
) {
636 pci_create_simple(pci_busA
, PCI_DEVFN(2, 0), "VGA");
637 vga_interface_created
= true;
642 abort(); /* Should not happen - types are checked in vl.c already */
645 memset(&macaddr
, 0, sizeof(MACAddr
));
648 nd
= qemu_find_nic_info(mc
->default_nic
, true, NULL
);
650 pci_dev
= pci_new_multifunction(PCI_DEVFN(1, 1), mc
->default_nic
);
651 dev
= &pci_dev
->qdev
;
652 qdev_set_nic_properties(dev
, nd
);
653 pci_realize_and_unref(pci_dev
, pci_busA
, &error_fatal
);
655 memcpy(&macaddr
, &nd
->macaddr
.a
, sizeof(MACAddr
));
658 pci_init_nic_devices(pci_busB
, mc
->default_nic
);
660 /* If we don't have an onboard NIC, grab a default MAC address so that
661 * we have a valid machine id */
663 qemu_macaddr_default_if_unset(&macaddr
);
666 pci_dev
= pci_new(PCI_DEVFN(3, 0), "cmd646-ide");
667 qdev_prop_set_uint32(&pci_dev
->qdev
, "secondary", 1);
668 pci_realize_and_unref(pci_dev
, pci_busA
, &error_fatal
);
669 pci_ide_create_devs(pci_dev
);
671 /* Map NVRAM into I/O (ebus) space */
672 dev
= qdev_new("sysbus-m48t59");
673 qdev_prop_set_int32(dev
, "base-year", 1968);
674 s
= SYS_BUS_DEVICE(dev
);
675 sysbus_realize_and_unref(s
, &error_fatal
);
676 memory_region_add_subregion(pci_address_space_io(ebus
), 0x2000,
677 sysbus_mmio_get_region(s
, 0));
682 kernel_size
= sun4u_load_kernel(machine
->kernel_filename
,
683 machine
->initrd_filename
,
684 machine
->ram_size
, &initrd_size
, &initrd_addr
,
685 &kernel_addr
, &kernel_entry
);
687 sun4u_NVRAM_set_params(nvram
, NVRAM_SIZE
, "Sun4u", machine
->ram_size
,
688 machine
->boot_config
.order
,
689 kernel_addr
, kernel_size
,
690 machine
->kernel_cmdline
,
691 initrd_addr
, initrd_size
,
692 /* XXX: need an option to load a NVRAM image */
694 graphic_width
, graphic_height
, graphic_depth
,
695 (uint8_t *)&macaddr
);
697 dev
= qdev_new(TYPE_FW_CFG_IO
);
698 qdev_prop_set_bit(dev
, "dma_enabled", false);
699 object_property_add_child(OBJECT(ebus
), TYPE_FW_CFG
, OBJECT(dev
));
700 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
701 memory_region_add_subregion(pci_address_space_io(ebus
), BIOS_CFG_IOPORT
,
702 &FW_CFG_IO(dev
)->comb_iomem
);
704 fw_cfg
= FW_CFG(dev
);
705 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)machine
->smp
.cpus
);
706 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)machine
->smp
.max_cpus
);
707 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)machine
->ram_size
);
708 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
709 fw_cfg_add_i64(fw_cfg
, FW_CFG_KERNEL_ADDR
, kernel_entry
);
710 fw_cfg_add_i64(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
711 if (machine
->kernel_cmdline
) {
712 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
713 strlen(machine
->kernel_cmdline
) + 1);
714 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, machine
->kernel_cmdline
);
716 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
718 fw_cfg_add_i64(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
719 fw_cfg_add_i64(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
720 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, machine
->boot_config
.order
[0]);
722 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_WIDTH
, graphic_width
);
723 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_HEIGHT
, graphic_height
);
724 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_DEPTH
, graphic_depth
);
726 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
735 * Implementation of an interface to adjust firmware path
736 * for the bootindex property handling.
738 static char *sun4u_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
743 if (!strcmp(object_get_typename(OBJECT(dev
)), "pbm-bridge")) {
744 pci
= PCI_DEVICE(dev
);
746 if (PCI_FUNC(pci
->devfn
)) {
747 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci
->devfn
),
748 PCI_FUNC(pci
->devfn
));
750 return g_strdup_printf("pci@%x", PCI_SLOT(pci
->devfn
));
754 if (!strcmp(object_get_typename(OBJECT(dev
)), "ide-hd")) {
755 return g_strdup("disk");
758 if (!strcmp(object_get_typename(OBJECT(dev
)), "ide-cd")) {
759 return g_strdup("cdrom");
762 if (!strcmp(object_get_typename(OBJECT(dev
)), "virtio-blk-device")) {
763 return g_strdup("disk");
769 static const struct hwdef hwdefs
[] = {
770 /* Sun4u generic PC-like machine */
772 .machine_id
= sun4u_id
,
773 .prom_addr
= 0x1fff0000000ULL
,
774 .console_serial_base
= 0,
776 /* Sun4v generic PC-like machine */
778 .machine_id
= sun4v_id
,
779 .prom_addr
= 0x1fff0000000ULL
,
780 .console_serial_base
= 0,
784 /* Sun4u hardware initialisation */
785 static void sun4u_init(MachineState
*machine
)
787 sun4uv_init(get_system_memory(), machine
, &hwdefs
[0]);
790 /* Sun4v hardware initialisation */
791 static void sun4v_init(MachineState
*machine
)
793 sun4uv_init(get_system_memory(), machine
, &hwdefs
[1]);
796 static GlobalProperty hw_compat_sparc64
[] = {
797 { "virtio-pci", "disable-legacy", "on", .optional
= true },
798 { "virtio-device", "iommu_platform", "on" },
800 static const size_t hw_compat_sparc64_len
= G_N_ELEMENTS(hw_compat_sparc64
);
802 static void sun4u_class_init(ObjectClass
*oc
, void *data
)
804 MachineClass
*mc
= MACHINE_CLASS(oc
);
805 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
807 mc
->desc
= "Sun4u platform";
808 mc
->init
= sun4u_init
;
809 mc
->block_default_type
= IF_IDE
;
810 mc
->max_cpus
= 1; /* XXX for now */
811 mc
->is_default
= true;
812 mc
->default_boot_order
= "c";
813 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
814 mc
->ignore_boot_device_suffixes
= true;
815 mc
->default_display
= "std";
816 mc
->default_nic
= "sunhme";
817 mc
->no_parallel
= !module_object_class_by_name(TYPE_ISA_PARALLEL
);
818 fwc
->get_dev_path
= sun4u_fw_dev_path
;
819 compat_props_add(mc
->compat_props
, hw_compat_sparc64
, hw_compat_sparc64_len
);
822 static const TypeInfo sun4u_type
= {
823 .name
= MACHINE_TYPE_NAME("sun4u"),
824 .parent
= TYPE_MACHINE
,
825 .class_init
= sun4u_class_init
,
826 .interfaces
= (InterfaceInfo
[]) {
827 { TYPE_FW_PATH_PROVIDER
},
832 static void sun4v_class_init(ObjectClass
*oc
, void *data
)
834 MachineClass
*mc
= MACHINE_CLASS(oc
);
836 mc
->desc
= "Sun4v platform";
837 mc
->init
= sun4v_init
;
838 mc
->block_default_type
= IF_IDE
;
839 mc
->max_cpus
= 1; /* XXX for now */
840 mc
->default_boot_order
= "c";
841 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
842 mc
->default_display
= "std";
843 mc
->default_nic
= "sunhme";
844 mc
->no_parallel
= !module_object_class_by_name(TYPE_ISA_PARALLEL
);
847 static const TypeInfo sun4v_type
= {
848 .name
= MACHINE_TYPE_NAME("sun4v"),
849 .parent
= TYPE_MACHINE
,
850 .class_init
= sun4v_class_init
,
853 static void sun4u_register_types(void)
855 type_register_static(&power_info
);
856 type_register_static(&ebus_info
);
857 type_register_static(&prom_info
);
858 type_register_static(&ram_info
);
860 type_register_static(&sun4u_type
);
861 type_register_static(&sun4v_type
);
864 type_init(sun4u_register_types
)