hw/sparc64/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "qemu/error-report.h"
  28 #include "qapi/error.h"
  29 #include "qemu-common.h"
  30 #include "cpu.h"
  31 #include "hw/hw.h"
  32 #include "hw/pci/pci.h"
  33 #include "hw/pci/pci_bridge.h"
  34 #include "hw/pci/pci_bus.h"
  35 #include "hw/pci/pci_host.h"
  36 #include "hw/pci-host/sabre.h"
  37 #include "hw/char/serial.h"
  38 #include "hw/char/parallel.h"
  39 #include "hw/timer/m48t59.h"
  40 #include "migration/vmstate.h"
  41 #include "hw/input/i8042.h"
  42 #include "hw/block/fdc.h"
  43 #include "net/net.h"
  44 #include "qemu/timer.h"
  45 #include "sysemu/sysemu.h"
  46 #include "hw/boards.h"
  47 #include "hw/nvram/sun_nvram.h"
  48 #include "hw/nvram/chrp_nvram.h"
  49 #include "hw/sparc/sparc64.h"
  50 #include "hw/nvram/fw_cfg.h"
  51 #include "hw/sysbus.h"
  52 #include "hw/ide.h"
  53 #include "hw/ide/pci.h"
  54 #include "hw/loader.h"
  55 #include "hw/fw-path-provider.h"
  56 #include "elf.h"
  57 #include "trace.h"
  58
  59 #define KERNEL_LOAD_ADDR     0x00404000
  60 #define CMDLINE_ADDR         0x003ff000
  61 #define PROM_SIZE_MAX        (4 * MiB)
  62 #define PROM_VADDR           0x000ffd00000ULL
  63 #define PBM_SPECIAL_BASE     0x1fe00000000ULL
  64 #define PBM_MEM_BASE         0x1ff00000000ULL
  65 #define PBM_PCI_IO_BASE      (PBM_SPECIAL_BASE + 0x02000000ULL)
  66 #define PROM_FILENAME        "openbios-sparc64"
  67 #define NVRAM_SIZE           0x2000
  68 #define MAX_IDE_BUS          2
  69 #define BIOS_CFG_IOPORT      0x510
  70 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  71 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  72 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  73
  74 #define IVEC_MAX             0x40
  75
  76 struct hwdef {
  77     uint16_t machine_id;
  78     uint64_t prom_addr;
  79     uint64_t console_serial_base;
  80 };
  81
  82 typedef struct EbusState {
  83     /*< private >*/
  84     PCIDevice parent_obj;
  85
  86     ISABus *isa_bus;
  87     qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
  88     uint64_t console_serial_base;
  89     MemoryRegion bar0;
  90     MemoryRegion bar1;
  91 } EbusState;
  92
  93 #define TYPE_EBUS "ebus"
  94 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
  95
  96 const char *fw_cfg_arch_key_name(uint16_t key)
  97 {
  98     static const struct {
  99         uint16_t key;
 100         const char *name;
 101     } fw_cfg_arch_wellknown_keys[] = {
 102         {FW_CFG_SPARC64_WIDTH, "width"},
 103         {FW_CFG_SPARC64_HEIGHT, "height"},
 104         {FW_CFG_SPARC64_DEPTH, "depth"},
 105     };
 106
 107     for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
 108         if (fw_cfg_arch_wellknown_keys[i].key == key) {
 109             return fw_cfg_arch_wellknown_keys[i].name;
 110         }
 111     }
 112     return NULL;
 113 }
 114
 115 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
 116                             Error **errp)
 117 {
 118     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 119 }
 120
 121 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
 122                                   const char *arch, ram_addr_t RAM_size,
 123                                   const char *boot_devices,
 124                                   uint32_t kernel_image, uint32_t kernel_size,
 125                                   const char *cmdline,
 126                                   uint32_t initrd_image, uint32_t initrd_size,
 127                                   uint32_t NVRAM_image,
 128                                   int width, int height, int depth,
 129                                   const uint8_t *macaddr)
 130 {
 131     unsigned int i;
 132     int sysp_end;
 133     uint8_t image[0x1ff0];
 134     NvramClass *k = NVRAM_GET_CLASS(nvram);
 135
 136     memset(image, '\0', sizeof(image));
 137
 138     /* OpenBIOS nvram variables partition */
 139     sysp_end = chrp_nvram_create_system_partition(image, 0);
 140
 141     /* Free space partition */
 142     chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
 143
 144     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 145
 146     for (i = 0; i < sizeof(image); i++) {
 147         (k->write)(nvram, i, image[i]);
 148     }
 149
 150     return 0;
 151 }
 152
 153 static uint64_t sun4u_load_kernel(const char *kernel_filename,
 154                                   const char *initrd_filename,
 155                                   ram_addr_t RAM_size, uint64_t *initrd_size,
 156                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
 157                                   uint64_t *kernel_entry)
 158 {
 159     int linux_boot;
 160     unsigned int i;
 161     long kernel_size;
 162     uint8_t *ptr;
 163     uint64_t kernel_top = 0;
 164
 165     linux_boot = (kernel_filename != NULL);
 166
 167     kernel_size = 0;
 168     if (linux_boot) {
 169         int bswap_needed;
 170
 171 #ifdef BSWAP_NEEDED
 172         bswap_needed = 1;
 173 #else
 174         bswap_needed = 0;
 175 #endif
 176         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry,
 177                                kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
 178         if (kernel_size < 0) {
 179             *kernel_addr = KERNEL_LOAD_ADDR;
 180             *kernel_entry = KERNEL_LOAD_ADDR;
 181             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 182                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 183                                     TARGET_PAGE_SIZE);
 184         }
 185         if (kernel_size < 0) {
 186             kernel_size = load_image_targphys(kernel_filename,
 187                                               KERNEL_LOAD_ADDR,
 188                                               RAM_size - KERNEL_LOAD_ADDR);
 189         }
 190         if (kernel_size < 0) {
 191             error_report("could not load kernel '%s'", kernel_filename);
 192             exit(1);
 193         }
 194         /* load initrd above kernel */
 195         *initrd_size = 0;
 196         if (initrd_filename && kernel_top) {
 197             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
 198
 199             *initrd_size = load_image_targphys(initrd_filename,
 200                                                *initrd_addr,
 201                                                RAM_size - *initrd_addr);
 202             if ((int)*initrd_size < 0) {
 203                 error_report("could not load initial ram disk '%s'",
 204                              initrd_filename);
 205                 exit(1);
 206             }
 207         }
 208         if (*initrd_size > 0) {
 209             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 210                 ptr = rom_ptr(*kernel_addr + i, 32);
 211                 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 212                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
 213                     stl_p(ptr + 28, *initrd_size);
 214                     break;
 215                 }
 216             }
 217         }
 218     }
 219     return kernel_size;
 220 }
 221
 222 typedef struct ResetData {
 223     SPARCCPU *cpu;
 224     uint64_t prom_addr;
 225 } ResetData;
 226
 227 #define TYPE_SUN4U_POWER "power"
 228 #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER)
 229
 230 typedef struct PowerDevice {
 231     SysBusDevice parent_obj;
 232
 233     MemoryRegion power_mmio;
 234 } PowerDevice;
 235
 236 /* Power */
 237 static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
 238 {
 239     return 0;
 240 }
 241
 242 static void power_mem_write(void *opaque, hwaddr addr,
 243                             uint64_t val, unsigned size)
 244 {
 245     /* According to a real Ultra 5, bit 24 controls the power */
 246     if (val & 0x1000000) {
 247         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 248     }
 249 }
 250
 251 static const MemoryRegionOps power_mem_ops = {
 252     .read = power_mem_read,
 253     .write = power_mem_write,
 254     .endianness = DEVICE_NATIVE_ENDIAN,
 255     .valid = {
 256         .min_access_size = 4,
 257         .max_access_size = 4,
 258     },
 259 };
 260
 261 static void power_realize(DeviceState *dev, Error **errp)
 262 {
 263     PowerDevice *d = SUN4U_POWER(dev);
 264     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 265
 266     memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
 267                           "power", sizeof(uint32_t));
 268
 269     sysbus_init_mmio(sbd, &d->power_mmio);
 270 }
 271
 272 static void power_class_init(ObjectClass *klass, void *data)
 273 {
 274     DeviceClass *dc = DEVICE_CLASS(klass);
 275
 276     dc->realize = power_realize;
 277 }
 278
 279 static const TypeInfo power_info = {
 280     .name          = TYPE_SUN4U_POWER,
 281     .parent        = TYPE_SYS_BUS_DEVICE,
 282     .instance_size = sizeof(PowerDevice),
 283     .class_init    = power_class_init,
 284 };
 285
 286 static void ebus_isa_irq_handler(void *opaque, int n, int level)
 287 {
 288     EbusState *s = EBUS(opaque);
 289     qemu_irq irq = s->isa_bus_irqs[n];
 290
 291     /* Pass ISA bus IRQs onto their gpio equivalent */
 292     trace_ebus_isa_irq_handler(n, level);
 293     if (irq) {
 294         qemu_set_irq(irq, level);
 295     }
 296 }
 297
 298 /* EBUS (Eight bit bus) bridge */
 299 static void ebus_realize(PCIDevice *pci_dev, Error **errp)
 300 {
 301     EbusState *s = EBUS(pci_dev);
 302     SysBusDevice *sbd;
 303     DeviceState *dev;
 304     qemu_irq *isa_irq;
 305     DriveInfo *fd[MAX_FD];
 306     int i;
 307
 308     s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
 309                              pci_address_space_io(pci_dev), errp);
 310     if (!s->isa_bus) {
 311         error_setg(errp, "unable to instantiate EBUS ISA bus");
 312         return;
 313     }
 314
 315     /* ISA bus */
 316     isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
 317     isa_bus_irqs(s->isa_bus, isa_irq);
 318     qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
 319                              ISA_NUM_IRQS);
 320
 321     /* Serial ports */
 322     i = 0;
 323     if (s->console_serial_base) {
 324         serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
 325                        0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
 326         i++;
 327     }
 328     serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
 329
 330     /* Parallel ports */
 331     parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
 332
 333     /* Keyboard */
 334     isa_create_simple(s->isa_bus, "i8042");
 335
 336     /* Floppy */
 337     for (i = 0; i < MAX_FD; i++) {
 338         fd[i] = drive_get(IF_FLOPPY, 0, i);
 339     }
 340     dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
 341     if (fd[0]) {
 342         qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
 343                             &error_abort);
 344     }
 345     if (fd[1]) {
 346         qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
 347                             &error_abort);
 348     }
 349     qdev_prop_set_uint32(dev, "dma", -1);
 350     qdev_init_nofail(dev);
 351
 352     /* Power */
 353     dev = qdev_create(NULL, TYPE_SUN4U_POWER);
 354     qdev_init_nofail(dev);
 355     sbd = SYS_BUS_DEVICE(dev);
 356     memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
 357                                 sysbus_mmio_get_region(sbd, 0));
 358
 359     /* PCI */
 360     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 361     pci_dev->config[0x05] = 0x00;
 362     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 363     pci_dev->config[0x07] = 0x03; // status = medium devsel
 364     pci_dev->config[0x09] = 0x00; // programming i/f
 365     pci_dev->config[0x0D] = 0x0a; // latency_timer
 366
 367     memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
 368                              0, 0x1000000);
 369     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 370     memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
 371                              0, 0x8000);
 372     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
 373 }
 374
 375 static Property ebus_properties[] = {
 376     DEFINE_PROP_UINT64("console-serial-base", EbusState,
 377                        console_serial_base, 0),
 378     DEFINE_PROP_END_OF_LIST(),
 379 };
 380
 381 static void ebus_class_init(ObjectClass *klass, void *data)
 382 {
 383     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 384     DeviceClass *dc = DEVICE_CLASS(klass);
 385
 386     k->realize = ebus_realize;
 387     k->vendor_id = PCI_VENDOR_ID_SUN;
 388     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 389     k->revision = 0x01;
 390     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 391     dc->props = ebus_properties;
 392 }
 393
 394 static const TypeInfo ebus_info = {
 395     .name          = TYPE_EBUS,
 396     .parent        = TYPE_PCI_DEVICE,
 397     .class_init    = ebus_class_init,
 398     .instance_size = sizeof(EbusState),
 399     .interfaces = (InterfaceInfo[]) {
 400         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 401         { },
 402     },
 403 };
 404
 405 #define TYPE_OPENPROM "openprom"
 406 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
 407
 408 typedef struct PROMState {
 409     SysBusDevice parent_obj;
 410
 411     MemoryRegion prom;
 412 } PROMState;
 413
 414 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 415 {
 416     hwaddr *base_addr = (hwaddr *)opaque;
 417     return addr + *base_addr - PROM_VADDR;
 418 }
 419
 420 /* Boot PROM (OpenBIOS) */
 421 static void prom_init(hwaddr addr, const char *bios_name)
 422 {
 423     DeviceState *dev;
 424     SysBusDevice *s;
 425     char *filename;
 426     int ret;
 427
 428     dev = qdev_create(NULL, TYPE_OPENPROM);
 429     qdev_init_nofail(dev);
 430     s = SYS_BUS_DEVICE(dev);
 431
 432     sysbus_mmio_map(s, 0, addr);
 433
 434     /* load boot prom */
 435     if (bios_name == NULL) {
 436         bios_name = PROM_FILENAME;
 437     }
 438     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 439     if (filename) {
 440         ret = load_elf(filename, NULL, translate_prom_address, &addr,
 441                        NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
 442         if (ret < 0 || ret > PROM_SIZE_MAX) {
 443             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 444         }
 445         g_free(filename);
 446     } else {
 447         ret = -1;
 448     }
 449     if (ret < 0 || ret > PROM_SIZE_MAX) {
 450         error_report("could not load prom '%s'", bios_name);
 451         exit(1);
 452     }
 453 }
 454
 455 static void prom_realize(DeviceState *ds, Error **errp)
 456 {
 457     PROMState *s = OPENPROM(ds);
 458     SysBusDevice *dev = SYS_BUS_DEVICE(ds);
 459     Error *local_err = NULL;
 460
 461     memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
 462                                      PROM_SIZE_MAX, &local_err);
 463     if (local_err) {
 464         error_propagate(errp, local_err);
 465         return;
 466     }
 467
 468     vmstate_register_ram_global(&s->prom);
 469     memory_region_set_readonly(&s->prom, true);
 470     sysbus_init_mmio(dev, &s->prom);
 471 }
 472
 473 static Property prom_properties[] = {
 474     {/* end of property list */},
 475 };
 476
 477 static void prom_class_init(ObjectClass *klass, void *data)
 478 {
 479     DeviceClass *dc = DEVICE_CLASS(klass);
 480
 481     dc->props = prom_properties;
 482     dc->realize = prom_realize;
 483 }
 484
 485 static const TypeInfo prom_info = {
 486     .name          = TYPE_OPENPROM,
 487     .parent        = TYPE_SYS_BUS_DEVICE,
 488     .instance_size = sizeof(PROMState),
 489     .class_init    = prom_class_init,
 490 };
 491
 492
 493 #define TYPE_SUN4U_MEMORY "memory"
 494 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
 495
 496 typedef struct RamDevice {
 497     SysBusDevice parent_obj;
 498
 499     MemoryRegion ram;
 500     uint64_t size;
 501 } RamDevice;
 502
 503 /* System RAM */
 504 static void ram_realize(DeviceState *dev, Error **errp)
 505 {
 506     RamDevice *d = SUN4U_RAM(dev);
 507     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 508
 509     memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
 510                            &error_fatal);
 511     vmstate_register_ram_global(&d->ram);
 512     sysbus_init_mmio(sbd, &d->ram);
 513 }
 514
 515 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
 516 {
 517     DeviceState *dev;
 518     SysBusDevice *s;
 519     RamDevice *d;
 520
 521     /* allocate RAM */
 522     dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
 523     s = SYS_BUS_DEVICE(dev);
 524
 525     d = SUN4U_RAM(dev);
 526     d->size = RAM_size;
 527     qdev_init_nofail(dev);
 528
 529     sysbus_mmio_map(s, 0, addr);
 530 }
 531
 532 static Property ram_properties[] = {
 533     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 534     DEFINE_PROP_END_OF_LIST(),
 535 };
 536
 537 static void ram_class_init(ObjectClass *klass, void *data)
 538 {
 539     DeviceClass *dc = DEVICE_CLASS(klass);
 540
 541     dc->realize = ram_realize;
 542     dc->props = ram_properties;
 543 }
 544
 545 static const TypeInfo ram_info = {
 546     .name          = TYPE_SUN4U_MEMORY,
 547     .parent        = TYPE_SYS_BUS_DEVICE,
 548     .instance_size = sizeof(RamDevice),
 549     .class_init    = ram_class_init,
 550 };
 551
 552 static void sun4uv_init(MemoryRegion *address_space_mem,
 553                         MachineState *machine,
 554                         const struct hwdef *hwdef)
 555 {
 556     SPARCCPU *cpu;
 557     Nvram *nvram;
 558     unsigned int i;
 559     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
 560     SabreState *sabre;
 561     PCIBus *pci_bus, *pci_busA, *pci_busB;
 562     PCIDevice *ebus, *pci_dev;
 563     SysBusDevice *s;
 564     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 565     DeviceState *iommu, *dev;
 566     FWCfgState *fw_cfg;
 567     NICInfo *nd;
 568     MACAddr macaddr;
 569     bool onboard_nic;
 570
 571     /* init CPUs */
 572     cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
 573
 574     /* IOMMU */
 575     iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
 576     qdev_init_nofail(iommu);
 577
 578     /* set up devices */
 579     ram_init(0, machine->ram_size);
 580
 581     prom_init(hwdef->prom_addr, bios_name);
 582
 583     /* Init sabre (PCI host bridge) */
 584     sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
 585     qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
 586     qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
 587     object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
 588                              &error_abort);
 589     qdev_init_nofail(DEVICE(sabre));
 590
 591     /* Wire up PCI interrupts to CPU */
 592     for (i = 0; i < IVEC_MAX; i++) {
 593         qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
 594             qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
 595     }
 596
 597     pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
 598     pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
 599     pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
 600
 601     /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
 602        reserved (leaving no slots free after on-board devices) however slots
 603        0-3 are free on busB */
 604     pci_bus->slot_reserved_mask = 0xfffffffc;
 605     pci_busA->slot_reserved_mask = 0xfffffff1;
 606     pci_busB->slot_reserved_mask = 0xfffffff0;
 607
 608     ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
 609     qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
 610                          hwdef->console_serial_base);
 611     qdev_init_nofail(DEVICE(ebus));
 612
 613     /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
 614     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
 615         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
 616     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
 617         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
 618     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
 619         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
 620     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
 621         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
 622     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
 623         qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
 624
 625     switch (vga_interface_type) {
 626     case VGA_STD:
 627         pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
 628         break;
 629     case VGA_NONE:
 630         break;
 631     default:
 632         abort();   /* Should not happen - types are checked in vl.c already */
 633     }
 634
 635     memset(&macaddr, 0, sizeof(MACAddr));
 636     onboard_nic = false;
 637     for (i = 0; i < nb_nics; i++) {
 638         nd = &nd_table[i];
 639
 640         if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
 641             if (!onboard_nic) {
 642                 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
 643                                                    true, "sunhme");
 644                 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
 645                 onboard_nic = true;
 646             } else {
 647                 pci_dev = pci_create(pci_busB, -1, "sunhme");
 648             }
 649         } else {
 650             pci_dev = pci_create(pci_busB, -1, nd->model);
 651         }
 652
 653         dev = &pci_dev->qdev;
 654         qdev_set_nic_properties(dev, nd);
 655         qdev_init_nofail(dev);
 656     }
 657
 658     /* If we don't have an onboard NIC, grab a default MAC address so that
 659      * we have a valid machine id */
 660     if (!onboard_nic) {
 661         qemu_macaddr_default_if_unset(&macaddr);
 662     }
 663
 664     ide_drive_get(hd, ARRAY_SIZE(hd));
 665
 666     pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
 667     qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
 668     qdev_init_nofail(&pci_dev->qdev);
 669     pci_ide_create_devs(pci_dev, hd);
 670
 671     /* Map NVRAM into I/O (ebus) space */
 672     nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
 673     s = SYS_BUS_DEVICE(nvram);
 674     memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
 675                                 sysbus_mmio_get_region(s, 0));
 676
 677     initrd_size = 0;
 678     initrd_addr = 0;
 679     kernel_size = sun4u_load_kernel(machine->kernel_filename,
 680                                     machine->initrd_filename,
 681                                     ram_size, &initrd_size, &initrd_addr,
 682                                     &kernel_addr, &kernel_entry);
 683
 684     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
 685                            machine->boot_order,
 686                            kernel_addr, kernel_size,
 687                            machine->kernel_cmdline,
 688                            initrd_addr, initrd_size,
 689                            /* XXX: need an option to load a NVRAM image */
 690                            0,
 691                            graphic_width, graphic_height, graphic_depth,
 692                            (uint8_t *)&macaddr);
 693
 694     dev = qdev_create(NULL, TYPE_FW_CFG_IO);
 695     qdev_prop_set_bit(dev, "dma_enabled", false);
 696     object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
 697     qdev_init_nofail(dev);
 698     memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
 699                                 &FW_CFG_IO(dev)->comb_iomem);
 700
 701     fw_cfg = FW_CFG(dev);
 702     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
 703     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
 704     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 705     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 706     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
 707     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 708     if (machine->kernel_cmdline) {
 709         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 710                        strlen(machine->kernel_cmdline) + 1);
 711         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
 712     } else {
 713         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 714     }
 715     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 716     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 717     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
 718
 719     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 720     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 721     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 722
 723     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 724 }
 725
 726 enum {
 727     sun4u_id = 0,
 728     sun4v_id = 64,
 729 };
 730
 731 /*
 732  * Implementation of an interface to adjust firmware path
 733  * for the bootindex property handling.
 734  */
 735 static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
 736                                DeviceState *dev)
 737 {
 738     PCIDevice *pci;
 739     IDEBus *ide_bus;
 740     IDEState *ide_s;
 741     int bus_id;
 742
 743     if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
 744         pci = PCI_DEVICE(dev);
 745
 746         if (PCI_FUNC(pci->devfn)) {
 747             return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
 748                                    PCI_FUNC(pci->devfn));
 749         } else {
 750             return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
 751         }
 752     }
 753
 754     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
 755          ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
 756          ide_s = idebus_active_if(ide_bus);
 757          bus_id = ide_bus->bus_id;
 758
 759          if (ide_s->drive_kind == IDE_CD) {
 760              return g_strdup_printf("ide@%x/cdrom", bus_id);
 761          }
 762
 763          return g_strdup_printf("ide@%x/disk", bus_id);
 764     }
 765
 766     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
 767         return g_strdup("disk");
 768     }
 769
 770     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
 771         return g_strdup("cdrom");
 772     }
 773
 774     if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
 775         return g_strdup("disk");
 776     }
 777
 778     return NULL;
 779 }
 780
 781 static const struct hwdef hwdefs[] = {
 782     /* Sun4u generic PC-like machine */
 783     {
 784         .machine_id = sun4u_id,
 785         .prom_addr = 0x1fff0000000ULL,
 786         .console_serial_base = 0,
 787     },
 788     /* Sun4v generic PC-like machine */
 789     {
 790         .machine_id = sun4v_id,
 791         .prom_addr = 0x1fff0000000ULL,
 792         .console_serial_base = 0,
 793     },
 794 };
 795
 796 /* Sun4u hardware initialisation */
 797 static void sun4u_init(MachineState *machine)
 798 {
 799     sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
 800 }
 801
 802 /* Sun4v hardware initialisation */
 803 static void sun4v_init(MachineState *machine)
 804 {
 805     sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
 806 }
 807
 808 static void sun4u_class_init(ObjectClass *oc, void *data)
 809 {
 810     MachineClass *mc = MACHINE_CLASS(oc);
 811     FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
 812
 813     mc->desc = "Sun4u platform";
 814     mc->init = sun4u_init;
 815     mc->block_default_type = IF_IDE;
 816     mc->max_cpus = 1; /* XXX for now */
 817     mc->is_default = 1;
 818     mc->default_boot_order = "c";
 819     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
 820     mc->ignore_boot_device_suffixes = true;
 821     mc->default_display = "std";
 822     fwc->get_dev_path = sun4u_fw_dev_path;
 823 }
 824
 825 static const TypeInfo sun4u_type = {
 826     .name = MACHINE_TYPE_NAME("sun4u"),
 827     .parent = TYPE_MACHINE,
 828     .class_init = sun4u_class_init,
 829     .interfaces = (InterfaceInfo[]) {
 830         { TYPE_FW_PATH_PROVIDER },
 831         { }
 832     },
 833 };
 834
 835 static void sun4v_class_init(ObjectClass *oc, void *data)
 836 {
 837     MachineClass *mc = MACHINE_CLASS(oc);
 838
 839     mc->desc = "Sun4v platform";
 840     mc->init = sun4v_init;
 841     mc->block_default_type = IF_IDE;
 842     mc->max_cpus = 1; /* XXX for now */
 843     mc->default_boot_order = "c";
 844     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
 845     mc->default_display = "std";
 846 }
 847
 848 static const TypeInfo sun4v_type = {
 849     .name = MACHINE_TYPE_NAME("sun4v"),
 850     .parent = TYPE_MACHINE,
 851     .class_init = sun4v_class_init,
 852 };
 853
 854 static void sun4u_register_types(void)
 855 {
 856     type_register_static(&power_info);
 857     type_register_static(&ebus_info);
 858     type_register_static(&prom_info);
 859     type_register_static(&ram_info);
 860
 861     type_register_static(&sun4u_type);
 862     type_register_static(&sun4v_type);
 863 }
 864
 865 type_init(sun4u_register_types)