hw/ssi/xilinx_spi.c

   1 /*
   2  * QEMU model of the Xilinx SPI Controller
   3  *
   4  * Copyright (C) 2010 Edgar E. Iglesias.
   5  * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
   6  * Copyright (C) 2012 PetaLogix
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "hw/sysbus.h"
  29 #include "migration/vmstate.h"
  30 #include "qemu/log.h"
  31 #include "qemu/module.h"
  32 #include "qemu/fifo8.h"
  33
  34 #include "hw/irq.h"
  35 #include "hw/qdev-properties.h"
  36 #include "hw/ssi/ssi.h"
  37 #include "qom/object.h"
  38
  39 #ifdef XILINX_SPI_ERR_DEBUG
  40 #define DB_PRINT(...) do { \
  41     fprintf(stderr,  ": %s: ", __func__); \
  42     fprintf(stderr, ## __VA_ARGS__); \
  43     } while (0)
  44 #else
  45     #define DB_PRINT(...)
  46 #endif
  47
  48 #define R_DGIER     (0x1c / 4)
  49 #define R_DGIER_IE  (1 << 31)
  50
  51 #define R_IPISR     (0x20 / 4)
  52 #define IRQ_DRR_NOT_EMPTY    (1 << (31 - 23))
  53 #define IRQ_DRR_OVERRUN      (1 << (31 - 26))
  54 #define IRQ_DRR_FULL         (1 << (31 - 27))
  55 #define IRQ_TX_FF_HALF_EMPTY (1 << 6)
  56 #define IRQ_DTR_UNDERRUN     (1 << 3)
  57 #define IRQ_DTR_EMPTY        (1 << (31 - 29))
  58
  59 #define R_IPIER     (0x28 / 4)
  60 #define R_SRR       (0x40 / 4)
  61 #define R_SPICR     (0x60 / 4)
  62 #define R_SPICR_TXFF_RST     (1 << 5)
  63 #define R_SPICR_RXFF_RST     (1 << 6)
  64 #define R_SPICR_MTI          (1 << 8)
  65
  66 #define R_SPISR     (0x64 / 4)
  67 #define SR_TX_FULL    (1 << 3)
  68 #define SR_TX_EMPTY   (1 << 2)
  69 #define SR_RX_FULL    (1 << 1)
  70 #define SR_RX_EMPTY   (1 << 0)
  71
  72 #define R_SPIDTR    (0x68 / 4)
  73 #define R_SPIDRR    (0x6C / 4)
  74 #define R_SPISSR    (0x70 / 4)
  75 #define R_TX_FF_OCY (0x74 / 4)
  76 #define R_RX_FF_OCY (0x78 / 4)
  77 #define R_MAX       (0x7C / 4)
  78
  79 #define FIFO_CAPACITY 256
  80
  81 #define TYPE_XILINX_SPI "xlnx.xps-spi"
  82 typedef struct XilinxSPI XilinxSPI;
  83 #define XILINX_SPI(obj) OBJECT_CHECK(XilinxSPI, (obj), TYPE_XILINX_SPI)
  84
  85 struct XilinxSPI {
  86     SysBusDevice parent_obj;
  87
  88     MemoryRegion mmio;
  89
  90     qemu_irq irq;
  91     int irqline;
  92
  93     uint8_t num_cs;
  94     qemu_irq *cs_lines;
  95
  96     SSIBus *spi;
  97
  98     Fifo8 rx_fifo;
  99     Fifo8 tx_fifo;
 100
 101     uint32_t regs[R_MAX];
 102 };
 103
 104 static void txfifo_reset(XilinxSPI *s)
 105 {
 106     fifo8_reset(&s->tx_fifo);
 107
 108     s->regs[R_SPISR] &= ~SR_TX_FULL;
 109     s->regs[R_SPISR] |= SR_TX_EMPTY;
 110 }
 111
 112 static void rxfifo_reset(XilinxSPI *s)
 113 {
 114     fifo8_reset(&s->rx_fifo);
 115
 116     s->regs[R_SPISR] |= SR_RX_EMPTY;
 117     s->regs[R_SPISR] &= ~SR_RX_FULL;
 118 }
 119
 120 static void xlx_spi_update_cs(XilinxSPI *s)
 121 {
 122     int i;
 123
 124     for (i = 0; i < s->num_cs; ++i) {
 125         qemu_set_irq(s->cs_lines[i], !(~s->regs[R_SPISSR] & 1 << i));
 126     }
 127 }
 128
 129 static void xlx_spi_update_irq(XilinxSPI *s)
 130 {
 131     uint32_t pending;
 132
 133     s->regs[R_IPISR] |=
 134             (!fifo8_is_empty(&s->rx_fifo) ? IRQ_DRR_NOT_EMPTY : 0) |
 135             (fifo8_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0);
 136
 137     pending = s->regs[R_IPISR] & s->regs[R_IPIER];
 138
 139     pending = pending && (s->regs[R_DGIER] & R_DGIER_IE);
 140     pending = !!pending;
 141
 142     /* This call lies right in the data paths so don't call the
 143        irq chain unless things really changed.  */
 144     if (pending != s->irqline) {
 145         s->irqline = pending;
 146         DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
 147                     pending, s->regs[R_IPISR], s->regs[R_IPIER]);
 148         qemu_set_irq(s->irq, pending);
 149     }
 150
 151 }
 152
 153 static void xlx_spi_do_reset(XilinxSPI *s)
 154 {
 155     memset(s->regs, 0, sizeof s->regs);
 156
 157     rxfifo_reset(s);
 158     txfifo_reset(s);
 159
 160     s->regs[R_SPISSR] = ~0;
 161     xlx_spi_update_irq(s);
 162     xlx_spi_update_cs(s);
 163 }
 164
 165 static void xlx_spi_reset(DeviceState *d)
 166 {
 167     xlx_spi_do_reset(XILINX_SPI(d));
 168 }
 169
 170 static inline int spi_master_enabled(XilinxSPI *s)
 171 {
 172     return !(s->regs[R_SPICR] & R_SPICR_MTI);
 173 }
 174
 175 static void spi_flush_txfifo(XilinxSPI *s)
 176 {
 177     uint32_t tx;
 178     uint32_t rx;
 179
 180     while (!fifo8_is_empty(&s->tx_fifo)) {
 181         tx = (uint32_t)fifo8_pop(&s->tx_fifo);
 182         DB_PRINT("data tx:%x\n", tx);
 183         rx = ssi_transfer(s->spi, tx);
 184         DB_PRINT("data rx:%x\n", rx);
 185         if (fifo8_is_full(&s->rx_fifo)) {
 186             s->regs[R_IPISR] |= IRQ_DRR_OVERRUN;
 187         } else {
 188             fifo8_push(&s->rx_fifo, (uint8_t)rx);
 189             if (fifo8_is_full(&s->rx_fifo)) {
 190                 s->regs[R_SPISR] |= SR_RX_FULL;
 191                 s->regs[R_IPISR] |= IRQ_DRR_FULL;
 192             }
 193         }
 194
 195         s->regs[R_SPISR] &= ~SR_RX_EMPTY;
 196         s->regs[R_SPISR] &= ~SR_TX_FULL;
 197         s->regs[R_SPISR] |= SR_TX_EMPTY;
 198
 199         s->regs[R_IPISR] |= IRQ_DTR_EMPTY;
 200         s->regs[R_IPISR] |= IRQ_DRR_NOT_EMPTY;
 201     }
 202
 203 }
 204
 205 static uint64_t
 206 spi_read(void *opaque, hwaddr addr, unsigned int size)
 207 {
 208     XilinxSPI *s = opaque;
 209     uint32_t r = 0;
 210
 211     addr >>= 2;
 212     switch (addr) {
 213     case R_SPIDRR:
 214         if (fifo8_is_empty(&s->rx_fifo)) {
 215             DB_PRINT("Read from empty FIFO!\n");
 216             return 0xdeadbeef;
 217         }
 218
 219         s->regs[R_SPISR] &= ~SR_RX_FULL;
 220         r = fifo8_pop(&s->rx_fifo);
 221         if (fifo8_is_empty(&s->rx_fifo)) {
 222             s->regs[R_SPISR] |= SR_RX_EMPTY;
 223         }
 224         break;
 225
 226     case R_SPISR:
 227         r = s->regs[addr];
 228         break;
 229
 230     default:
 231         if (addr < ARRAY_SIZE(s->regs)) {
 232             r = s->regs[addr];
 233         }
 234         break;
 235
 236     }
 237     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r);
 238     xlx_spi_update_irq(s);
 239     return r;
 240 }
 241
 242 static void
 243 spi_write(void *opaque, hwaddr addr,
 244             uint64_t val64, unsigned int size)
 245 {
 246     XilinxSPI *s = opaque;
 247     uint32_t value = val64;
 248
 249     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
 250     addr >>= 2;
 251     switch (addr) {
 252     case R_SRR:
 253         if (value != 0xa) {
 254             DB_PRINT("Invalid write to SRR %x\n", value);
 255         } else {
 256             xlx_spi_do_reset(s);
 257         }
 258         break;
 259
 260     case R_SPIDTR:
 261         s->regs[R_SPISR] &= ~SR_TX_EMPTY;
 262         fifo8_push(&s->tx_fifo, (uint8_t)value);
 263         if (fifo8_is_full(&s->tx_fifo)) {
 264             s->regs[R_SPISR] |= SR_TX_FULL;
 265         }
 266         if (!spi_master_enabled(s)) {
 267             goto done;
 268         } else {
 269             DB_PRINT("DTR and master enabled\n");
 270         }
 271         spi_flush_txfifo(s);
 272         break;
 273
 274     case R_SPISR:
 275         DB_PRINT("Invalid write to SPISR %x\n", value);
 276         break;
 277
 278     case R_IPISR:
 279         /* Toggle the bits.  */
 280         s->regs[addr] ^= value;
 281         break;
 282
 283     /* Slave Select Register.  */
 284     case R_SPISSR:
 285         s->regs[addr] = value;
 286         xlx_spi_update_cs(s);
 287         break;
 288
 289     case R_SPICR:
 290         /* FIXME: reset irq and sr state to empty queues.  */
 291         if (value & R_SPICR_RXFF_RST) {
 292             rxfifo_reset(s);
 293         }
 294
 295         if (value & R_SPICR_TXFF_RST) {
 296             txfifo_reset(s);
 297         }
 298         value &= ~(R_SPICR_RXFF_RST | R_SPICR_TXFF_RST);
 299         s->regs[addr] = value;
 300
 301         if (!(value & R_SPICR_MTI)) {
 302             spi_flush_txfifo(s);
 303         }
 304         break;
 305
 306     default:
 307         if (addr < ARRAY_SIZE(s->regs)) {
 308             s->regs[addr] = value;
 309         }
 310         break;
 311     }
 312
 313 done:
 314     xlx_spi_update_irq(s);
 315 }
 316
 317 static const MemoryRegionOps spi_ops = {
 318     .read = spi_read,
 319     .write = spi_write,
 320     .endianness = DEVICE_NATIVE_ENDIAN,
 321     .valid = {
 322         .min_access_size = 4,
 323         .max_access_size = 4
 324     }
 325 };
 326
 327 static void xilinx_spi_realize(DeviceState *dev, Error **errp)
 328 {
 329     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 330     XilinxSPI *s = XILINX_SPI(dev);
 331     int i;
 332
 333     DB_PRINT("\n");
 334
 335     s->spi = ssi_create_bus(dev, "spi");
 336
 337     sysbus_init_irq(sbd, &s->irq);
 338     s->cs_lines = g_new0(qemu_irq, s->num_cs);
 339     for (i = 0; i < s->num_cs; ++i) {
 340         sysbus_init_irq(sbd, &s->cs_lines[i]);
 341     }
 342
 343     memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
 344                           "xilinx-spi", R_MAX * 4);
 345     sysbus_init_mmio(sbd, &s->mmio);
 346
 347     s->irqline = -1;
 348
 349     fifo8_create(&s->tx_fifo, FIFO_CAPACITY);
 350     fifo8_create(&s->rx_fifo, FIFO_CAPACITY);
 351 }
 352
 353 static const VMStateDescription vmstate_xilinx_spi = {
 354     .name = "xilinx_spi",
 355     .version_id = 1,
 356     .minimum_version_id = 1,
 357     .fields = (VMStateField[]) {
 358         VMSTATE_FIFO8(tx_fifo, XilinxSPI),
 359         VMSTATE_FIFO8(rx_fifo, XilinxSPI),
 360         VMSTATE_UINT32_ARRAY(regs, XilinxSPI, R_MAX),
 361         VMSTATE_END_OF_LIST()
 362     }
 363 };
 364
 365 static Property xilinx_spi_properties[] = {
 366     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
 367     DEFINE_PROP_END_OF_LIST(),
 368 };
 369
 370 static void xilinx_spi_class_init(ObjectClass *klass, void *data)
 371 {
 372     DeviceClass *dc = DEVICE_CLASS(klass);
 373
 374     dc->realize = xilinx_spi_realize;
 375     dc->reset = xlx_spi_reset;
 376     device_class_set_props(dc, xilinx_spi_properties);
 377     dc->vmsd = &vmstate_xilinx_spi;
 378 }
 379
 380 static const TypeInfo xilinx_spi_info = {
 381     .name           = TYPE_XILINX_SPI,
 382     .parent         = TYPE_SYS_BUS_DEVICE,
 383     .instance_size  = sizeof(XilinxSPI),
 384     .class_init     = xilinx_spi_class_init,
 385 };
 386
 387 static void xilinx_spi_register_types(void)
 388 {
 389     type_register_static(&xilinx_spi_info);
 390 }
 391
 392 type_init(xilinx_spi_register_types)