2 * Luminary Micro Stellaris preipherals
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
13 typedef const struct {
22 enum {OLED_I2C
, OLED_SSI
} oled
;
23 } stellaris_board_info
;
25 /* General purpose timer module. */
27 /* Multiplication factor to convert from GPTM timer ticks to qemu timer
29 static int stellaris_clock_scale
;
31 typedef struct gptm_state
{
40 uint32_t match_prescale
[2];
43 struct gptm_state
*opaque
[2];
46 /* The timers have an alternate output used to trigger the ADC. */
51 static void gptm_update_irq(gptm_state
*s
)
54 level
= (s
->state
& s
->mask
) != 0;
55 qemu_set_irq(s
->irq
, level
);
58 static void gptm_stop(gptm_state
*s
, int n
)
60 qemu_del_timer(s
->timer
[n
]);
63 static void gptm_reload(gptm_state
*s
, int n
, int reset
)
67 tick
= qemu_get_clock(vm_clock
);
72 /* 32-bit CountDown. */
74 count
= s
->load
[0] | (s
->load
[1] << 16);
75 tick
+= (int64_t)count
* stellaris_clock_scale
;
76 } else if (s
->config
== 1) {
77 /* 32-bit RTC. 1Hz tick. */
78 tick
+= ticks_per_sec
;
79 } else if (s
->mode
[n
] == 0xa) {
80 /* PWM mode. Not implemented. */
82 cpu_abort(cpu_single_env
, "TODO: 16-bit timer mode 0x%x\n",
86 qemu_mod_timer(s
->timer
[n
], tick
);
89 static void gptm_tick(void *opaque
)
91 gptm_state
**p
= (gptm_state
**)opaque
;
99 if ((s
->control
& 0x20)) {
100 /* Output trigger. */
101 qemu_irq_raise(s
->trigger
);
102 qemu_irq_lower(s
->trigger
);
104 if (s
->mode
[0] & 1) {
109 gptm_reload(s
, 0, 0);
111 } else if (s
->config
== 1) {
115 match
= s
->match
[0] | (s
->match
[1] << 16);
121 gptm_reload(s
, 0, 0);
122 } else if (s
->mode
[n
] == 0xa) {
123 /* PWM mode. Not implemented. */
125 cpu_abort(cpu_single_env
, "TODO: 16-bit timer mode 0x%x\n",
131 static uint32_t gptm_read(void *opaque
, target_phys_addr_t offset
)
133 gptm_state
*s
= (gptm_state
*)opaque
;
139 case 0x04: /* TAMR */
141 case 0x08: /* TBMR */
150 return s
->state
& s
->mask
;
153 case 0x28: /* TAILR */
154 return s
->load
[0] | ((s
->config
< 4) ? (s
->load
[1] << 16) : 0);
155 case 0x2c: /* TBILR */
157 case 0x30: /* TAMARCHR */
158 return s
->match
[0] | ((s
->config
< 4) ? (s
->match
[1] << 16) : 0);
159 case 0x34: /* TBMATCHR */
161 case 0x38: /* TAPR */
162 return s
->prescale
[0];
163 case 0x3c: /* TBPR */
164 return s
->prescale
[1];
165 case 0x40: /* TAPMR */
166 return s
->match_prescale
[0];
167 case 0x44: /* TBPMR */
168 return s
->match_prescale
[1];
173 cpu_abort(cpu_single_env
, "TODO: Timer value read\n");
175 cpu_abort(cpu_single_env
, "gptm_read: Bad offset 0x%x\n", (int)offset
);
180 static void gptm_write(void *opaque
, target_phys_addr_t offset
, uint32_t value
)
182 gptm_state
*s
= (gptm_state
*)opaque
;
186 /* The timers should be disabled before changing the configuration.
187 We take advantage of this and defer everything until the timer
193 case 0x04: /* TAMR */
196 case 0x08: /* TBMR */
202 /* TODO: Implement pause. */
203 if ((oldval
^ value
) & 1) {
205 gptm_reload(s
, 0, 1);
210 if (((oldval
^ value
) & 0x100) && s
->config
>= 4) {
212 gptm_reload(s
, 1, 1);
219 s
->mask
= value
& 0x77;
225 case 0x28: /* TAILR */
226 s
->load
[0] = value
& 0xffff;
228 s
->load
[1] = value
>> 16;
231 case 0x2c: /* TBILR */
232 s
->load
[1] = value
& 0xffff;
234 case 0x30: /* TAMARCHR */
235 s
->match
[0] = value
& 0xffff;
237 s
->match
[1] = value
>> 16;
240 case 0x34: /* TBMATCHR */
241 s
->match
[1] = value
>> 16;
243 case 0x38: /* TAPR */
244 s
->prescale
[0] = value
;
246 case 0x3c: /* TBPR */
247 s
->prescale
[1] = value
;
249 case 0x40: /* TAPMR */
250 s
->match_prescale
[0] = value
;
252 case 0x44: /* TBPMR */
253 s
->match_prescale
[0] = value
;
256 cpu_abort(cpu_single_env
, "gptm_write: Bad offset 0x%x\n", (int)offset
);
261 static CPUReadMemoryFunc
*gptm_readfn
[] = {
267 static CPUWriteMemoryFunc
*gptm_writefn
[] = {
273 static void stellaris_gptm_init(uint32_t base
, qemu_irq irq
, qemu_irq trigger
)
278 s
= (gptm_state
*)qemu_mallocz(sizeof(gptm_state
));
281 s
->trigger
= trigger
;
282 s
->opaque
[0] = s
->opaque
[1] = s
;
284 iomemtype
= cpu_register_io_memory(0, gptm_readfn
,
286 cpu_register_physical_memory(base
, 0x00001000, iomemtype
);
287 s
->timer
[0] = qemu_new_timer(vm_clock
, gptm_tick
, &s
->opaque
[0]);
288 s
->timer
[1] = qemu_new_timer(vm_clock
, gptm_tick
, &s
->opaque
[1]);
289 /* ??? Save/restore. */
293 /* System controller. */
309 stellaris_board_info
*board
;
312 static void ssys_update(ssys_state
*s
)
314 qemu_set_irq(s
->irq
, (s
->int_status
& s
->int_mask
) != 0);
317 static uint32_t pllcfg_sandstorm
[16] = {
319 0x1ae0, /* 1.8432 Mhz */
321 0xd573, /* 2.4576 Mhz */
322 0x37a6, /* 3.57954 Mhz */
323 0x1ae2, /* 3.6864 Mhz */
325 0x98bc, /* 4.906 Mhz */
326 0x935b, /* 4.9152 Mhz */
328 0x4dee, /* 5.12 Mhz */
330 0x75db, /* 6.144 Mhz */
331 0x1ae6, /* 7.3728 Mhz */
333 0x585b /* 8.192 Mhz */
336 static uint32_t pllcfg_fury
[16] = {
338 0x1b20, /* 1.8432 Mhz */
340 0xf42b, /* 2.4576 Mhz */
341 0x37e3, /* 3.57954 Mhz */
342 0x1b21, /* 3.6864 Mhz */
344 0x98ee, /* 4.906 Mhz */
345 0xd5b4, /* 4.9152 Mhz */
347 0x4e27, /* 5.12 Mhz */
349 0xec1c, /* 6.144 Mhz */
350 0x1b23, /* 7.3728 Mhz */
352 0xb11c /* 8.192 Mhz */
355 static uint32_t ssys_read(void *opaque
, target_phys_addr_t offset
)
357 ssys_state
*s
= (ssys_state
*)opaque
;
361 case 0x000: /* DID0 */
362 return s
->board
->did0
;
363 case 0x004: /* DID1 */
364 return s
->board
->did1
;
365 case 0x008: /* DC0 */
366 return s
->board
->dc0
;
367 case 0x010: /* DC1 */
368 return s
->board
->dc1
;
369 case 0x014: /* DC2 */
370 return s
->board
->dc2
;
371 case 0x018: /* DC3 */
372 return s
->board
->dc3
;
373 case 0x01c: /* DC4 */
374 return s
->board
->dc4
;
375 case 0x030: /* PBORCTL */
377 case 0x034: /* LDOPCTL */
379 case 0x040: /* SRCR0 */
381 case 0x044: /* SRCR1 */
383 case 0x048: /* SRCR2 */
385 case 0x050: /* RIS */
386 return s
->int_status
;
387 case 0x054: /* IMC */
389 case 0x058: /* MISC */
390 return s
->int_status
& s
->int_mask
;
391 case 0x05c: /* RESC */
393 case 0x060: /* RCC */
395 case 0x064: /* PLLCFG */
398 xtal
= (s
->rcc
>> 6) & 0xf;
399 if (s
->board
->did0
& (1 << 16)) {
400 return pllcfg_fury
[xtal
];
402 return pllcfg_sandstorm
[xtal
];
405 case 0x100: /* RCGC0 */
407 case 0x104: /* RCGC1 */
409 case 0x108: /* RCGC2 */
411 case 0x110: /* SCGC0 */
413 case 0x114: /* SCGC1 */
415 case 0x118: /* SCGC2 */
417 case 0x120: /* DCGC0 */
419 case 0x124: /* DCGC1 */
421 case 0x128: /* DCGC2 */
423 case 0x150: /* CLKVCLR */
425 case 0x160: /* LDOARST */
428 cpu_abort(cpu_single_env
, "gptm_read: Bad offset 0x%x\n", (int)offset
);
433 static void ssys_write(void *opaque
, target_phys_addr_t offset
, uint32_t value
)
435 ssys_state
*s
= (ssys_state
*)opaque
;
439 case 0x030: /* PBORCTL */
440 s
->pborctl
= value
& 0xffff;
442 case 0x034: /* LDOPCTL */
443 s
->ldopctl
= value
& 0x1f;
445 case 0x040: /* SRCR0 */
446 case 0x044: /* SRCR1 */
447 case 0x048: /* SRCR2 */
448 fprintf(stderr
, "Peripheral reset not implemented\n");
450 case 0x054: /* IMC */
451 s
->int_mask
= value
& 0x7f;
453 case 0x058: /* MISC */
454 s
->int_status
&= ~value
;
456 case 0x05c: /* RESC */
457 s
->resc
= value
& 0x3f;
459 case 0x060: /* RCC */
460 if ((s
->rcc
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
462 s
->int_status
|= (1 << 6);
465 stellaris_clock_scale
= 5 * (((s
->rcc
>> 23) & 0xf) + 1);
467 case 0x100: /* RCGC0 */
470 case 0x104: /* RCGC1 */
473 case 0x108: /* RCGC2 */
476 case 0x110: /* SCGC0 */
479 case 0x114: /* SCGC1 */
482 case 0x118: /* SCGC2 */
485 case 0x120: /* DCGC0 */
488 case 0x124: /* DCGC1 */
491 case 0x128: /* DCGC2 */
494 case 0x150: /* CLKVCLR */
497 case 0x160: /* LDOARST */
501 cpu_abort(cpu_single_env
, "gptm_write: Bad offset 0x%x\n", (int)offset
);
506 static CPUReadMemoryFunc
*ssys_readfn
[] = {
512 static CPUWriteMemoryFunc
*ssys_writefn
[] = {
518 void ssys_reset(void *opaque
)
520 ssys_state
*s
= (ssys_state
*)opaque
;
529 static void stellaris_sys_init(uint32_t base
, qemu_irq irq
,
530 stellaris_board_info
* board
)
535 s
= (ssys_state
*)qemu_mallocz(sizeof(ssys_state
));
540 iomemtype
= cpu_register_io_memory(0, ssys_readfn
,
542 cpu_register_physical_memory(base
, 0x00001000, iomemtype
);
544 /* ??? Save/restore. */
548 /* I2C controller. */
561 } stellaris_i2c_state
;
563 #define STELLARIS_I2C_MCS_BUSY 0x01
564 #define STELLARIS_I2C_MCS_ERROR 0x02
565 #define STELLARIS_I2C_MCS_ADRACK 0x04
566 #define STELLARIS_I2C_MCS_DATACK 0x08
567 #define STELLARIS_I2C_MCS_ARBLST 0x10
568 #define STELLARIS_I2C_MCS_IDLE 0x20
569 #define STELLARIS_I2C_MCS_BUSBSY 0x40
571 static uint32_t stellaris_i2c_read(void *opaque
, target_phys_addr_t offset
)
573 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
580 /* We don't emulate timing, so the controller is never busy. */
581 return s
->mcs
| STELLARIS_I2C_MCS_IDLE
;
584 case 0x0c: /* MTPR */
586 case 0x10: /* MIMR */
588 case 0x14: /* MRIS */
590 case 0x18: /* MMIS */
591 return s
->mris
& s
->mimr
;
595 cpu_abort(cpu_single_env
, "strllaris_i2c_read: Bad offset 0x%x\n",
601 static void stellaris_i2c_update(stellaris_i2c_state
*s
)
605 level
= (s
->mris
& s
->mimr
) != 0;
606 qemu_set_irq(s
->irq
, level
);
609 static void stellaris_i2c_write(void *opaque
, target_phys_addr_t offset
,
612 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
617 s
->msa
= value
& 0xff;
620 if ((s
->mcr
& 0x10) == 0) {
621 /* Disabled. Do nothing. */
624 /* Grab the bus if this is starting a transfer. */
625 if ((value
& 2) && (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
626 if (i2c_start_transfer(s
->bus
, s
->msa
>> 1, s
->msa
& 1)) {
627 s
->mcs
|= STELLARIS_I2C_MCS_ARBLST
;
629 s
->mcs
&= ~STELLARIS_I2C_MCS_ARBLST
;
630 s
->mcs
|= STELLARIS_I2C_MCS_BUSBSY
;
633 /* If we don't have the bus then indicate an error. */
634 if (!i2c_bus_busy(s
->bus
)
635 || (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
636 s
->mcs
|= STELLARIS_I2C_MCS_ERROR
;
639 s
->mcs
&= ~STELLARIS_I2C_MCS_ERROR
;
641 /* Transfer a byte. */
642 /* TODO: Handle errors. */
645 s
->mdr
= i2c_recv(s
->bus
) & 0xff;
648 i2c_send(s
->bus
, s
->mdr
);
650 /* Raise an interrupt. */
654 /* Finish transfer. */
655 i2c_end_transfer(s
->bus
);
656 s
->mcs
&= ~STELLARIS_I2C_MCS_BUSBSY
;
660 s
->mdr
= value
& 0xff;
662 case 0x0c: /* MTPR */
663 s
->mtpr
= value
& 0xff;
665 case 0x10: /* MIMR */
668 case 0x1c: /* MICR */
673 cpu_abort(cpu_single_env
,
674 "stellaris_i2c_write: Loopback not implemented\n");
676 cpu_abort(cpu_single_env
,
677 "stellaris_i2c_write: Slave mode not implemented\n");
678 s
->mcr
= value
& 0x31;
681 cpu_abort(cpu_single_env
, "stellaris_i2c_write: Bad offset 0x%x\n",
684 stellaris_i2c_update(s
);
687 static void stellaris_i2c_reset(stellaris_i2c_state
*s
)
689 if (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
)
690 i2c_end_transfer(s
->bus
);
699 stellaris_i2c_update(s
);
702 static CPUReadMemoryFunc
*stellaris_i2c_readfn
[] = {
708 static CPUWriteMemoryFunc
*stellaris_i2c_writefn
[] = {
714 static void stellaris_i2c_init(uint32_t base
, qemu_irq irq
, i2c_bus
*bus
)
716 stellaris_i2c_state
*s
;
719 s
= (stellaris_i2c_state
*)qemu_mallocz(sizeof(stellaris_i2c_state
));
724 iomemtype
= cpu_register_io_memory(0, stellaris_i2c_readfn
,
725 stellaris_i2c_writefn
, s
);
726 cpu_register_physical_memory(base
, 0x00001000, iomemtype
);
727 /* ??? For now we only implement the master interface. */
728 stellaris_i2c_reset(s
);
731 /* Analogue to Digital Converter. This is only partially implemented,
732 enough for applications that use a combined ADC and timer tick. */
734 #define STELLARIS_ADC_EM_CONTROLLER 0
735 #define STELLARIS_ADC_EM_COMP 1
736 #define STELLARIS_ADC_EM_EXTERNAL 4
737 #define STELLARIS_ADC_EM_TIMER 5
738 #define STELLARIS_ADC_EM_PWM0 6
739 #define STELLARIS_ADC_EM_PWM1 7
740 #define STELLARIS_ADC_EM_PWM2 8
742 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
743 #define STELLARIS_ADC_FIFO_FULL 0x1000
763 } stellaris_adc_state
;
765 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state
*s
, int n
)
769 tail
= s
->fifo
[n
].state
& 0xf;
770 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_EMPTY
) {
773 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf) | ((tail
+ 1) & 0xf);
774 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_FULL
;
775 if (tail
+ 1 == ((s
->fifo
[n
].state
>> 4) & 0xf))
776 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_EMPTY
;
778 return s
->fifo
[n
].data
[tail
];
781 static void stellaris_adc_fifo_write(stellaris_adc_state
*s
, int n
,
786 head
= (s
->fifo
[n
].state
>> 4) & 0xf;
787 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_FULL
) {
791 s
->fifo
[n
].data
[head
] = value
;
792 head
= (head
+ 1) & 0xf;
793 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_EMPTY
;
794 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf0) | (head
<< 4);
795 if ((s
->fifo
[n
].state
& 0xf) == head
)
796 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_FULL
;
799 static void stellaris_adc_update(stellaris_adc_state
*s
)
803 level
= (s
->ris
& s
->im
) != 0;
804 qemu_set_irq(s
->irq
, level
);
807 static void stellaris_adc_trigger(void *opaque
, int irq
, int level
)
809 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
810 /* Some applications use the ADC as a random number source, so introduce
811 some variation into the signal. */
812 static uint32_t noise
= 0;
814 if ((s
->actss
& 1) == 0) {
818 noise
= noise
* 314159 + 1;
819 /* ??? actual inputs not implemented. Return an arbitrary value. */
820 stellaris_adc_fifo_write(s
, 0, 0x200 + ((noise
>> 16) & 7));
822 stellaris_adc_update(s
);
825 static void stellaris_adc_reset(stellaris_adc_state
*s
)
829 for (n
= 0; n
< 4; n
++) {
832 s
->fifo
[n
].state
= STELLARIS_ADC_FIFO_EMPTY
;
836 static uint32_t stellaris_adc_read(void *opaque
, target_phys_addr_t offset
)
838 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
840 /* TODO: Implement this. */
842 if (offset
>= 0x40 && offset
< 0xc0) {
844 n
= (offset
- 0x40) >> 5;
845 switch (offset
& 0x1f) {
846 case 0x00: /* SSMUX */
848 case 0x04: /* SSCTL */
850 case 0x08: /* SSFIFO */
851 return stellaris_adc_fifo_read(s
, n
);
852 case 0x0c: /* SSFSTAT */
853 return s
->fifo
[n
].state
;
859 case 0x00: /* ACTSS */
866 return s
->ris
& s
->im
;
867 case 0x10: /* OSTAT */
869 case 0x14: /* EMUX */
871 case 0x18: /* USTAT */
873 case 0x20: /* SSPRI */
878 cpu_abort(cpu_single_env
, "strllaris_adc_read: Bad offset 0x%x\n",
884 static void stellaris_adc_write(void *opaque
, target_phys_addr_t offset
,
887 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
889 /* TODO: Implement this. */
891 if (offset
>= 0x40 && offset
< 0xc0) {
893 n
= (offset
- 0x40) >> 5;
894 switch (offset
& 0x1f) {
895 case 0x00: /* SSMUX */
896 s
->ssmux
[n
] = value
& 0x33333333;
898 case 0x04: /* SSCTL */
900 cpu_abort(cpu_single_env
, "ADC: Unimplemented sequence %x\n",
910 case 0x00: /* ACTSS */
911 s
->actss
= value
& 0xf;
913 cpu_abort(cpu_single_env
,
914 "Not implemented: ADC sequencers 1-3\n");
923 case 0x10: /* OSTAT */
926 case 0x14: /* EMUX */
929 case 0x18: /* USTAT */
932 case 0x20: /* SSPRI */
935 case 0x28: /* PSSI */
936 cpu_abort(cpu_single_env
, "Not implemented: ADC sample initiate\n");
942 cpu_abort(cpu_single_env
, "stellaris_adc_write: Bad offset 0x%x\n",
945 stellaris_adc_update(s
);
948 static CPUReadMemoryFunc
*stellaris_adc_readfn
[] = {
954 static CPUWriteMemoryFunc
*stellaris_adc_writefn
[] = {
960 static qemu_irq
stellaris_adc_init(uint32_t base
, qemu_irq irq
)
962 stellaris_adc_state
*s
;
966 s
= (stellaris_adc_state
*)qemu_mallocz(sizeof(stellaris_adc_state
));
970 iomemtype
= cpu_register_io_memory(0, stellaris_adc_readfn
,
971 stellaris_adc_writefn
, s
);
972 cpu_register_physical_memory(base
, 0x00001000, iomemtype
);
973 stellaris_adc_reset(s
);
974 qi
= qemu_allocate_irqs(stellaris_adc_trigger
, s
, 1);
979 static stellaris_board_info stellaris_boards
[] = {
983 0x001f001f, /* dc0 */
993 0x00ff007f, /* dc0 */
1002 static void stellaris_init(const char *kernel_filename
, const char *cpu_model
,
1003 DisplayState
*ds
, stellaris_board_info
*board
)
1005 static const int uart_irq
[] = {5, 6, 33, 34};
1006 static const int timer_irq
[] = {19, 21, 23, 35};
1007 static const uint32_t gpio_addr
[7] =
1008 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1009 0x40024000, 0x40025000, 0x40026000};
1010 static const int gpio_irq
[7] = {0, 1, 2, 3, 4, 30, 31};
1013 qemu_irq
*gpio_in
[5];
1014 qemu_irq
*gpio_out
[5];
1021 flash_size
= ((board
->dc0
& 0xffff) + 1) << 1;
1022 sram_size
= (board
->dc0
>> 18) + 1;
1023 pic
= armv7m_init(flash_size
, sram_size
, kernel_filename
, cpu_model
);
1025 if (board
->dc1
& (1 << 16)) {
1026 adc
= stellaris_adc_init(0x40038000, pic
[14]);
1030 for (i
= 0; i
< 4; i
++) {
1031 if (board
->dc2
& (0x10000 << i
)) {
1032 stellaris_gptm_init(0x40030000 + i
* 0x1000,
1033 pic
[timer_irq
[i
]], adc
);
1037 stellaris_sys_init(0x400fe000, pic
[28], board
);
1039 for (i
= 0; i
< 7; i
++) {
1040 if (board
->dc4
& (1 << i
)) {
1041 gpio_in
[i
] = pl061_init(gpio_addr
[i
], pic
[gpio_irq
[i
]],
1046 if (board
->dc2
& (1 << 12)) {
1047 i2c
= i2c_init_bus();
1048 stellaris_i2c_init(0x40020000, pic
[8], i2c
);
1049 if (board
->oled
== OLED_I2C
) {
1050 ssd0303_init(ds
, i2c
, 0x3d);
1054 for (i
= 0; i
< 4; i
++) {
1055 if (board
->dc2
& (1 << i
)) {
1056 pl011_init(0x4000c000 + i
* 0x1000, pic
[uart_irq
[i
]],
1057 serial_hds
[i
], PL011_LUMINARY
);
1060 if (board
->dc2
& (1 << 4)) {
1061 if (board
->oled
== OLED_SSI
) {
1063 /* FIXME: Implement chip select for OLED/MMC. */
1064 oled
= ssd0323_init(ds
, &gpio_out
[2][7]);
1065 pl022_init(0x40008000, pic
[7], ssd0323_xfer_ssi
, oled
);
1067 pl022_init(0x40008000, pic
[7], NULL
, NULL
);
1072 /* FIXME: Figure out how to generate these from stellaris_boards. */
1073 static void lm3s811evb_init(int ram_size
, int vga_ram_size
,
1074 const char *boot_device
, DisplayState
*ds
,
1075 const char **fd_filename
, int snapshot
,
1076 const char *kernel_filename
, const char *kernel_cmdline
,
1077 const char *initrd_filename
, const char *cpu_model
)
1079 stellaris_init(kernel_filename
, cpu_model
, ds
, &stellaris_boards
[0]);
1082 static void lm3s6965evb_init(int ram_size
, int vga_ram_size
,
1083 const char *boot_device
, DisplayState
*ds
,
1084 const char **fd_filename
, int snapshot
,
1085 const char *kernel_filename
, const char *kernel_cmdline
,
1086 const char *initrd_filename
, const char *cpu_model
)
1088 stellaris_init(kernel_filename
, cpu_model
, ds
, &stellaris_boards
[1]);
1091 QEMUMachine lm3s811evb_machine
= {
1093 "Stellaris LM3S811EVB",
1097 QEMUMachine lm3s6965evb_machine
= {
1099 "Stellaris LM3S6965EVB",