2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu-timer.h"
28 #include "sparc32_dma.h"
33 #include "firmware_abi.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
48 * Sun4m architecture was used in the following machines:
50 * SPARCserver 6xxMP/xx
51 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
52 * SPARCclassic X (4/10)
53 * SPARCstation LX/ZX (4/30)
54 * SPARCstation Voyager
55 * SPARCstation 10/xx, SPARCserver 10/xx
56 * SPARCstation 5, SPARCserver 5
57 * SPARCstation 20/xx, SPARCserver 20
60 * Sun4d architecture was used in the following machines:
65 * Sun4c architecture was used in the following machines:
66 * SPARCstation 1/1+, SPARCserver 1/1+
72 * See for example: http://www.sunhelp.org/faq/sunref1.html
76 #define DPRINTF(fmt, ...) \
77 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
79 #define DPRINTF(fmt, ...)
82 #define KERNEL_LOAD_ADDR 0x00004000
83 #define CMDLINE_ADDR 0x007ff000
84 #define INITRD_LOAD_ADDR 0x00800000
85 #define PROM_SIZE_MAX (1024 * 1024)
86 #define PROM_VADDR 0xffd00000
87 #define PROM_FILENAME "openbios-sparc32"
88 #define CFG_ADDR 0xd00000510ULL
89 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
95 #define ESCC_CLOCK 4915200
98 target_phys_addr_t iommu_base
, iommu_pad_base
, iommu_pad_len
, slavio_base
;
99 target_phys_addr_t intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
100 target_phys_addr_t serial_base
, fd_base
;
101 target_phys_addr_t afx_base
, idreg_base
, dma_base
, esp_base
, le_base
;
102 target_phys_addr_t tcx_base
, cs_base
, apc_base
, aux1_base
, aux2_base
;
103 target_phys_addr_t bpp_base
, dbri_base
, sx_base
;
105 target_phys_addr_t reg_base
, vram_base
;
107 target_phys_addr_t ecc_base
;
108 uint32_t ecc_version
;
109 uint8_t nvram_machine_id
;
111 uint32_t iommu_version
;
113 const char * const default_cpu_model
;
116 #define MAX_IOUNITS 5
119 target_phys_addr_t iounit_bases
[MAX_IOUNITS
], slavio_base
;
120 target_phys_addr_t counter_base
, nvram_base
, ms_kb_base
;
121 target_phys_addr_t serial_base
;
122 target_phys_addr_t espdma_base
, esp_base
;
123 target_phys_addr_t ledma_base
, le_base
;
124 target_phys_addr_t tcx_base
;
125 target_phys_addr_t sbi_base
;
126 uint8_t nvram_machine_id
;
128 uint32_t iounit_version
;
130 const char * const default_cpu_model
;
134 target_phys_addr_t iommu_base
, slavio_base
;
135 target_phys_addr_t intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
136 target_phys_addr_t serial_base
, fd_base
;
137 target_phys_addr_t idreg_base
, dma_base
, esp_base
, le_base
;
138 target_phys_addr_t tcx_base
, aux1_base
;
139 uint8_t nvram_machine_id
;
141 uint32_t iommu_version
;
143 const char * const default_cpu_model
;
146 int DMA_get_channel_mode (int nchan
)
150 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
154 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
158 void DMA_hold_DREQ (int nchan
) {}
159 void DMA_release_DREQ (int nchan
) {}
160 void DMA_schedule(int nchan
) {}
162 void DMA_init(int high_page_enable
, qemu_irq
*cpu_request_exit
)
166 void DMA_register_channel (int nchan
,
167 DMA_transfer_handler transfer_handler
,
172 static int fw_cfg_boot_set(void *opaque
, const char *boot_device
)
174 fw_cfg_add_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
178 static void nvram_init(M48t59State
*nvram
, uint8_t *macaddr
,
179 const char *cmdline
, const char *boot_devices
,
180 ram_addr_t RAM_size
, uint32_t kernel_size
,
181 int width
, int height
, int depth
,
182 int nvram_machine_id
, const char *arch
)
186 uint8_t image
[0x1ff0];
187 struct OpenBIOS_nvpart_v1
*part_header
;
189 memset(image
, '\0', sizeof(image
));
193 // OpenBIOS nvram variables
194 // Variable partition
195 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
196 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
197 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "system");
199 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
200 for (i
= 0; i
< nb_prom_envs
; i
++)
201 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
206 end
= start
+ ((end
- start
+ 15) & ~15);
207 OpenBIOS_finish_partition(part_header
, end
- start
);
211 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
212 part_header
->signature
= OPENBIOS_PART_FREE
;
213 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "free");
216 OpenBIOS_finish_partition(part_header
, end
- start
);
218 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
,
221 for (i
= 0; i
< sizeof(image
); i
++)
222 m48t59_write(nvram
, i
, image
[i
]);
225 static DeviceState
*slavio_intctl
;
227 void pic_info(Monitor
*mon
)
230 slavio_pic_info(mon
, slavio_intctl
);
233 void irq_info(Monitor
*mon
)
236 slavio_irq_info(mon
, slavio_intctl
);
239 void cpu_check_irqs(CPUState
*env
)
241 if (env
->pil_in
&& (env
->interrupt_index
== 0 ||
242 (env
->interrupt_index
& ~15) == TT_EXTINT
)) {
245 for (i
= 15; i
> 0; i
--) {
246 if (env
->pil_in
& (1 << i
)) {
247 int old_interrupt
= env
->interrupt_index
;
249 env
->interrupt_index
= TT_EXTINT
| i
;
250 if (old_interrupt
!= env
->interrupt_index
) {
251 DPRINTF("Set CPU IRQ %d\n", i
);
252 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
257 } else if (!env
->pil_in
&& (env
->interrupt_index
& ~15) == TT_EXTINT
) {
258 DPRINTF("Reset CPU IRQ %d\n", env
->interrupt_index
& 15);
259 env
->interrupt_index
= 0;
260 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
264 static void cpu_set_irq(void *opaque
, int irq
, int level
)
266 CPUState
*env
= opaque
;
269 DPRINTF("Raise CPU IRQ %d\n", irq
);
271 env
->pil_in
|= 1 << irq
;
274 DPRINTF("Lower CPU IRQ %d\n", irq
);
275 env
->pil_in
&= ~(1 << irq
);
280 static void dummy_cpu_set_irq(void *opaque
, int irq
, int level
)
284 static void main_cpu_reset(void *opaque
)
286 CPUState
*env
= opaque
;
292 static void secondary_cpu_reset(void *opaque
)
294 CPUState
*env
= opaque
;
300 static void cpu_halt_signal(void *opaque
, int irq
, int level
)
302 if (level
&& cpu_single_env
)
303 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HALT
);
306 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
308 return addr
- 0xf0000000ULL
;
311 static unsigned long sun4m_load_kernel(const char *kernel_filename
,
312 const char *initrd_filename
,
317 long initrd_size
, kernel_size
;
320 linux_boot
= (kernel_filename
!= NULL
);
331 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
332 NULL
, NULL
, NULL
, 1, ELF_MACHINE
, 0);
334 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
335 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
338 kernel_size
= load_image_targphys(kernel_filename
,
340 RAM_size
- KERNEL_LOAD_ADDR
);
341 if (kernel_size
< 0) {
342 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
349 if (initrd_filename
) {
350 initrd_size
= load_image_targphys(initrd_filename
,
352 RAM_size
- INITRD_LOAD_ADDR
);
353 if (initrd_size
< 0) {
354 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
359 if (initrd_size
> 0) {
360 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
361 ptr
= rom_ptr(KERNEL_LOAD_ADDR
+ i
);
362 if (ldl_p(ptr
) == 0x48647253) { // HdrS
363 stl_p(ptr
+ 16, INITRD_LOAD_ADDR
);
364 stl_p(ptr
+ 20, initrd_size
);
373 static void *iommu_init(target_phys_addr_t addr
, uint32_t version
, qemu_irq irq
)
378 dev
= qdev_create(NULL
, "iommu");
379 qdev_prop_set_uint32(dev
, "version", version
);
380 qdev_init_nofail(dev
);
381 s
= sysbus_from_qdev(dev
);
382 sysbus_connect_irq(s
, 0, irq
);
383 sysbus_mmio_map(s
, 0, addr
);
388 static void *sparc32_dma_init(target_phys_addr_t daddr
, qemu_irq parent_irq
,
389 void *iommu
, qemu_irq
*dev_irq
)
394 dev
= qdev_create(NULL
, "sparc32_dma");
395 qdev_prop_set_ptr(dev
, "iommu_opaque", iommu
);
396 qdev_init_nofail(dev
);
397 s
= sysbus_from_qdev(dev
);
398 sysbus_connect_irq(s
, 0, parent_irq
);
399 *dev_irq
= qdev_get_gpio_in(dev
, 0);
400 sysbus_mmio_map(s
, 0, daddr
);
405 static void lance_init(NICInfo
*nd
, target_phys_addr_t leaddr
,
406 void *dma_opaque
, qemu_irq irq
)
412 qemu_check_nic_model(&nd_table
[0], "lance");
414 dev
= qdev_create(NULL
, "lance");
415 qdev_set_nic_properties(dev
, nd
);
416 qdev_prop_set_ptr(dev
, "dma", dma_opaque
);
417 qdev_init_nofail(dev
);
418 s
= sysbus_from_qdev(dev
);
419 sysbus_mmio_map(s
, 0, leaddr
);
420 sysbus_connect_irq(s
, 0, irq
);
421 reset
= qdev_get_gpio_in(dev
, 0);
422 qdev_connect_gpio_out(dma_opaque
, 0, reset
);
425 static DeviceState
*slavio_intctl_init(target_phys_addr_t addr
,
426 target_phys_addr_t addrg
,
427 qemu_irq
**parent_irq
)
433 dev
= qdev_create(NULL
, "slavio_intctl");
434 qdev_init_nofail(dev
);
436 s
= sysbus_from_qdev(dev
);
438 for (i
= 0; i
< MAX_CPUS
; i
++) {
439 for (j
= 0; j
< MAX_PILS
; j
++) {
440 sysbus_connect_irq(s
, i
* MAX_PILS
+ j
, parent_irq
[i
][j
]);
443 sysbus_mmio_map(s
, 0, addrg
);
444 for (i
= 0; i
< MAX_CPUS
; i
++) {
445 sysbus_mmio_map(s
, i
+ 1, addr
+ i
* TARGET_PAGE_SIZE
);
451 #define SYS_TIMER_OFFSET 0x10000ULL
452 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
454 static void slavio_timer_init_all(target_phys_addr_t addr
, qemu_irq master_irq
,
455 qemu_irq
*cpu_irqs
, unsigned int num_cpus
)
461 dev
= qdev_create(NULL
, "slavio_timer");
462 qdev_prop_set_uint32(dev
, "num_cpus", num_cpus
);
463 qdev_init_nofail(dev
);
464 s
= sysbus_from_qdev(dev
);
465 sysbus_connect_irq(s
, 0, master_irq
);
466 sysbus_mmio_map(s
, 0, addr
+ SYS_TIMER_OFFSET
);
468 for (i
= 0; i
< MAX_CPUS
; i
++) {
469 sysbus_mmio_map(s
, i
+ 1, addr
+ (target_phys_addr_t
)CPU_TIMER_OFFSET(i
));
470 sysbus_connect_irq(s
, i
+ 1, cpu_irqs
[i
]);
474 #define MISC_LEDS 0x01600000
475 #define MISC_CFG 0x01800000
476 #define MISC_DIAG 0x01a00000
477 #define MISC_MDM 0x01b00000
478 #define MISC_SYS 0x01f00000
480 static void slavio_misc_init(target_phys_addr_t base
,
481 target_phys_addr_t aux1_base
,
482 target_phys_addr_t aux2_base
, qemu_irq irq
,
488 dev
= qdev_create(NULL
, "slavio_misc");
489 qdev_init_nofail(dev
);
490 s
= sysbus_from_qdev(dev
);
492 /* 8 bit registers */
494 sysbus_mmio_map(s
, 0, base
+ MISC_CFG
);
496 sysbus_mmio_map(s
, 1, base
+ MISC_DIAG
);
498 sysbus_mmio_map(s
, 2, base
+ MISC_MDM
);
499 /* 16 bit registers */
500 /* ss600mp diag LEDs */
501 sysbus_mmio_map(s
, 3, base
+ MISC_LEDS
);
502 /* 32 bit registers */
504 sysbus_mmio_map(s
, 4, base
+ MISC_SYS
);
507 /* AUX 1 (Misc System Functions) */
508 sysbus_mmio_map(s
, 5, aux1_base
);
511 /* AUX 2 (Software Powerdown Control) */
512 sysbus_mmio_map(s
, 6, aux2_base
);
514 sysbus_connect_irq(s
, 0, irq
);
515 sysbus_connect_irq(s
, 1, fdc_tc
);
516 qemu_system_powerdown
= qdev_get_gpio_in(dev
, 0);
519 static void ecc_init(target_phys_addr_t base
, qemu_irq irq
, uint32_t version
)
524 dev
= qdev_create(NULL
, "eccmemctl");
525 qdev_prop_set_uint32(dev
, "version", version
);
526 qdev_init_nofail(dev
);
527 s
= sysbus_from_qdev(dev
);
528 sysbus_connect_irq(s
, 0, irq
);
529 sysbus_mmio_map(s
, 0, base
);
530 if (version
== 0) { // SS-600MP only
531 sysbus_mmio_map(s
, 1, base
+ 0x1000);
535 static void apc_init(target_phys_addr_t power_base
, qemu_irq cpu_halt
)
540 dev
= qdev_create(NULL
, "apc");
541 qdev_init_nofail(dev
);
542 s
= sysbus_from_qdev(dev
);
543 /* Power management (APC) XXX: not a Slavio device */
544 sysbus_mmio_map(s
, 0, power_base
);
545 sysbus_connect_irq(s
, 0, cpu_halt
);
548 static void tcx_init(target_phys_addr_t addr
, int vram_size
, int width
,
549 int height
, int depth
)
554 dev
= qdev_create(NULL
, "SUNW,tcx");
555 qdev_prop_set_taddr(dev
, "addr", addr
);
556 qdev_prop_set_uint32(dev
, "vram_size", vram_size
);
557 qdev_prop_set_uint16(dev
, "width", width
);
558 qdev_prop_set_uint16(dev
, "height", height
);
559 qdev_prop_set_uint16(dev
, "depth", depth
);
560 qdev_init_nofail(dev
);
561 s
= sysbus_from_qdev(dev
);
563 sysbus_mmio_map(s
, 0, addr
+ 0x00800000ULL
);
565 sysbus_mmio_map(s
, 1, addr
+ 0x00200000ULL
);
567 sysbus_mmio_map(s
, 2, addr
+ 0x00700000ULL
);
568 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
569 sysbus_mmio_map(s
, 3, addr
+ 0x00301000ULL
);
572 sysbus_mmio_map(s
, 4, addr
+ 0x02000000ULL
);
574 sysbus_mmio_map(s
, 5, addr
+ 0x0a000000ULL
);
576 /* THC 8 bit (dummy) */
577 sysbus_mmio_map(s
, 4, addr
+ 0x00300000ULL
);
581 /* NCR89C100/MACIO Internal ID register */
582 static const uint8_t idreg_data
[] = { 0xfe, 0x81, 0x01, 0x03 };
584 static void idreg_init(target_phys_addr_t addr
)
589 dev
= qdev_create(NULL
, "macio_idreg");
590 qdev_init_nofail(dev
);
591 s
= sysbus_from_qdev(dev
);
593 sysbus_mmio_map(s
, 0, addr
);
594 cpu_physical_memory_write_rom(addr
, idreg_data
, sizeof(idreg_data
));
597 static int idreg_init1(SysBusDevice
*dev
)
599 ram_addr_t idreg_offset
;
601 idreg_offset
= qemu_ram_alloc(NULL
, "sun4m.idreg", sizeof(idreg_data
));
602 sysbus_init_mmio(dev
, sizeof(idreg_data
), idreg_offset
| IO_MEM_ROM
);
606 static SysBusDeviceInfo idreg_info
= {
608 .qdev
.name
= "macio_idreg",
609 .qdev
.size
= sizeof(SysBusDevice
),
612 static void idreg_register_devices(void)
614 sysbus_register_withprop(&idreg_info
);
617 device_init(idreg_register_devices
);
619 /* SS-5 TCX AFX register */
620 static void afx_init(target_phys_addr_t addr
)
625 dev
= qdev_create(NULL
, "tcx_afx");
626 qdev_init_nofail(dev
);
627 s
= sysbus_from_qdev(dev
);
629 sysbus_mmio_map(s
, 0, addr
);
632 static int afx_init1(SysBusDevice
*dev
)
634 ram_addr_t afx_offset
;
636 afx_offset
= qemu_ram_alloc(NULL
, "sun4m.afx", 4);
637 sysbus_init_mmio(dev
, 4, afx_offset
| IO_MEM_RAM
);
641 static SysBusDeviceInfo afx_info
= {
643 .qdev
.name
= "tcx_afx",
644 .qdev
.size
= sizeof(SysBusDevice
),
647 static void afx_register_devices(void)
649 sysbus_register_withprop(&afx_info
);
652 device_init(afx_register_devices
);
654 /* Boot PROM (OpenBIOS) */
655 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
657 target_phys_addr_t
*base_addr
= (target_phys_addr_t
*)opaque
;
658 return addr
+ *base_addr
- PROM_VADDR
;
661 static void prom_init(target_phys_addr_t addr
, const char *bios_name
)
668 dev
= qdev_create(NULL
, "openprom");
669 qdev_init_nofail(dev
);
670 s
= sysbus_from_qdev(dev
);
672 sysbus_mmio_map(s
, 0, addr
);
675 if (bios_name
== NULL
) {
676 bios_name
= PROM_FILENAME
;
678 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
680 ret
= load_elf(filename
, translate_prom_address
, &addr
, NULL
,
681 NULL
, NULL
, 1, ELF_MACHINE
, 0);
682 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
683 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
689 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
690 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
695 static int prom_init1(SysBusDevice
*dev
)
697 ram_addr_t prom_offset
;
699 prom_offset
= qemu_ram_alloc(NULL
, "sun4m.prom", PROM_SIZE_MAX
);
700 sysbus_init_mmio(dev
, PROM_SIZE_MAX
, prom_offset
| IO_MEM_ROM
);
704 static SysBusDeviceInfo prom_info
= {
706 .qdev
.name
= "openprom",
707 .qdev
.size
= sizeof(SysBusDevice
),
708 .qdev
.props
= (Property
[]) {
709 {/* end of property list */}
713 static void prom_register_devices(void)
715 sysbus_register_withprop(&prom_info
);
718 device_init(prom_register_devices
);
720 typedef struct RamDevice
727 static int ram_init1(SysBusDevice
*dev
)
729 ram_addr_t RAM_size
, ram_offset
;
730 RamDevice
*d
= FROM_SYSBUS(RamDevice
, dev
);
734 ram_offset
= qemu_ram_alloc(NULL
, "sun4m.ram", RAM_size
);
735 sysbus_init_mmio(dev
, RAM_size
, ram_offset
);
739 static void ram_init(target_phys_addr_t addr
, ram_addr_t RAM_size
,
747 if ((uint64_t)RAM_size
> max_mem
) {
749 "qemu: Too much memory for this machine: %d, maximum %d\n",
750 (unsigned int)(RAM_size
/ (1024 * 1024)),
751 (unsigned int)(max_mem
/ (1024 * 1024)));
754 dev
= qdev_create(NULL
, "memory");
755 s
= sysbus_from_qdev(dev
);
757 d
= FROM_SYSBUS(RamDevice
, s
);
759 qdev_init_nofail(dev
);
761 sysbus_mmio_map(s
, 0, addr
);
764 static SysBusDeviceInfo ram_info
= {
766 .qdev
.name
= "memory",
767 .qdev
.size
= sizeof(RamDevice
),
768 .qdev
.props
= (Property
[]) {
769 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
770 DEFINE_PROP_END_OF_LIST(),
774 static void ram_register_devices(void)
776 sysbus_register_withprop(&ram_info
);
779 device_init(ram_register_devices
);
781 static void cpu_devinit(const char *cpu_model
, unsigned int id
,
782 uint64_t prom_addr
, qemu_irq
**cpu_irqs
)
786 env
= cpu_init(cpu_model
);
788 fprintf(stderr
, "qemu: Unable to find Sparc CPU definition\n");
792 cpu_sparc_set_id(env
, id
);
794 qemu_register_reset(main_cpu_reset
, env
);
796 qemu_register_reset(secondary_cpu_reset
, env
);
799 *cpu_irqs
= qemu_allocate_irqs(cpu_set_irq
, env
, MAX_PILS
);
800 env
->prom_addr
= prom_addr
;
803 static void sun4m_hw_init(const struct sun4m_hwdef
*hwdef
, ram_addr_t RAM_size
,
804 const char *boot_device
,
805 const char *kernel_filename
,
806 const char *kernel_cmdline
,
807 const char *initrd_filename
, const char *cpu_model
)
810 void *iommu
, *espdma
, *ledma
, *nvram
;
811 qemu_irq
*cpu_irqs
[MAX_CPUS
], slavio_irq
[32], slavio_cpu_irq
[MAX_CPUS
],
812 espdma_irq
, ledma_irq
;
816 unsigned long kernel_size
;
817 DriveInfo
*fd
[MAX_FD
];
819 unsigned int num_vsimms
;
823 cpu_model
= hwdef
->default_cpu_model
;
825 for(i
= 0; i
< smp_cpus
; i
++) {
826 cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
829 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
830 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
834 ram_init(0, RAM_size
, hwdef
->max_mem
);
835 /* models without ECC don't trap when missing ram is accessed */
836 if (!hwdef
->ecc_base
) {
837 empty_slot_init(RAM_size
, hwdef
->max_mem
- RAM_size
);
840 prom_init(hwdef
->slavio_base
, bios_name
);
842 slavio_intctl
= slavio_intctl_init(hwdef
->intctl_base
,
843 hwdef
->intctl_base
+ 0x10000ULL
,
846 for (i
= 0; i
< 32; i
++) {
847 slavio_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, i
);
849 for (i
= 0; i
< MAX_CPUS
; i
++) {
850 slavio_cpu_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, 32 + i
);
853 if (hwdef
->idreg_base
) {
854 idreg_init(hwdef
->idreg_base
);
857 if (hwdef
->afx_base
) {
858 afx_init(hwdef
->afx_base
);
861 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
864 if (hwdef
->iommu_pad_base
) {
865 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
866 Software shouldn't use aliased addresses, neither should it crash
867 when does. Using empty_slot instead of aliasing can help with
868 debugging such accesses */
869 empty_slot_init(hwdef
->iommu_pad_base
,hwdef
->iommu_pad_len
);
872 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[18],
875 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
876 slavio_irq
[16], iommu
, &ledma_irq
);
878 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
879 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
883 if (num_vsimms
== 0) {
884 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
888 for (i
= num_vsimms
; i
< MAX_VSIMMS
; i
++) {
889 /* vsimm registers probed by OBP */
890 if (hwdef
->vsimm
[i
].reg_base
) {
891 empty_slot_init(hwdef
->vsimm
[i
].reg_base
, 0x2000);
895 if (hwdef
->sx_base
) {
896 empty_slot_init(hwdef
->sx_base
, 0x2000);
899 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
901 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 8);
903 slavio_timer_init_all(hwdef
->counter_base
, slavio_irq
[19], slavio_cpu_irq
, smp_cpus
);
905 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[14],
906 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
907 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
908 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
909 escc_init(hwdef
->serial_base
, slavio_irq
[15], slavio_irq
[15],
910 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
912 cpu_halt
= qemu_allocate_irqs(cpu_halt_signal
, NULL
, 1);
913 slavio_misc_init(hwdef
->slavio_base
, hwdef
->aux1_base
, hwdef
->aux2_base
,
914 slavio_irq
[30], fdc_tc
);
916 if (hwdef
->apc_base
) {
917 apc_init(hwdef
->apc_base
, cpu_halt
[0]);
920 if (hwdef
->fd_base
) {
921 /* there is zero or one floppy drive */
922 memset(fd
, 0, sizeof(fd
));
923 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
924 sun4m_fdctrl_init(slavio_irq
[22], hwdef
->fd_base
, fd
,
928 if (drive_get_max_bus(IF_SCSI
) > 0) {
929 fprintf(stderr
, "qemu: too many SCSI bus\n");
933 esp_reset
= qdev_get_gpio_in(espdma
, 0);
934 esp_init(hwdef
->esp_base
, 2,
935 espdma_memory_read
, espdma_memory_write
,
936 espdma
, espdma_irq
, &esp_reset
);
939 if (hwdef
->cs_base
) {
940 sysbus_create_simple("SUNW,CS4231", hwdef
->cs_base
,
944 if (hwdef
->dbri_base
) {
945 /* ISDN chip with attached CS4215 audio codec */
947 empty_slot_init(hwdef
->dbri_base
+0x1000, 0x30);
949 empty_slot_init(hwdef
->dbri_base
+0x10000, 0x100);
952 if (hwdef
->bpp_base
) {
954 empty_slot_init(hwdef
->bpp_base
, 0x20);
957 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
960 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
961 boot_device
, RAM_size
, kernel_size
, graphic_width
,
962 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
966 ecc_init(hwdef
->ecc_base
, slavio_irq
[28],
969 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
970 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
971 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
972 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
973 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
974 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
975 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
976 if (kernel_cmdline
) {
977 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
978 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
979 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
980 (uint8_t*)strdup(kernel_cmdline
),
981 strlen(kernel_cmdline
) + 1);
982 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
983 strlen(kernel_cmdline
) + 1);
985 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
986 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
988 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
989 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
990 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
991 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1009 static const struct sun4m_hwdef sun4m_hwdefs
[] = {
1012 .iommu_base
= 0x10000000,
1013 .iommu_pad_base
= 0x10004000,
1014 .iommu_pad_len
= 0x0fffb000,
1015 .tcx_base
= 0x50000000,
1016 .cs_base
= 0x6c000000,
1017 .slavio_base
= 0x70000000,
1018 .ms_kb_base
= 0x71000000,
1019 .serial_base
= 0x71100000,
1020 .nvram_base
= 0x71200000,
1021 .fd_base
= 0x71400000,
1022 .counter_base
= 0x71d00000,
1023 .intctl_base
= 0x71e00000,
1024 .idreg_base
= 0x78000000,
1025 .dma_base
= 0x78400000,
1026 .esp_base
= 0x78800000,
1027 .le_base
= 0x78c00000,
1028 .apc_base
= 0x6a000000,
1029 .afx_base
= 0x6e000000,
1030 .aux1_base
= 0x71900000,
1031 .aux2_base
= 0x71910000,
1032 .nvram_machine_id
= 0x80,
1033 .machine_id
= ss5_id
,
1034 .iommu_version
= 0x05000000,
1035 .max_mem
= 0x10000000,
1036 .default_cpu_model
= "Fujitsu MB86904",
1040 .iommu_base
= 0xfe0000000ULL
,
1041 .tcx_base
= 0xe20000000ULL
,
1042 .slavio_base
= 0xff0000000ULL
,
1043 .ms_kb_base
= 0xff1000000ULL
,
1044 .serial_base
= 0xff1100000ULL
,
1045 .nvram_base
= 0xff1200000ULL
,
1046 .fd_base
= 0xff1700000ULL
,
1047 .counter_base
= 0xff1300000ULL
,
1048 .intctl_base
= 0xff1400000ULL
,
1049 .idreg_base
= 0xef0000000ULL
,
1050 .dma_base
= 0xef0400000ULL
,
1051 .esp_base
= 0xef0800000ULL
,
1052 .le_base
= 0xef0c00000ULL
,
1053 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1054 .aux1_base
= 0xff1800000ULL
,
1055 .aux2_base
= 0xff1a01000ULL
,
1056 .ecc_base
= 0xf00000000ULL
,
1057 .ecc_version
= 0x10000000, // version 0, implementation 1
1058 .nvram_machine_id
= 0x72,
1059 .machine_id
= ss10_id
,
1060 .iommu_version
= 0x03000000,
1061 .max_mem
= 0xf00000000ULL
,
1062 .default_cpu_model
= "TI SuperSparc II",
1066 .iommu_base
= 0xfe0000000ULL
,
1067 .tcx_base
= 0xe20000000ULL
,
1068 .slavio_base
= 0xff0000000ULL
,
1069 .ms_kb_base
= 0xff1000000ULL
,
1070 .serial_base
= 0xff1100000ULL
,
1071 .nvram_base
= 0xff1200000ULL
,
1072 .counter_base
= 0xff1300000ULL
,
1073 .intctl_base
= 0xff1400000ULL
,
1074 .dma_base
= 0xef0081000ULL
,
1075 .esp_base
= 0xef0080000ULL
,
1076 .le_base
= 0xef0060000ULL
,
1077 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1078 .aux1_base
= 0xff1800000ULL
,
1079 .aux2_base
= 0xff1a01000ULL
, // XXX should not exist
1080 .ecc_base
= 0xf00000000ULL
,
1081 .ecc_version
= 0x00000000, // version 0, implementation 0
1082 .nvram_machine_id
= 0x71,
1083 .machine_id
= ss600mp_id
,
1084 .iommu_version
= 0x01000000,
1085 .max_mem
= 0xf00000000ULL
,
1086 .default_cpu_model
= "TI SuperSparc II",
1090 .iommu_base
= 0xfe0000000ULL
,
1091 .tcx_base
= 0xe20000000ULL
,
1092 .slavio_base
= 0xff0000000ULL
,
1093 .ms_kb_base
= 0xff1000000ULL
,
1094 .serial_base
= 0xff1100000ULL
,
1095 .nvram_base
= 0xff1200000ULL
,
1096 .fd_base
= 0xff1700000ULL
,
1097 .counter_base
= 0xff1300000ULL
,
1098 .intctl_base
= 0xff1400000ULL
,
1099 .idreg_base
= 0xef0000000ULL
,
1100 .dma_base
= 0xef0400000ULL
,
1101 .esp_base
= 0xef0800000ULL
,
1102 .le_base
= 0xef0c00000ULL
,
1103 .bpp_base
= 0xef4800000ULL
,
1104 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1105 .aux1_base
= 0xff1800000ULL
,
1106 .aux2_base
= 0xff1a01000ULL
,
1107 .dbri_base
= 0xee0000000ULL
,
1108 .sx_base
= 0xf80000000ULL
,
1111 .reg_base
= 0x9c000000ULL
,
1112 .vram_base
= 0xfc000000ULL
1114 .reg_base
= 0x90000000ULL
,
1115 .vram_base
= 0xf0000000ULL
1117 .reg_base
= 0x94000000ULL
1119 .reg_base
= 0x98000000ULL
1122 .ecc_base
= 0xf00000000ULL
,
1123 .ecc_version
= 0x20000000, // version 0, implementation 2
1124 .nvram_machine_id
= 0x72,
1125 .machine_id
= ss20_id
,
1126 .iommu_version
= 0x13000000,
1127 .max_mem
= 0xf00000000ULL
,
1128 .default_cpu_model
= "TI SuperSparc II",
1132 .iommu_base
= 0x10000000,
1133 .tcx_base
= 0x50000000,
1134 .slavio_base
= 0x70000000,
1135 .ms_kb_base
= 0x71000000,
1136 .serial_base
= 0x71100000,
1137 .nvram_base
= 0x71200000,
1138 .fd_base
= 0x71400000,
1139 .counter_base
= 0x71d00000,
1140 .intctl_base
= 0x71e00000,
1141 .idreg_base
= 0x78000000,
1142 .dma_base
= 0x78400000,
1143 .esp_base
= 0x78800000,
1144 .le_base
= 0x78c00000,
1145 .apc_base
= 0x71300000, // pmc
1146 .aux1_base
= 0x71900000,
1147 .aux2_base
= 0x71910000,
1148 .nvram_machine_id
= 0x80,
1149 .machine_id
= vger_id
,
1150 .iommu_version
= 0x05000000,
1151 .max_mem
= 0x10000000,
1152 .default_cpu_model
= "Fujitsu MB86904",
1156 .iommu_base
= 0x10000000,
1157 .iommu_pad_base
= 0x10004000,
1158 .iommu_pad_len
= 0x0fffb000,
1159 .tcx_base
= 0x50000000,
1160 .slavio_base
= 0x70000000,
1161 .ms_kb_base
= 0x71000000,
1162 .serial_base
= 0x71100000,
1163 .nvram_base
= 0x71200000,
1164 .fd_base
= 0x71400000,
1165 .counter_base
= 0x71d00000,
1166 .intctl_base
= 0x71e00000,
1167 .idreg_base
= 0x78000000,
1168 .dma_base
= 0x78400000,
1169 .esp_base
= 0x78800000,
1170 .le_base
= 0x78c00000,
1171 .aux1_base
= 0x71900000,
1172 .aux2_base
= 0x71910000,
1173 .nvram_machine_id
= 0x80,
1174 .machine_id
= lx_id
,
1175 .iommu_version
= 0x04000000,
1176 .max_mem
= 0x10000000,
1177 .default_cpu_model
= "TI MicroSparc I",
1181 .iommu_base
= 0x10000000,
1182 .tcx_base
= 0x50000000,
1183 .cs_base
= 0x6c000000,
1184 .slavio_base
= 0x70000000,
1185 .ms_kb_base
= 0x71000000,
1186 .serial_base
= 0x71100000,
1187 .nvram_base
= 0x71200000,
1188 .fd_base
= 0x71400000,
1189 .counter_base
= 0x71d00000,
1190 .intctl_base
= 0x71e00000,
1191 .idreg_base
= 0x78000000,
1192 .dma_base
= 0x78400000,
1193 .esp_base
= 0x78800000,
1194 .le_base
= 0x78c00000,
1195 .apc_base
= 0x6a000000,
1196 .aux1_base
= 0x71900000,
1197 .aux2_base
= 0x71910000,
1198 .nvram_machine_id
= 0x80,
1199 .machine_id
= ss4_id
,
1200 .iommu_version
= 0x05000000,
1201 .max_mem
= 0x10000000,
1202 .default_cpu_model
= "Fujitsu MB86904",
1206 .iommu_base
= 0x10000000,
1207 .tcx_base
= 0x50000000,
1208 .slavio_base
= 0x70000000,
1209 .ms_kb_base
= 0x71000000,
1210 .serial_base
= 0x71100000,
1211 .nvram_base
= 0x71200000,
1212 .fd_base
= 0x71400000,
1213 .counter_base
= 0x71d00000,
1214 .intctl_base
= 0x71e00000,
1215 .idreg_base
= 0x78000000,
1216 .dma_base
= 0x78400000,
1217 .esp_base
= 0x78800000,
1218 .le_base
= 0x78c00000,
1219 .apc_base
= 0x6a000000,
1220 .aux1_base
= 0x71900000,
1221 .aux2_base
= 0x71910000,
1222 .nvram_machine_id
= 0x80,
1223 .machine_id
= scls_id
,
1224 .iommu_version
= 0x05000000,
1225 .max_mem
= 0x10000000,
1226 .default_cpu_model
= "TI MicroSparc I",
1230 .iommu_base
= 0x10000000,
1231 .tcx_base
= 0x50000000, // XXX
1232 .slavio_base
= 0x70000000,
1233 .ms_kb_base
= 0x71000000,
1234 .serial_base
= 0x71100000,
1235 .nvram_base
= 0x71200000,
1236 .fd_base
= 0x71400000,
1237 .counter_base
= 0x71d00000,
1238 .intctl_base
= 0x71e00000,
1239 .idreg_base
= 0x78000000,
1240 .dma_base
= 0x78400000,
1241 .esp_base
= 0x78800000,
1242 .le_base
= 0x78c00000,
1243 .apc_base
= 0x6a000000,
1244 .aux1_base
= 0x71900000,
1245 .aux2_base
= 0x71910000,
1246 .nvram_machine_id
= 0x80,
1247 .machine_id
= sbook_id
,
1248 .iommu_version
= 0x05000000,
1249 .max_mem
= 0x10000000,
1250 .default_cpu_model
= "TI MicroSparc I",
1254 /* SPARCstation 5 hardware initialisation */
1255 static void ss5_init(ram_addr_t RAM_size
,
1256 const char *boot_device
,
1257 const char *kernel_filename
, const char *kernel_cmdline
,
1258 const char *initrd_filename
, const char *cpu_model
)
1260 sun4m_hw_init(&sun4m_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1261 kernel_cmdline
, initrd_filename
, cpu_model
);
1264 /* SPARCstation 10 hardware initialisation */
1265 static void ss10_init(ram_addr_t RAM_size
,
1266 const char *boot_device
,
1267 const char *kernel_filename
, const char *kernel_cmdline
,
1268 const char *initrd_filename
, const char *cpu_model
)
1270 sun4m_hw_init(&sun4m_hwdefs
[1], RAM_size
, boot_device
, kernel_filename
,
1271 kernel_cmdline
, initrd_filename
, cpu_model
);
1274 /* SPARCserver 600MP hardware initialisation */
1275 static void ss600mp_init(ram_addr_t RAM_size
,
1276 const char *boot_device
,
1277 const char *kernel_filename
,
1278 const char *kernel_cmdline
,
1279 const char *initrd_filename
, const char *cpu_model
)
1281 sun4m_hw_init(&sun4m_hwdefs
[2], RAM_size
, boot_device
, kernel_filename
,
1282 kernel_cmdline
, initrd_filename
, cpu_model
);
1285 /* SPARCstation 20 hardware initialisation */
1286 static void ss20_init(ram_addr_t RAM_size
,
1287 const char *boot_device
,
1288 const char *kernel_filename
, const char *kernel_cmdline
,
1289 const char *initrd_filename
, const char *cpu_model
)
1291 sun4m_hw_init(&sun4m_hwdefs
[3], RAM_size
, boot_device
, kernel_filename
,
1292 kernel_cmdline
, initrd_filename
, cpu_model
);
1295 /* SPARCstation Voyager hardware initialisation */
1296 static void vger_init(ram_addr_t RAM_size
,
1297 const char *boot_device
,
1298 const char *kernel_filename
, const char *kernel_cmdline
,
1299 const char *initrd_filename
, const char *cpu_model
)
1301 sun4m_hw_init(&sun4m_hwdefs
[4], RAM_size
, boot_device
, kernel_filename
,
1302 kernel_cmdline
, initrd_filename
, cpu_model
);
1305 /* SPARCstation LX hardware initialisation */
1306 static void ss_lx_init(ram_addr_t RAM_size
,
1307 const char *boot_device
,
1308 const char *kernel_filename
, const char *kernel_cmdline
,
1309 const char *initrd_filename
, const char *cpu_model
)
1311 sun4m_hw_init(&sun4m_hwdefs
[5], RAM_size
, boot_device
, kernel_filename
,
1312 kernel_cmdline
, initrd_filename
, cpu_model
);
1315 /* SPARCstation 4 hardware initialisation */
1316 static void ss4_init(ram_addr_t RAM_size
,
1317 const char *boot_device
,
1318 const char *kernel_filename
, const char *kernel_cmdline
,
1319 const char *initrd_filename
, const char *cpu_model
)
1321 sun4m_hw_init(&sun4m_hwdefs
[6], RAM_size
, boot_device
, kernel_filename
,
1322 kernel_cmdline
, initrd_filename
, cpu_model
);
1325 /* SPARCClassic hardware initialisation */
1326 static void scls_init(ram_addr_t RAM_size
,
1327 const char *boot_device
,
1328 const char *kernel_filename
, const char *kernel_cmdline
,
1329 const char *initrd_filename
, const char *cpu_model
)
1331 sun4m_hw_init(&sun4m_hwdefs
[7], RAM_size
, boot_device
, kernel_filename
,
1332 kernel_cmdline
, initrd_filename
, cpu_model
);
1335 /* SPARCbook hardware initialisation */
1336 static void sbook_init(ram_addr_t RAM_size
,
1337 const char *boot_device
,
1338 const char *kernel_filename
, const char *kernel_cmdline
,
1339 const char *initrd_filename
, const char *cpu_model
)
1341 sun4m_hw_init(&sun4m_hwdefs
[8], RAM_size
, boot_device
, kernel_filename
,
1342 kernel_cmdline
, initrd_filename
, cpu_model
);
1345 static QEMUMachine ss5_machine
= {
1347 .desc
= "Sun4m platform, SPARCstation 5",
1353 static QEMUMachine ss10_machine
= {
1355 .desc
= "Sun4m platform, SPARCstation 10",
1361 static QEMUMachine ss600mp_machine
= {
1363 .desc
= "Sun4m platform, SPARCserver 600MP",
1364 .init
= ss600mp_init
,
1369 static QEMUMachine ss20_machine
= {
1371 .desc
= "Sun4m platform, SPARCstation 20",
1377 static QEMUMachine voyager_machine
= {
1379 .desc
= "Sun4m platform, SPARCstation Voyager",
1384 static QEMUMachine ss_lx_machine
= {
1386 .desc
= "Sun4m platform, SPARCstation LX",
1391 static QEMUMachine ss4_machine
= {
1393 .desc
= "Sun4m platform, SPARCstation 4",
1398 static QEMUMachine scls_machine
= {
1399 .name
= "SPARCClassic",
1400 .desc
= "Sun4m platform, SPARCClassic",
1405 static QEMUMachine sbook_machine
= {
1406 .name
= "SPARCbook",
1407 .desc
= "Sun4m platform, SPARCbook",
1412 static const struct sun4d_hwdef sun4d_hwdefs
[] = {
1422 .tcx_base
= 0x820000000ULL
,
1423 .slavio_base
= 0xf00000000ULL
,
1424 .ms_kb_base
= 0xf00240000ULL
,
1425 .serial_base
= 0xf00200000ULL
,
1426 .nvram_base
= 0xf00280000ULL
,
1427 .counter_base
= 0xf00300000ULL
,
1428 .espdma_base
= 0x800081000ULL
,
1429 .esp_base
= 0x800080000ULL
,
1430 .ledma_base
= 0x800040000ULL
,
1431 .le_base
= 0x800060000ULL
,
1432 .sbi_base
= 0xf02800000ULL
,
1433 .nvram_machine_id
= 0x80,
1434 .machine_id
= ss1000_id
,
1435 .iounit_version
= 0x03000000,
1436 .max_mem
= 0xf00000000ULL
,
1437 .default_cpu_model
= "TI SuperSparc II",
1448 .tcx_base
= 0x820000000ULL
,
1449 .slavio_base
= 0xf00000000ULL
,
1450 .ms_kb_base
= 0xf00240000ULL
,
1451 .serial_base
= 0xf00200000ULL
,
1452 .nvram_base
= 0xf00280000ULL
,
1453 .counter_base
= 0xf00300000ULL
,
1454 .espdma_base
= 0x800081000ULL
,
1455 .esp_base
= 0x800080000ULL
,
1456 .ledma_base
= 0x800040000ULL
,
1457 .le_base
= 0x800060000ULL
,
1458 .sbi_base
= 0xf02800000ULL
,
1459 .nvram_machine_id
= 0x80,
1460 .machine_id
= ss2000_id
,
1461 .iounit_version
= 0x03000000,
1462 .max_mem
= 0xf00000000ULL
,
1463 .default_cpu_model
= "TI SuperSparc II",
1467 static DeviceState
*sbi_init(target_phys_addr_t addr
, qemu_irq
**parent_irq
)
1473 dev
= qdev_create(NULL
, "sbi");
1474 qdev_init_nofail(dev
);
1476 s
= sysbus_from_qdev(dev
);
1478 for (i
= 0; i
< MAX_CPUS
; i
++) {
1479 sysbus_connect_irq(s
, i
, *parent_irq
[i
]);
1482 sysbus_mmio_map(s
, 0, addr
);
1487 static void sun4d_hw_init(const struct sun4d_hwdef
*hwdef
, ram_addr_t RAM_size
,
1488 const char *boot_device
,
1489 const char *kernel_filename
,
1490 const char *kernel_cmdline
,
1491 const char *initrd_filename
, const char *cpu_model
)
1494 void *iounits
[MAX_IOUNITS
], *espdma
, *ledma
, *nvram
;
1495 qemu_irq
*cpu_irqs
[MAX_CPUS
], sbi_irq
[32], sbi_cpu_irq
[MAX_CPUS
],
1496 espdma_irq
, ledma_irq
;
1498 unsigned long kernel_size
;
1504 cpu_model
= hwdef
->default_cpu_model
;
1506 for(i
= 0; i
< smp_cpus
; i
++) {
1507 cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
1510 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
1511 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
1513 /* set up devices */
1514 ram_init(0, RAM_size
, hwdef
->max_mem
);
1516 prom_init(hwdef
->slavio_base
, bios_name
);
1518 dev
= sbi_init(hwdef
->sbi_base
, cpu_irqs
);
1520 for (i
= 0; i
< 32; i
++) {
1521 sbi_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1523 for (i
= 0; i
< MAX_CPUS
; i
++) {
1524 sbi_cpu_irq
[i
] = qdev_get_gpio_in(dev
, 32 + i
);
1527 for (i
= 0; i
< MAX_IOUNITS
; i
++)
1528 if (hwdef
->iounit_bases
[i
] != (target_phys_addr_t
)-1)
1529 iounits
[i
] = iommu_init(hwdef
->iounit_bases
[i
],
1530 hwdef
->iounit_version
,
1533 espdma
= sparc32_dma_init(hwdef
->espdma_base
, sbi_irq
[3],
1534 iounits
[0], &espdma_irq
);
1536 ledma
= sparc32_dma_init(hwdef
->ledma_base
, sbi_irq
[4],
1537 iounits
[0], &ledma_irq
);
1539 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
1540 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
1543 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
1546 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
1548 nvram
= m48t59_init(sbi_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 8);
1550 slavio_timer_init_all(hwdef
->counter_base
, sbi_irq
[10], sbi_cpu_irq
, smp_cpus
);
1552 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, sbi_irq
[12],
1553 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
1554 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1555 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1556 escc_init(hwdef
->serial_base
, sbi_irq
[12], sbi_irq
[12],
1557 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
1559 if (drive_get_max_bus(IF_SCSI
) > 0) {
1560 fprintf(stderr
, "qemu: too many SCSI bus\n");
1564 esp_reset
= qdev_get_gpio_in(espdma
, 0);
1565 esp_init(hwdef
->esp_base
, 2,
1566 espdma_memory_read
, espdma_memory_write
,
1567 espdma
, espdma_irq
, &esp_reset
);
1569 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
1572 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
1573 boot_device
, RAM_size
, kernel_size
, graphic_width
,
1574 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
1577 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
1578 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1579 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1580 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1581 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1582 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1583 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1584 if (kernel_cmdline
) {
1585 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1586 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1587 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
1588 (uint8_t*)strdup(kernel_cmdline
),
1589 strlen(kernel_cmdline
) + 1);
1591 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1593 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1594 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1595 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1596 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1599 /* SPARCserver 1000 hardware initialisation */
1600 static void ss1000_init(ram_addr_t RAM_size
,
1601 const char *boot_device
,
1602 const char *kernel_filename
, const char *kernel_cmdline
,
1603 const char *initrd_filename
, const char *cpu_model
)
1605 sun4d_hw_init(&sun4d_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1606 kernel_cmdline
, initrd_filename
, cpu_model
);
1609 /* SPARCcenter 2000 hardware initialisation */
1610 static void ss2000_init(ram_addr_t RAM_size
,
1611 const char *boot_device
,
1612 const char *kernel_filename
, const char *kernel_cmdline
,
1613 const char *initrd_filename
, const char *cpu_model
)
1615 sun4d_hw_init(&sun4d_hwdefs
[1], RAM_size
, boot_device
, kernel_filename
,
1616 kernel_cmdline
, initrd_filename
, cpu_model
);
1619 static QEMUMachine ss1000_machine
= {
1621 .desc
= "Sun4d platform, SPARCserver 1000",
1622 .init
= ss1000_init
,
1627 static QEMUMachine ss2000_machine
= {
1629 .desc
= "Sun4d platform, SPARCcenter 2000",
1630 .init
= ss2000_init
,
1635 static const struct sun4c_hwdef sun4c_hwdefs
[] = {
1638 .iommu_base
= 0xf8000000,
1639 .tcx_base
= 0xfe000000,
1640 .slavio_base
= 0xf6000000,
1641 .intctl_base
= 0xf5000000,
1642 .counter_base
= 0xf3000000,
1643 .ms_kb_base
= 0xf0000000,
1644 .serial_base
= 0xf1000000,
1645 .nvram_base
= 0xf2000000,
1646 .fd_base
= 0xf7200000,
1647 .dma_base
= 0xf8400000,
1648 .esp_base
= 0xf8800000,
1649 .le_base
= 0xf8c00000,
1650 .aux1_base
= 0xf7400003,
1651 .nvram_machine_id
= 0x55,
1652 .machine_id
= ss2_id
,
1653 .max_mem
= 0x10000000,
1654 .default_cpu_model
= "Cypress CY7C601",
1658 static DeviceState
*sun4c_intctl_init(target_phys_addr_t addr
,
1659 qemu_irq
*parent_irq
)
1665 dev
= qdev_create(NULL
, "sun4c_intctl");
1666 qdev_init_nofail(dev
);
1668 s
= sysbus_from_qdev(dev
);
1670 for (i
= 0; i
< MAX_PILS
; i
++) {
1671 sysbus_connect_irq(s
, i
, parent_irq
[i
]);
1673 sysbus_mmio_map(s
, 0, addr
);
1678 static void sun4c_hw_init(const struct sun4c_hwdef
*hwdef
, ram_addr_t RAM_size
,
1679 const char *boot_device
,
1680 const char *kernel_filename
,
1681 const char *kernel_cmdline
,
1682 const char *initrd_filename
, const char *cpu_model
)
1684 void *iommu
, *espdma
, *ledma
, *nvram
;
1685 qemu_irq
*cpu_irqs
, slavio_irq
[8], espdma_irq
, ledma_irq
;
1688 unsigned long kernel_size
;
1689 DriveInfo
*fd
[MAX_FD
];
1696 cpu_model
= hwdef
->default_cpu_model
;
1698 cpu_devinit(cpu_model
, 0, hwdef
->slavio_base
, &cpu_irqs
);
1700 /* set up devices */
1701 ram_init(0, RAM_size
, hwdef
->max_mem
);
1703 prom_init(hwdef
->slavio_base
, bios_name
);
1705 dev
= sun4c_intctl_init(hwdef
->intctl_base
, cpu_irqs
);
1707 for (i
= 0; i
< 8; i
++) {
1708 slavio_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1711 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
1714 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[2],
1715 iommu
, &espdma_irq
);
1717 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
1718 slavio_irq
[3], iommu
, &ledma_irq
);
1720 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
1721 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
1724 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
1727 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
1729 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x800, 2);
1731 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[1],
1732 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
1733 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1734 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1735 escc_init(hwdef
->serial_base
, slavio_irq
[1],
1736 slavio_irq
[1], serial_hds
[0], serial_hds
[1],
1739 slavio_misc_init(0, hwdef
->aux1_base
, 0, slavio_irq
[1], fdc_tc
);
1741 if (hwdef
->fd_base
!= (target_phys_addr_t
)-1) {
1742 /* there is zero or one floppy drive */
1743 memset(fd
, 0, sizeof(fd
));
1744 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
1745 sun4m_fdctrl_init(slavio_irq
[1], hwdef
->fd_base
, fd
,
1749 if (drive_get_max_bus(IF_SCSI
) > 0) {
1750 fprintf(stderr
, "qemu: too many SCSI bus\n");
1754 esp_reset
= qdev_get_gpio_in(espdma
, 0);
1755 esp_init(hwdef
->esp_base
, 2,
1756 espdma_memory_read
, espdma_memory_write
,
1757 espdma
, espdma_irq
, &esp_reset
);
1759 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
1762 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
1763 boot_device
, RAM_size
, kernel_size
, graphic_width
,
1764 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
1767 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
1768 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1769 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1770 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1771 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1772 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1773 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1774 if (kernel_cmdline
) {
1775 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1776 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1777 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
1778 (uint8_t*)strdup(kernel_cmdline
),
1779 strlen(kernel_cmdline
) + 1);
1781 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1783 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1784 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1785 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1786 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1789 /* SPARCstation 2 hardware initialisation */
1790 static void ss2_init(ram_addr_t RAM_size
,
1791 const char *boot_device
,
1792 const char *kernel_filename
, const char *kernel_cmdline
,
1793 const char *initrd_filename
, const char *cpu_model
)
1795 sun4c_hw_init(&sun4c_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1796 kernel_cmdline
, initrd_filename
, cpu_model
);
1799 static QEMUMachine ss2_machine
= {
1801 .desc
= "Sun4c platform, SPARCstation 2",
1806 static void ss2_machine_init(void)
1808 qemu_register_machine(&ss5_machine
);
1809 qemu_register_machine(&ss10_machine
);
1810 qemu_register_machine(&ss600mp_machine
);
1811 qemu_register_machine(&ss20_machine
);
1812 qemu_register_machine(&voyager_machine
);
1813 qemu_register_machine(&ss_lx_machine
);
1814 qemu_register_machine(&ss4_machine
);
1815 qemu_register_machine(&scls_machine
);
1816 qemu_register_machine(&sbook_machine
);
1817 qemu_register_machine(&ss1000_machine
);
1818 qemu_register_machine(&ss2000_machine
);
1819 qemu_register_machine(&ss2_machine
);
1822 machine_init(ss2_machine_init
);