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Add common keys to firmware configuration
[mirror_qemu.git] / hw / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38
39 //#define DEBUG_IRQ
40
41 /*
42 * Sun4m architecture was used in the following machines:
43 *
44 * SPARCserver 6xxMP/xx
45 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
46 * SPARCclassic X (4/10)
47 * SPARCstation LX/ZX (4/30)
48 * SPARCstation Voyager
49 * SPARCstation 10/xx, SPARCserver 10/xx
50 * SPARCstation 5, SPARCserver 5
51 * SPARCstation 20/xx, SPARCserver 20
52 * SPARCstation 4
53 *
54 * Sun4d architecture was used in the following machines:
55 *
56 * SPARCcenter 2000
57 * SPARCserver 1000
58 *
59 * Sun4c architecture was used in the following machines:
60 * SPARCstation 1/1+, SPARCserver 1/1+
61 * SPARCstation SLC
62 * SPARCstation IPC
63 * SPARCstation ELC
64 * SPARCstation IPX
65 *
66 * See for example: http://www.sunhelp.org/faq/sunref1.html
67 */
68
69 #ifdef DEBUG_IRQ
70 #define DPRINTF(fmt, args...) \
71 do { printf("CPUIRQ: " fmt , ##args); } while (0)
72 #else
73 #define DPRINTF(fmt, args...)
74 #endif
75
76 #define KERNEL_LOAD_ADDR 0x00004000
77 #define CMDLINE_ADDR 0x007ff000
78 #define INITRD_LOAD_ADDR 0x00800000
79 #define PROM_SIZE_MAX (512 * 1024)
80 #define PROM_VADDR 0xffd00000
81 #define PROM_FILENAME "openbios-sparc32"
82 #define CFG_ADDR 0xd00000510ULL
83
84 // Control plane, 8-bit and 24-bit planes
85 #define TCX_SIZE (9 * 1024 * 1024)
86
87 #define MAX_CPUS 16
88 #define MAX_PILS 16
89
90 struct hwdef {
91 target_phys_addr_t iommu_base, slavio_base;
92 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
93 target_phys_addr_t serial_base, fd_base;
94 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
95 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
96 target_phys_addr_t ecc_base;
97 uint32_t ecc_version;
98 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
99 long vram_size, nvram_size;
100 // IRQ numbers are not PIL ones, but master interrupt controller
101 // register bit numbers
102 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
103 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104 uint8_t nvram_machine_id;
105 uint16_t machine_id;
106 uint32_t iommu_version;
107 uint32_t intbit_to_level[32];
108 uint64_t max_mem;
109 const char * const default_cpu_model;
110 };
111
112 #define MAX_IOUNITS 5
113
114 struct sun4d_hwdef {
115 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117 target_phys_addr_t serial_base;
118 target_phys_addr_t espdma_base, esp_base;
119 target_phys_addr_t ledma_base, le_base;
120 target_phys_addr_t tcx_base;
121 target_phys_addr_t sbi_base;
122 unsigned long vram_size, nvram_size;
123 // IRQ numbers are not PIL ones, but SBI register bit numbers
124 int esp_irq, le_irq, clock_irq, clock1_irq;
125 int ser_irq, ms_kb_irq, me_irq;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 int DMA_get_channel_mode (int nchan)
134 {
135 return 0;
136 }
137 int DMA_read_memory (int nchan, void *buf, int pos, int size)
138 {
139 return 0;
140 }
141 int DMA_write_memory (int nchan, void *buf, int pos, int size)
142 {
143 return 0;
144 }
145 void DMA_hold_DREQ (int nchan) {}
146 void DMA_release_DREQ (int nchan) {}
147 void DMA_schedule(int nchan) {}
148 void DMA_run (void) {}
149 void DMA_init (int high_page_enable) {}
150 void DMA_register_channel (int nchan,
151 DMA_transfer_handler transfer_handler,
152 void *opaque)
153 {
154 }
155
156 static int nvram_boot_set(void *opaque, const char *boot_device)
157 {
158 unsigned int i;
159 uint8_t image[sizeof(ohwcfg_v3_t)];
160 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
161 m48t59_t *nvram = (m48t59_t *)opaque;
162
163 for (i = 0; i < sizeof(image); i++)
164 image[i] = m48t59_read(nvram, i) & 0xff;
165
166 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
167 boot_device);
168 header->nboot_devices = strlen(boot_device) & 0xff;
169 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
170
171 for (i = 0; i < sizeof(image); i++)
172 m48t59_write(nvram, i, image[i]);
173
174 return 0;
175 }
176
177 extern int nographic;
178
179 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
180 const char *boot_devices, ram_addr_t RAM_size,
181 uint32_t kernel_size,
182 int width, int height, int depth,
183 int nvram_machine_id, const char *arch)
184 {
185 unsigned int i;
186 uint32_t start, end;
187 uint8_t image[0x1ff0];
188 ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
189 struct sparc_arch_cfg *sparc_header;
190 struct OpenBIOS_nvpart_v1 *part_header;
191
192 memset(image, '\0', sizeof(image));
193
194 // Try to match PPC NVRAM
195 pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
196 "QEMU_BIOS");
197 header->struct_version = cpu_to_be32(3); /* structure v3 */
198
199 header->nvram_size = cpu_to_be16(0x2000);
200 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
201 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
202 pstrcpy((char *)header->arch, sizeof(header->arch), arch);
203 header->nb_cpus = smp_cpus & 0xff;
204 header->RAM0_base = 0;
205 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
206 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
207 boot_devices);
208 header->nboot_devices = strlen(boot_devices) & 0xff;
209 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
210 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
211 if (cmdline) {
212 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
213 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
214 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
215 }
216 // XXX add initrd_image, initrd_size
217 header->width = cpu_to_be16(width);
218 header->height = cpu_to_be16(height);
219 header->depth = cpu_to_be16(depth);
220 if (nographic)
221 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
222
223 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
224
225 // Architecture specific header
226 start = sizeof(ohwcfg_v3_t);
227 sparc_header = (struct sparc_arch_cfg *)&image[start];
228 sparc_header->valid = 0;
229 start += sizeof(struct sparc_arch_cfg);
230
231 // OpenBIOS nvram variables
232 // Variable partition
233 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
234 part_header->signature = OPENBIOS_PART_SYSTEM;
235 pstrcpy(part_header->name, sizeof(part_header->name), "system");
236
237 end = start + sizeof(struct OpenBIOS_nvpart_v1);
238 for (i = 0; i < nb_prom_envs; i++)
239 end = OpenBIOS_set_var(image, end, prom_envs[i]);
240
241 // End marker
242 image[end++] = '\0';
243
244 end = start + ((end - start + 15) & ~15);
245 OpenBIOS_finish_partition(part_header, end - start);
246
247 // free partition
248 start = end;
249 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
250 part_header->signature = OPENBIOS_PART_FREE;
251 pstrcpy(part_header->name, sizeof(part_header->name), "free");
252
253 end = 0x1fd0;
254 OpenBIOS_finish_partition(part_header, end - start);
255
256 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
257 nvram_machine_id);
258
259 for (i = 0; i < sizeof(image); i++)
260 m48t59_write(nvram, i, image[i]);
261
262 qemu_register_boot_set(nvram_boot_set, nvram);
263 }
264
265 static void *slavio_intctl;
266
267 void pic_info(void)
268 {
269 if (slavio_intctl)
270 slavio_pic_info(slavio_intctl);
271 }
272
273 void irq_info(void)
274 {
275 if (slavio_intctl)
276 slavio_irq_info(slavio_intctl);
277 }
278
279 void cpu_check_irqs(CPUState *env)
280 {
281 if (env->pil_in && (env->interrupt_index == 0 ||
282 (env->interrupt_index & ~15) == TT_EXTINT)) {
283 unsigned int i;
284
285 for (i = 15; i > 0; i--) {
286 if (env->pil_in & (1 << i)) {
287 int old_interrupt = env->interrupt_index;
288
289 env->interrupt_index = TT_EXTINT | i;
290 if (old_interrupt != env->interrupt_index) {
291 DPRINTF("Set CPU IRQ %d\n", i);
292 cpu_interrupt(env, CPU_INTERRUPT_HARD);
293 }
294 break;
295 }
296 }
297 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
298 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
299 env->interrupt_index = 0;
300 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
301 }
302 }
303
304 static void cpu_set_irq(void *opaque, int irq, int level)
305 {
306 CPUState *env = opaque;
307
308 if (level) {
309 DPRINTF("Raise CPU IRQ %d\n", irq);
310 env->halted = 0;
311 env->pil_in |= 1 << irq;
312 cpu_check_irqs(env);
313 } else {
314 DPRINTF("Lower CPU IRQ %d\n", irq);
315 env->pil_in &= ~(1 << irq);
316 cpu_check_irqs(env);
317 }
318 }
319
320 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
321 {
322 }
323
324 static void *slavio_misc;
325
326 void qemu_system_powerdown(void)
327 {
328 slavio_set_power_fail(slavio_misc, 1);
329 }
330
331 static void main_cpu_reset(void *opaque)
332 {
333 CPUState *env = opaque;
334
335 cpu_reset(env);
336 env->halted = 0;
337 }
338
339 static void secondary_cpu_reset(void *opaque)
340 {
341 CPUState *env = opaque;
342
343 cpu_reset(env);
344 env->halted = 1;
345 }
346
347 static unsigned long sun4m_load_kernel(const char *kernel_filename,
348 const char *initrd_filename,
349 ram_addr_t RAM_size)
350 {
351 int linux_boot;
352 unsigned int i;
353 long initrd_size, kernel_size;
354
355 linux_boot = (kernel_filename != NULL);
356
357 kernel_size = 0;
358 if (linux_boot) {
359 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
360 NULL);
361 if (kernel_size < 0)
362 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
363 RAM_size - KERNEL_LOAD_ADDR);
364 if (kernel_size < 0)
365 kernel_size = load_image_targphys(kernel_filename,
366 KERNEL_LOAD_ADDR,
367 RAM_size - KERNEL_LOAD_ADDR);
368 if (kernel_size < 0) {
369 fprintf(stderr, "qemu: could not load kernel '%s'\n",
370 kernel_filename);
371 exit(1);
372 }
373
374 /* load initrd */
375 initrd_size = 0;
376 if (initrd_filename) {
377 initrd_size = load_image_targphys(initrd_filename,
378 INITRD_LOAD_ADDR,
379 RAM_size - INITRD_LOAD_ADDR);
380 if (initrd_size < 0) {
381 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
382 initrd_filename);
383 exit(1);
384 }
385 }
386 if (initrd_size > 0) {
387 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
388 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
389 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
390 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
391 break;
392 }
393 }
394 }
395 }
396 return kernel_size;
397 }
398
399 static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
400 const char *boot_device,
401 DisplayState *ds, const char *kernel_filename,
402 const char *kernel_cmdline,
403 const char *initrd_filename, const char *cpu_model)
404
405 {
406 CPUState *env, *envs[MAX_CPUS];
407 unsigned int i;
408 void *iommu, *espdma, *ledma, *main_esp, *nvram;
409 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
410 *espdma_irq, *ledma_irq;
411 qemu_irq *esp_reset, *le_reset;
412 qemu_irq *fdc_tc;
413 unsigned long prom_offset, kernel_size;
414 int ret;
415 char buf[1024];
416 BlockDriverState *fd[MAX_FD];
417 int drive_index;
418 void *fw_cfg;
419
420 /* init CPUs */
421 if (!cpu_model)
422 cpu_model = hwdef->default_cpu_model;
423
424 for(i = 0; i < smp_cpus; i++) {
425 env = cpu_init(cpu_model);
426 if (!env) {
427 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
428 exit(1);
429 }
430 cpu_sparc_set_id(env, i);
431 envs[i] = env;
432 if (i == 0) {
433 qemu_register_reset(main_cpu_reset, env);
434 } else {
435 qemu_register_reset(secondary_cpu_reset, env);
436 env->halted = 1;
437 }
438 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
439 env->prom_addr = hwdef->slavio_base;
440 }
441
442 for (i = smp_cpus; i < MAX_CPUS; i++)
443 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
444
445
446 /* allocate RAM */
447 if ((uint64_t)RAM_size > hwdef->max_mem) {
448 fprintf(stderr,
449 "qemu: Too much memory for this machine: %d, maximum %d\n",
450 (unsigned int)(RAM_size / (1024 * 1024)),
451 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
452 exit(1);
453 }
454 cpu_register_physical_memory(0, RAM_size, 0);
455
456 /* load boot prom */
457 prom_offset = RAM_size + hwdef->vram_size;
458 cpu_register_physical_memory(hwdef->slavio_base,
459 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
460 TARGET_PAGE_MASK,
461 prom_offset | IO_MEM_ROM);
462
463 if (bios_name == NULL)
464 bios_name = PROM_FILENAME;
465 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
466 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
467 if (ret < 0 || ret > PROM_SIZE_MAX)
468 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
469 if (ret < 0 || ret > PROM_SIZE_MAX) {
470 fprintf(stderr, "qemu: could not load prom '%s'\n",
471 buf);
472 exit(1);
473 }
474 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
475
476 /* set up devices */
477 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
478 hwdef->intctl_base + 0x10000ULL,
479 &hwdef->intbit_to_level[0],
480 &slavio_irq, &slavio_cpu_irq,
481 cpu_irqs,
482 hwdef->clock_irq);
483
484 if (hwdef->idreg_base != (target_phys_addr_t)-1) {
485 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
486
487 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
488 prom_offset | IO_MEM_ROM);
489 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
490 sizeof(idreg_data));
491 }
492
493 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
494 slavio_irq[hwdef->me_irq]);
495
496 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
497 iommu, &espdma_irq, &esp_reset);
498
499 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
500 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
501 &le_reset);
502
503 if (graphic_depth != 8 && graphic_depth != 24) {
504 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
505 exit (1);
506 }
507 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
508 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
509
510 if (nd_table[0].model == NULL
511 || strcmp(nd_table[0].model, "lance") == 0) {
512 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
513 } else if (strcmp(nd_table[0].model, "?") == 0) {
514 fprintf(stderr, "qemu: Supported NICs: lance\n");
515 exit (1);
516 } else {
517 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
518 exit (1);
519 }
520
521 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
522 hwdef->nvram_size, 8);
523
524 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
525 slavio_cpu_irq, smp_cpus);
526
527 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
528 nographic);
529 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
530 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
531 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
532 serial_hds[1], serial_hds[0]);
533
534 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
535 hwdef->aux1_base, hwdef->aux2_base,
536 slavio_irq[hwdef->me_irq], envs[0],
537 &fdc_tc);
538
539 if (hwdef->fd_base != (target_phys_addr_t)-1) {
540 /* there is zero or one floppy drive */
541 memset(fd, 0, sizeof(fd));
542 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
543 if (drive_index != -1)
544 fd[0] = drives_table[drive_index].bdrv;
545
546 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
547 fdc_tc);
548 }
549
550 if (drive_get_max_bus(IF_SCSI) > 0) {
551 fprintf(stderr, "qemu: too many SCSI bus\n");
552 exit(1);
553 }
554
555 main_esp = esp_init(hwdef->esp_base, 2,
556 espdma_memory_read, espdma_memory_write,
557 espdma, *espdma_irq, esp_reset);
558
559 for (i = 0; i < ESP_MAX_DEVS; i++) {
560 drive_index = drive_get_index(IF_SCSI, 0, i);
561 if (drive_index == -1)
562 continue;
563 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
564 }
565
566 if (hwdef->cs_base != (target_phys_addr_t)-1)
567 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
568
569 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
570 RAM_size);
571
572 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
573 boot_device, RAM_size, kernel_size, graphic_width,
574 graphic_height, graphic_depth, hwdef->nvram_machine_id,
575 "Sun4m");
576
577 if (hwdef->ecc_base != (target_phys_addr_t)-1)
578 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
579 hwdef->ecc_version);
580
581 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
582 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
583 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
584 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
585 }
586
587 static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
588 const char *boot_device,
589 DisplayState *ds, const char *kernel_filename,
590 const char *kernel_cmdline,
591 const char *initrd_filename, const char *cpu_model)
592 {
593 CPUState *env;
594 unsigned int i;
595 void *iommu, *espdma, *ledma, *main_esp, *nvram;
596 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
597 qemu_irq *esp_reset, *le_reset;
598 qemu_irq *fdc_tc;
599 unsigned long prom_offset, kernel_size;
600 int ret;
601 char buf[1024];
602 BlockDriverState *fd[MAX_FD];
603 int drive_index;
604 void *fw_cfg;
605
606 /* init CPU */
607 if (!cpu_model)
608 cpu_model = hwdef->default_cpu_model;
609
610 env = cpu_init(cpu_model);
611 if (!env) {
612 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
613 exit(1);
614 }
615
616 cpu_sparc_set_id(env, 0);
617
618 qemu_register_reset(main_cpu_reset, env);
619 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
620 env->prom_addr = hwdef->slavio_base;
621
622 /* allocate RAM */
623 if ((uint64_t)RAM_size > hwdef->max_mem) {
624 fprintf(stderr,
625 "qemu: Too much memory for this machine: %d, maximum %d\n",
626 (unsigned int)(RAM_size / (1024 * 1024)),
627 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
628 exit(1);
629 }
630 cpu_register_physical_memory(0, RAM_size, 0);
631
632 /* load boot prom */
633 prom_offset = RAM_size + hwdef->vram_size;
634 cpu_register_physical_memory(hwdef->slavio_base,
635 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
636 TARGET_PAGE_MASK,
637 prom_offset | IO_MEM_ROM);
638
639 if (bios_name == NULL)
640 bios_name = PROM_FILENAME;
641 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
642 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
643 if (ret < 0 || ret > PROM_SIZE_MAX)
644 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
645 if (ret < 0 || ret > PROM_SIZE_MAX) {
646 fprintf(stderr, "qemu: could not load prom '%s'\n",
647 buf);
648 exit(1);
649 }
650 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
651
652 /* set up devices */
653 slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
654 &slavio_irq, cpu_irqs);
655
656 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
657 slavio_irq[hwdef->me_irq]);
658
659 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
660 iommu, &espdma_irq, &esp_reset);
661
662 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
663 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
664 &le_reset);
665
666 if (graphic_depth != 8 && graphic_depth != 24) {
667 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
668 exit (1);
669 }
670 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
671 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
672
673 if (nd_table[0].model == NULL
674 || strcmp(nd_table[0].model, "lance") == 0) {
675 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
676 } else if (strcmp(nd_table[0].model, "?") == 0) {
677 fprintf(stderr, "qemu: Supported NICs: lance\n");
678 exit (1);
679 } else {
680 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
681 exit (1);
682 }
683
684 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
685 hwdef->nvram_size, 2);
686
687 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
688 nographic);
689 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
690 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
691 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
692 serial_hds[1], serial_hds[0]);
693
694 slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
695 hwdef->aux1_base, hwdef->aux2_base,
696 slavio_irq[hwdef->me_irq], env, &fdc_tc);
697
698 if (hwdef->fd_base != (target_phys_addr_t)-1) {
699 /* there is zero or one floppy drive */
700 fd[1] = fd[0] = NULL;
701 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
702 if (drive_index != -1)
703 fd[0] = drives_table[drive_index].bdrv;
704
705 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
706 fdc_tc);
707 }
708
709 if (drive_get_max_bus(IF_SCSI) > 0) {
710 fprintf(stderr, "qemu: too many SCSI bus\n");
711 exit(1);
712 }
713
714 main_esp = esp_init(hwdef->esp_base, 2,
715 espdma_memory_read, espdma_memory_write,
716 espdma, *espdma_irq, esp_reset);
717
718 for (i = 0; i < ESP_MAX_DEVS; i++) {
719 drive_index = drive_get_index(IF_SCSI, 0, i);
720 if (drive_index == -1)
721 continue;
722 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
723 }
724
725 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
726 RAM_size);
727
728 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
729 boot_device, RAM_size, kernel_size, graphic_width,
730 graphic_height, graphic_depth, hwdef->nvram_machine_id,
731 "Sun4c");
732
733 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
734 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
735 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
736 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
737 }
738
739 enum {
740 ss2_id = 0,
741 ss5_id = 32,
742 vger_id,
743 lx_id,
744 ss4_id,
745 scls_id,
746 sbook_id,
747 ss10_id = 64,
748 ss20_id,
749 ss600mp_id,
750 ss1000_id = 96,
751 ss2000_id,
752 };
753
754 static const struct hwdef hwdefs[] = {
755 /* SS-5 */
756 {
757 .iommu_base = 0x10000000,
758 .tcx_base = 0x50000000,
759 .cs_base = 0x6c000000,
760 .slavio_base = 0x70000000,
761 .ms_kb_base = 0x71000000,
762 .serial_base = 0x71100000,
763 .nvram_base = 0x71200000,
764 .fd_base = 0x71400000,
765 .counter_base = 0x71d00000,
766 .intctl_base = 0x71e00000,
767 .idreg_base = 0x78000000,
768 .dma_base = 0x78400000,
769 .esp_base = 0x78800000,
770 .le_base = 0x78c00000,
771 .apc_base = 0x6a000000,
772 .aux1_base = 0x71900000,
773 .aux2_base = 0x71910000,
774 .ecc_base = -1,
775 .sun4c_intctl_base = -1,
776 .sun4c_counter_base = -1,
777 .vram_size = 0x00100000,
778 .nvram_size = 0x2000,
779 .esp_irq = 18,
780 .le_irq = 16,
781 .clock_irq = 7,
782 .clock1_irq = 19,
783 .ms_kb_irq = 14,
784 .ser_irq = 15,
785 .fd_irq = 22,
786 .me_irq = 30,
787 .cs_irq = 5,
788 .nvram_machine_id = 0x80,
789 .machine_id = ss5_id,
790 .iommu_version = 0x05000000,
791 .intbit_to_level = {
792 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
793 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
794 },
795 .max_mem = 0x10000000,
796 .default_cpu_model = "Fujitsu MB86904",
797 },
798 /* SS-10 */
799 {
800 .iommu_base = 0xfe0000000ULL,
801 .tcx_base = 0xe20000000ULL,
802 .cs_base = -1,
803 .slavio_base = 0xff0000000ULL,
804 .ms_kb_base = 0xff1000000ULL,
805 .serial_base = 0xff1100000ULL,
806 .nvram_base = 0xff1200000ULL,
807 .fd_base = 0xff1700000ULL,
808 .counter_base = 0xff1300000ULL,
809 .intctl_base = 0xff1400000ULL,
810 .idreg_base = 0xef0000000ULL,
811 .dma_base = 0xef0400000ULL,
812 .esp_base = 0xef0800000ULL,
813 .le_base = 0xef0c00000ULL,
814 .apc_base = 0xefa000000ULL, // XXX should not exist
815 .aux1_base = 0xff1800000ULL,
816 .aux2_base = 0xff1a01000ULL,
817 .ecc_base = 0xf00000000ULL,
818 .ecc_version = 0x10000000, // version 0, implementation 1
819 .sun4c_intctl_base = -1,
820 .sun4c_counter_base = -1,
821 .vram_size = 0x00100000,
822 .nvram_size = 0x2000,
823 .esp_irq = 18,
824 .le_irq = 16,
825 .clock_irq = 7,
826 .clock1_irq = 19,
827 .ms_kb_irq = 14,
828 .ser_irq = 15,
829 .fd_irq = 22,
830 .me_irq = 30,
831 .cs_irq = -1,
832 .ecc_irq = 28,
833 .nvram_machine_id = 0x72,
834 .machine_id = ss10_id,
835 .iommu_version = 0x03000000,
836 .intbit_to_level = {
837 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
838 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
839 },
840 .max_mem = 0xf00000000ULL,
841 .default_cpu_model = "TI SuperSparc II",
842 },
843 /* SS-600MP */
844 {
845 .iommu_base = 0xfe0000000ULL,
846 .tcx_base = 0xe20000000ULL,
847 .cs_base = -1,
848 .slavio_base = 0xff0000000ULL,
849 .ms_kb_base = 0xff1000000ULL,
850 .serial_base = 0xff1100000ULL,
851 .nvram_base = 0xff1200000ULL,
852 .fd_base = -1,
853 .counter_base = 0xff1300000ULL,
854 .intctl_base = 0xff1400000ULL,
855 .idreg_base = -1,
856 .dma_base = 0xef0081000ULL,
857 .esp_base = 0xef0080000ULL,
858 .le_base = 0xef0060000ULL,
859 .apc_base = 0xefa000000ULL, // XXX should not exist
860 .aux1_base = 0xff1800000ULL,
861 .aux2_base = 0xff1a01000ULL, // XXX should not exist
862 .ecc_base = 0xf00000000ULL,
863 .ecc_version = 0x00000000, // version 0, implementation 0
864 .sun4c_intctl_base = -1,
865 .sun4c_counter_base = -1,
866 .vram_size = 0x00100000,
867 .nvram_size = 0x2000,
868 .esp_irq = 18,
869 .le_irq = 16,
870 .clock_irq = 7,
871 .clock1_irq = 19,
872 .ms_kb_irq = 14,
873 .ser_irq = 15,
874 .fd_irq = 22,
875 .me_irq = 30,
876 .cs_irq = -1,
877 .ecc_irq = 28,
878 .nvram_machine_id = 0x71,
879 .machine_id = ss600mp_id,
880 .iommu_version = 0x01000000,
881 .intbit_to_level = {
882 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
883 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
884 },
885 .max_mem = 0xf00000000ULL,
886 .default_cpu_model = "TI SuperSparc II",
887 },
888 /* SS-20 */
889 {
890 .iommu_base = 0xfe0000000ULL,
891 .tcx_base = 0xe20000000ULL,
892 .cs_base = -1,
893 .slavio_base = 0xff0000000ULL,
894 .ms_kb_base = 0xff1000000ULL,
895 .serial_base = 0xff1100000ULL,
896 .nvram_base = 0xff1200000ULL,
897 .fd_base = 0xff1700000ULL,
898 .counter_base = 0xff1300000ULL,
899 .intctl_base = 0xff1400000ULL,
900 .idreg_base = 0xef0000000ULL,
901 .dma_base = 0xef0400000ULL,
902 .esp_base = 0xef0800000ULL,
903 .le_base = 0xef0c00000ULL,
904 .apc_base = 0xefa000000ULL, // XXX should not exist
905 .aux1_base = 0xff1800000ULL,
906 .aux2_base = 0xff1a01000ULL,
907 .ecc_base = 0xf00000000ULL,
908 .ecc_version = 0x20000000, // version 0, implementation 2
909 .sun4c_intctl_base = -1,
910 .sun4c_counter_base = -1,
911 .vram_size = 0x00100000,
912 .nvram_size = 0x2000,
913 .esp_irq = 18,
914 .le_irq = 16,
915 .clock_irq = 7,
916 .clock1_irq = 19,
917 .ms_kb_irq = 14,
918 .ser_irq = 15,
919 .fd_irq = 22,
920 .me_irq = 30,
921 .cs_irq = -1,
922 .ecc_irq = 28,
923 .nvram_machine_id = 0x72,
924 .machine_id = ss20_id,
925 .iommu_version = 0x13000000,
926 .intbit_to_level = {
927 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
928 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
929 },
930 .max_mem = 0xf00000000ULL,
931 .default_cpu_model = "TI SuperSparc II",
932 },
933 /* SS-2 */
934 {
935 .iommu_base = 0xf8000000,
936 .tcx_base = 0xfe000000,
937 .cs_base = -1,
938 .slavio_base = 0xf6000000,
939 .ms_kb_base = 0xf0000000,
940 .serial_base = 0xf1000000,
941 .nvram_base = 0xf2000000,
942 .fd_base = 0xf7200000,
943 .counter_base = -1,
944 .intctl_base = -1,
945 .dma_base = 0xf8400000,
946 .esp_base = 0xf8800000,
947 .le_base = 0xf8c00000,
948 .apc_base = -1,
949 .aux1_base = 0xf7400003,
950 .aux2_base = -1,
951 .sun4c_intctl_base = 0xf5000000,
952 .sun4c_counter_base = 0xf3000000,
953 .vram_size = 0x00100000,
954 .nvram_size = 0x800,
955 .esp_irq = 2,
956 .le_irq = 3,
957 .clock_irq = 5,
958 .clock1_irq = 7,
959 .ms_kb_irq = 1,
960 .ser_irq = 1,
961 .fd_irq = 1,
962 .me_irq = 1,
963 .cs_irq = -1,
964 .nvram_machine_id = 0x55,
965 .machine_id = ss2_id,
966 .max_mem = 0x10000000,
967 .default_cpu_model = "Cypress CY7C601",
968 },
969 /* Voyager */
970 {
971 .iommu_base = 0x10000000,
972 .tcx_base = 0x50000000,
973 .cs_base = -1,
974 .slavio_base = 0x70000000,
975 .ms_kb_base = 0x71000000,
976 .serial_base = 0x71100000,
977 .nvram_base = 0x71200000,
978 .fd_base = 0x71400000,
979 .counter_base = 0x71d00000,
980 .intctl_base = 0x71e00000,
981 .idreg_base = 0x78000000,
982 .dma_base = 0x78400000,
983 .esp_base = 0x78800000,
984 .le_base = 0x78c00000,
985 .apc_base = 0x71300000, // pmc
986 .aux1_base = 0x71900000,
987 .aux2_base = 0x71910000,
988 .ecc_base = -1,
989 .sun4c_intctl_base = -1,
990 .sun4c_counter_base = -1,
991 .vram_size = 0x00100000,
992 .nvram_size = 0x2000,
993 .esp_irq = 18,
994 .le_irq = 16,
995 .clock_irq = 7,
996 .clock1_irq = 19,
997 .ms_kb_irq = 14,
998 .ser_irq = 15,
999 .fd_irq = 22,
1000 .me_irq = 30,
1001 .cs_irq = -1,
1002 .nvram_machine_id = 0x80,
1003 .machine_id = vger_id,
1004 .iommu_version = 0x05000000,
1005 .intbit_to_level = {
1006 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1007 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1008 },
1009 .max_mem = 0x10000000,
1010 .default_cpu_model = "Fujitsu MB86904",
1011 },
1012 /* LX */
1013 {
1014 .iommu_base = 0x10000000,
1015 .tcx_base = 0x50000000,
1016 .cs_base = -1,
1017 .slavio_base = 0x70000000,
1018 .ms_kb_base = 0x71000000,
1019 .serial_base = 0x71100000,
1020 .nvram_base = 0x71200000,
1021 .fd_base = 0x71400000,
1022 .counter_base = 0x71d00000,
1023 .intctl_base = 0x71e00000,
1024 .idreg_base = 0x78000000,
1025 .dma_base = 0x78400000,
1026 .esp_base = 0x78800000,
1027 .le_base = 0x78c00000,
1028 .apc_base = -1,
1029 .aux1_base = 0x71900000,
1030 .aux2_base = 0x71910000,
1031 .ecc_base = -1,
1032 .sun4c_intctl_base = -1,
1033 .sun4c_counter_base = -1,
1034 .vram_size = 0x00100000,
1035 .nvram_size = 0x2000,
1036 .esp_irq = 18,
1037 .le_irq = 16,
1038 .clock_irq = 7,
1039 .clock1_irq = 19,
1040 .ms_kb_irq = 14,
1041 .ser_irq = 15,
1042 .fd_irq = 22,
1043 .me_irq = 30,
1044 .cs_irq = -1,
1045 .nvram_machine_id = 0x80,
1046 .machine_id = lx_id,
1047 .iommu_version = 0x04000000,
1048 .intbit_to_level = {
1049 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1050 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1051 },
1052 .max_mem = 0x10000000,
1053 .default_cpu_model = "TI MicroSparc I",
1054 },
1055 /* SS-4 */
1056 {
1057 .iommu_base = 0x10000000,
1058 .tcx_base = 0x50000000,
1059 .cs_base = 0x6c000000,
1060 .slavio_base = 0x70000000,
1061 .ms_kb_base = 0x71000000,
1062 .serial_base = 0x71100000,
1063 .nvram_base = 0x71200000,
1064 .fd_base = 0x71400000,
1065 .counter_base = 0x71d00000,
1066 .intctl_base = 0x71e00000,
1067 .idreg_base = 0x78000000,
1068 .dma_base = 0x78400000,
1069 .esp_base = 0x78800000,
1070 .le_base = 0x78c00000,
1071 .apc_base = 0x6a000000,
1072 .aux1_base = 0x71900000,
1073 .aux2_base = 0x71910000,
1074 .ecc_base = -1,
1075 .sun4c_intctl_base = -1,
1076 .sun4c_counter_base = -1,
1077 .vram_size = 0x00100000,
1078 .nvram_size = 0x2000,
1079 .esp_irq = 18,
1080 .le_irq = 16,
1081 .clock_irq = 7,
1082 .clock1_irq = 19,
1083 .ms_kb_irq = 14,
1084 .ser_irq = 15,
1085 .fd_irq = 22,
1086 .me_irq = 30,
1087 .cs_irq = 5,
1088 .nvram_machine_id = 0x80,
1089 .machine_id = ss4_id,
1090 .iommu_version = 0x05000000,
1091 .intbit_to_level = {
1092 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1093 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1094 },
1095 .max_mem = 0x10000000,
1096 .default_cpu_model = "Fujitsu MB86904",
1097 },
1098 /* SPARCClassic */
1099 {
1100 .iommu_base = 0x10000000,
1101 .tcx_base = 0x50000000,
1102 .cs_base = -1,
1103 .slavio_base = 0x70000000,
1104 .ms_kb_base = 0x71000000,
1105 .serial_base = 0x71100000,
1106 .nvram_base = 0x71200000,
1107 .fd_base = 0x71400000,
1108 .counter_base = 0x71d00000,
1109 .intctl_base = 0x71e00000,
1110 .idreg_base = 0x78000000,
1111 .dma_base = 0x78400000,
1112 .esp_base = 0x78800000,
1113 .le_base = 0x78c00000,
1114 .apc_base = 0x6a000000,
1115 .aux1_base = 0x71900000,
1116 .aux2_base = 0x71910000,
1117 .ecc_base = -1,
1118 .sun4c_intctl_base = -1,
1119 .sun4c_counter_base = -1,
1120 .vram_size = 0x00100000,
1121 .nvram_size = 0x2000,
1122 .esp_irq = 18,
1123 .le_irq = 16,
1124 .clock_irq = 7,
1125 .clock1_irq = 19,
1126 .ms_kb_irq = 14,
1127 .ser_irq = 15,
1128 .fd_irq = 22,
1129 .me_irq = 30,
1130 .cs_irq = -1,
1131 .nvram_machine_id = 0x80,
1132 .machine_id = scls_id,
1133 .iommu_version = 0x05000000,
1134 .intbit_to_level = {
1135 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1136 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1137 },
1138 .max_mem = 0x10000000,
1139 .default_cpu_model = "TI MicroSparc I",
1140 },
1141 /* SPARCbook */
1142 {
1143 .iommu_base = 0x10000000,
1144 .tcx_base = 0x50000000, // XXX
1145 .cs_base = -1,
1146 .slavio_base = 0x70000000,
1147 .ms_kb_base = 0x71000000,
1148 .serial_base = 0x71100000,
1149 .nvram_base = 0x71200000,
1150 .fd_base = 0x71400000,
1151 .counter_base = 0x71d00000,
1152 .intctl_base = 0x71e00000,
1153 .idreg_base = 0x78000000,
1154 .dma_base = 0x78400000,
1155 .esp_base = 0x78800000,
1156 .le_base = 0x78c00000,
1157 .apc_base = 0x6a000000,
1158 .aux1_base = 0x71900000,
1159 .aux2_base = 0x71910000,
1160 .ecc_base = -1,
1161 .sun4c_intctl_base = -1,
1162 .sun4c_counter_base = -1,
1163 .vram_size = 0x00100000,
1164 .nvram_size = 0x2000,
1165 .esp_irq = 18,
1166 .le_irq = 16,
1167 .clock_irq = 7,
1168 .clock1_irq = 19,
1169 .ms_kb_irq = 14,
1170 .ser_irq = 15,
1171 .fd_irq = 22,
1172 .me_irq = 30,
1173 .cs_irq = -1,
1174 .nvram_machine_id = 0x80,
1175 .machine_id = sbook_id,
1176 .iommu_version = 0x05000000,
1177 .intbit_to_level = {
1178 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1179 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1180 },
1181 .max_mem = 0x10000000,
1182 .default_cpu_model = "TI MicroSparc I",
1183 },
1184 };
1185
1186 /* SPARCstation 5 hardware initialisation */
1187 static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
1188 const char *boot_device, DisplayState *ds,
1189 const char *kernel_filename, const char *kernel_cmdline,
1190 const char *initrd_filename, const char *cpu_model)
1191 {
1192 sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1193 kernel_cmdline, initrd_filename, cpu_model);
1194 }
1195
1196 /* SPARCstation 10 hardware initialisation */
1197 static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
1198 const char *boot_device, DisplayState *ds,
1199 const char *kernel_filename, const char *kernel_cmdline,
1200 const char *initrd_filename, const char *cpu_model)
1201 {
1202 sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1203 kernel_cmdline, initrd_filename, cpu_model);
1204 }
1205
1206 /* SPARCserver 600MP hardware initialisation */
1207 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
1208 const char *boot_device, DisplayState *ds,
1209 const char *kernel_filename,
1210 const char *kernel_cmdline,
1211 const char *initrd_filename, const char *cpu_model)
1212 {
1213 sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
1214 kernel_cmdline, initrd_filename, cpu_model);
1215 }
1216
1217 /* SPARCstation 20 hardware initialisation */
1218 static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
1219 const char *boot_device, DisplayState *ds,
1220 const char *kernel_filename, const char *kernel_cmdline,
1221 const char *initrd_filename, const char *cpu_model)
1222 {
1223 sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
1224 kernel_cmdline, initrd_filename, cpu_model);
1225 }
1226
1227 /* SPARCstation 2 hardware initialisation */
1228 static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1229 const char *boot_device, DisplayState *ds,
1230 const char *kernel_filename, const char *kernel_cmdline,
1231 const char *initrd_filename, const char *cpu_model)
1232 {
1233 sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
1234 kernel_cmdline, initrd_filename, cpu_model);
1235 }
1236
1237 /* SPARCstation Voyager hardware initialisation */
1238 static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
1239 const char *boot_device, DisplayState *ds,
1240 const char *kernel_filename, const char *kernel_cmdline,
1241 const char *initrd_filename, const char *cpu_model)
1242 {
1243 sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
1244 kernel_cmdline, initrd_filename, cpu_model);
1245 }
1246
1247 /* SPARCstation LX hardware initialisation */
1248 static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
1249 const char *boot_device, DisplayState *ds,
1250 const char *kernel_filename, const char *kernel_cmdline,
1251 const char *initrd_filename, const char *cpu_model)
1252 {
1253 sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
1254 kernel_cmdline, initrd_filename, cpu_model);
1255 }
1256
1257 /* SPARCstation 4 hardware initialisation */
1258 static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
1259 const char *boot_device, DisplayState *ds,
1260 const char *kernel_filename, const char *kernel_cmdline,
1261 const char *initrd_filename, const char *cpu_model)
1262 {
1263 sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
1264 kernel_cmdline, initrd_filename, cpu_model);
1265 }
1266
1267 /* SPARCClassic hardware initialisation */
1268 static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1269 const char *boot_device, DisplayState *ds,
1270 const char *kernel_filename, const char *kernel_cmdline,
1271 const char *initrd_filename, const char *cpu_model)
1272 {
1273 sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
1274 kernel_cmdline, initrd_filename, cpu_model);
1275 }
1276
1277 /* SPARCbook hardware initialisation */
1278 static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1279 const char *boot_device, DisplayState *ds,
1280 const char *kernel_filename, const char *kernel_cmdline,
1281 const char *initrd_filename, const char *cpu_model)
1282 {
1283 sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
1284 kernel_cmdline, initrd_filename, cpu_model);
1285 }
1286
1287 QEMUMachine ss5_machine = {
1288 .name = "SS-5",
1289 .desc = "Sun4m platform, SPARCstation 5",
1290 .init = ss5_init,
1291 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1292 .nodisk_ok = 1,
1293 };
1294
1295 QEMUMachine ss10_machine = {
1296 .name = "SS-10",
1297 .desc = "Sun4m platform, SPARCstation 10",
1298 .init = ss10_init,
1299 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1300 .nodisk_ok = 1,
1301 };
1302
1303 QEMUMachine ss600mp_machine = {
1304 .name = "SS-600MP",
1305 .desc = "Sun4m platform, SPARCserver 600MP",
1306 .init = ss600mp_init,
1307 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1308 .nodisk_ok = 1,
1309 };
1310
1311 QEMUMachine ss20_machine = {
1312 .name = "SS-20",
1313 .desc = "Sun4m platform, SPARCstation 20",
1314 .init = ss20_init,
1315 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1316 .nodisk_ok = 1,
1317 };
1318
1319 QEMUMachine ss2_machine = {
1320 .name = "SS-2",
1321 .desc = "Sun4c platform, SPARCstation 2",
1322 .init = ss2_init,
1323 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1324 .nodisk_ok = 1,
1325 };
1326
1327 QEMUMachine voyager_machine = {
1328 .name = "Voyager",
1329 .desc = "Sun4m platform, SPARCstation Voyager",
1330 .init = vger_init,
1331 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1332 .nodisk_ok = 1,
1333 };
1334
1335 QEMUMachine ss_lx_machine = {
1336 .name = "LX",
1337 .desc = "Sun4m platform, SPARCstation LX",
1338 .init = ss_lx_init,
1339 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1340 .nodisk_ok = 1,
1341 };
1342
1343 QEMUMachine ss4_machine = {
1344 .name = "SS-4",
1345 .desc = "Sun4m platform, SPARCstation 4",
1346 .init = ss4_init,
1347 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1348 .nodisk_ok = 1,
1349 };
1350
1351 QEMUMachine scls_machine = {
1352 .name = "SPARCClassic",
1353 .desc = "Sun4m platform, SPARCClassic",
1354 .init = scls_init,
1355 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1356 .nodisk_ok = 1,
1357 };
1358
1359 QEMUMachine sbook_machine = {
1360 .name = "SPARCbook",
1361 .desc = "Sun4m platform, SPARCbook",
1362 .init = sbook_init,
1363 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1364 .nodisk_ok = 1,
1365 };
1366
1367 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1368 /* SS-1000 */
1369 {
1370 .iounit_bases = {
1371 0xfe0200000ULL,
1372 0xfe1200000ULL,
1373 0xfe2200000ULL,
1374 0xfe3200000ULL,
1375 -1,
1376 },
1377 .tcx_base = 0x820000000ULL,
1378 .slavio_base = 0xf00000000ULL,
1379 .ms_kb_base = 0xf00240000ULL,
1380 .serial_base = 0xf00200000ULL,
1381 .nvram_base = 0xf00280000ULL,
1382 .counter_base = 0xf00300000ULL,
1383 .espdma_base = 0x800081000ULL,
1384 .esp_base = 0x800080000ULL,
1385 .ledma_base = 0x800040000ULL,
1386 .le_base = 0x800060000ULL,
1387 .sbi_base = 0xf02800000ULL,
1388 .vram_size = 0x00100000,
1389 .nvram_size = 0x2000,
1390 .esp_irq = 3,
1391 .le_irq = 4,
1392 .clock_irq = 14,
1393 .clock1_irq = 10,
1394 .ms_kb_irq = 12,
1395 .ser_irq = 12,
1396 .nvram_machine_id = 0x80,
1397 .machine_id = ss1000_id,
1398 .iounit_version = 0x03000000,
1399 .max_mem = 0xf00000000ULL,
1400 .default_cpu_model = "TI SuperSparc II",
1401 },
1402 /* SS-2000 */
1403 {
1404 .iounit_bases = {
1405 0xfe0200000ULL,
1406 0xfe1200000ULL,
1407 0xfe2200000ULL,
1408 0xfe3200000ULL,
1409 0xfe4200000ULL,
1410 },
1411 .tcx_base = 0x820000000ULL,
1412 .slavio_base = 0xf00000000ULL,
1413 .ms_kb_base = 0xf00240000ULL,
1414 .serial_base = 0xf00200000ULL,
1415 .nvram_base = 0xf00280000ULL,
1416 .counter_base = 0xf00300000ULL,
1417 .espdma_base = 0x800081000ULL,
1418 .esp_base = 0x800080000ULL,
1419 .ledma_base = 0x800040000ULL,
1420 .le_base = 0x800060000ULL,
1421 .sbi_base = 0xf02800000ULL,
1422 .vram_size = 0x00100000,
1423 .nvram_size = 0x2000,
1424 .esp_irq = 3,
1425 .le_irq = 4,
1426 .clock_irq = 14,
1427 .clock1_irq = 10,
1428 .ms_kb_irq = 12,
1429 .ser_irq = 12,
1430 .nvram_machine_id = 0x80,
1431 .machine_id = ss2000_id,
1432 .iounit_version = 0x03000000,
1433 .max_mem = 0xf00000000ULL,
1434 .default_cpu_model = "TI SuperSparc II",
1435 },
1436 };
1437
1438 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1439 const char *boot_device,
1440 DisplayState *ds, const char *kernel_filename,
1441 const char *kernel_cmdline,
1442 const char *initrd_filename, const char *cpu_model)
1443 {
1444 CPUState *env, *envs[MAX_CPUS];
1445 unsigned int i;
1446 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1447 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1448 *espdma_irq, *ledma_irq;
1449 qemu_irq *esp_reset, *le_reset;
1450 unsigned long prom_offset, kernel_size;
1451 int ret;
1452 char buf[1024];
1453 int drive_index;
1454 void *fw_cfg;
1455
1456 /* init CPUs */
1457 if (!cpu_model)
1458 cpu_model = hwdef->default_cpu_model;
1459
1460 for (i = 0; i < smp_cpus; i++) {
1461 env = cpu_init(cpu_model);
1462 if (!env) {
1463 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1464 exit(1);
1465 }
1466 cpu_sparc_set_id(env, i);
1467 envs[i] = env;
1468 if (i == 0) {
1469 qemu_register_reset(main_cpu_reset, env);
1470 } else {
1471 qemu_register_reset(secondary_cpu_reset, env);
1472 env->halted = 1;
1473 }
1474 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1475 env->prom_addr = hwdef->slavio_base;
1476 }
1477
1478 for (i = smp_cpus; i < MAX_CPUS; i++)
1479 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1480
1481 /* allocate RAM */
1482 if ((uint64_t)RAM_size > hwdef->max_mem) {
1483 fprintf(stderr,
1484 "qemu: Too much memory for this machine: %d, maximum %d\n",
1485 (unsigned int)(RAM_size / (1024 * 1024)),
1486 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1487 exit(1);
1488 }
1489 cpu_register_physical_memory(0, RAM_size, 0);
1490
1491 /* load boot prom */
1492 prom_offset = RAM_size + hwdef->vram_size;
1493 cpu_register_physical_memory(hwdef->slavio_base,
1494 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1495 TARGET_PAGE_MASK,
1496 prom_offset | IO_MEM_ROM);
1497
1498 if (bios_name == NULL)
1499 bios_name = PROM_FILENAME;
1500 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1501 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1502 if (ret < 0 || ret > PROM_SIZE_MAX)
1503 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1504 if (ret < 0 || ret > PROM_SIZE_MAX) {
1505 fprintf(stderr, "qemu: could not load prom '%s'\n",
1506 buf);
1507 exit(1);
1508 }
1509
1510 /* set up devices */
1511 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1512
1513 for (i = 0; i < MAX_IOUNITS; i++)
1514 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1515 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1516 hwdef->iounit_version,
1517 sbi_irq[hwdef->me_irq]);
1518
1519 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1520 iounits[0], &espdma_irq, &esp_reset);
1521
1522 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1523 iounits[0], &ledma_irq, &le_reset);
1524
1525 if (graphic_depth != 8 && graphic_depth != 24) {
1526 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1527 exit (1);
1528 }
1529 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1530 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1531
1532 if (nd_table[0].model == NULL
1533 || strcmp(nd_table[0].model, "lance") == 0) {
1534 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1535 } else if (strcmp(nd_table[0].model, "?") == 0) {
1536 fprintf(stderr, "qemu: Supported NICs: lance\n");
1537 exit (1);
1538 } else {
1539 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1540 exit (1);
1541 }
1542
1543 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1544 hwdef->nvram_size, 8);
1545
1546 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1547 sbi_cpu_irq, smp_cpus);
1548
1549 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1550 nographic);
1551 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1552 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1553 slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1554 serial_hds[1], serial_hds[0]);
1555
1556 if (drive_get_max_bus(IF_SCSI) > 0) {
1557 fprintf(stderr, "qemu: too many SCSI bus\n");
1558 exit(1);
1559 }
1560
1561 main_esp = esp_init(hwdef->esp_base, 2,
1562 espdma_memory_read, espdma_memory_write,
1563 espdma, *espdma_irq, esp_reset);
1564
1565 for (i = 0; i < ESP_MAX_DEVS; i++) {
1566 drive_index = drive_get_index(IF_SCSI, 0, i);
1567 if (drive_index == -1)
1568 continue;
1569 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1570 }
1571
1572 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1573 RAM_size);
1574
1575 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1576 boot_device, RAM_size, kernel_size, graphic_width,
1577 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1578 "Sun4d");
1579
1580 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1581 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1582 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1583 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1584 }
1585
1586 /* SPARCserver 1000 hardware initialisation */
1587 static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1588 const char *boot_device, DisplayState *ds,
1589 const char *kernel_filename, const char *kernel_cmdline,
1590 const char *initrd_filename, const char *cpu_model)
1591 {
1592 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1593 kernel_cmdline, initrd_filename, cpu_model);
1594 }
1595
1596 /* SPARCcenter 2000 hardware initialisation */
1597 static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1598 const char *boot_device, DisplayState *ds,
1599 const char *kernel_filename, const char *kernel_cmdline,
1600 const char *initrd_filename, const char *cpu_model)
1601 {
1602 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1603 kernel_cmdline, initrd_filename, cpu_model);
1604 }
1605
1606 QEMUMachine ss1000_machine = {
1607 .name = "SS-1000",
1608 .desc = "Sun4d platform, SPARCserver 1000",
1609 .init = ss1000_init,
1610 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1611 .nodisk_ok = 1,
1612 };
1613
1614 QEMUMachine ss2000_machine = {
1615 .name = "SS-2000",
1616 .desc = "Sun4d platform, SPARCcenter 2000",
1617 .init = ss2000_init,
1618 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1619 .nodisk_ok = 1,
1620 };
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