hw/sun4m.c

   1 /*
   2  * QEMU Sun4m System Emulator
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25 //#define DEBUG_IRQ
  26
  27 /*
  28  * Sun4m architecture was used in the following machines:
  29  *
  30  * SPARCserver 6xxMP/xx
  31  * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
  32  * SPARCstation LX/ZX (4/30)
  33  * SPARCstation Voyager
  34  * SPARCstation 10/xx, SPARCserver 10/xx
  35  * SPARCstation 5, SPARCserver 5
  36  * SPARCstation 20/xx, SPARCserver 20
  37  * SPARCstation 4
  38  *
  39  * See for example: http://www.sunhelp.org/faq/sunref1.html
  40  */
  41
  42 #ifdef DEBUG_IRQ
  43 #define DPRINTF(fmt, args...)                           \
  44     do { printf("CPUIRQ: " fmt , ##args); } while (0)
  45 #else
  46 #define DPRINTF(fmt, args...)
  47 #endif
  48
  49 #define KERNEL_LOAD_ADDR     0x00004000
  50 #define CMDLINE_ADDR         0x007ff000
  51 #define INITRD_LOAD_ADDR     0x00800000
  52 #define PROM_SIZE_MAX        (512 * 1024)
  53 #define PROM_PADDR           0xff0000000ULL
  54 #define PROM_VADDR           0xffd00000
  55 #define PROM_FILENAME        "openbios-sparc32"
  56
  57 #define MAX_CPUS 16
  58 #define MAX_PILS 16
  59
  60 struct hwdef {
  61     target_phys_addr_t iommu_base, slavio_base;
  62     target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
  63     target_phys_addr_t serial_base, fd_base;
  64     target_phys_addr_t dma_base, esp_base, le_base;
  65     target_phys_addr_t tcx_base, cs_base, power_base;
  66     long vram_size, nvram_size;
  67     // IRQ numbers are not PIL ones, but master interrupt controller register
  68     // bit numbers
  69     int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
  70     int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
  71     int machine_id; // For NVRAM
  72     uint32_t intbit_to_level[32];
  73 };
  74
  75 /* TSC handling */
  76
  77 uint64_t cpu_get_tsc()
  78 {
  79     return qemu_get_clock(vm_clock);
  80 }
  81
  82 int DMA_get_channel_mode (int nchan)
  83 {
  84     return 0;
  85 }
  86 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  87 {
  88     return 0;
  89 }
  90 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  91 {
  92     return 0;
  93 }
  94 void DMA_hold_DREQ (int nchan) {}
  95 void DMA_release_DREQ (int nchan) {}
  96 void DMA_schedule(int nchan) {}
  97 void DMA_run (void) {}
  98 void DMA_init (int high_page_enable) {}
  99 void DMA_register_channel (int nchan,
 100                            DMA_transfer_handler transfer_handler,
 101                            void *opaque)
 102 {
 103 }
 104
 105 static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
 106 {
 107     m48t59_write(nvram, addr++, (value >> 8) & 0xff);
 108     m48t59_write(nvram, addr++, value & 0xff);
 109 }
 110
 111 static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
 112 {
 113     m48t59_write(nvram, addr++, value >> 24);
 114     m48t59_write(nvram, addr++, (value >> 16) & 0xff);
 115     m48t59_write(nvram, addr++, (value >> 8) & 0xff);
 116     m48t59_write(nvram, addr++, value & 0xff);
 117 }
 118
 119 static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
 120                        const unsigned char *str, uint32_t max)
 121 {
 122     unsigned int i;
 123
 124     for (i = 0; i < max && str[i] != '\0'; i++) {
 125         m48t59_write(nvram, addr + i, str[i]);
 126     }
 127     m48t59_write(nvram, addr + max - 1, '\0');
 128 }
 129
 130 static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
 131                                 const unsigned char *str)
 132 {
 133     uint32_t len;
 134
 135     len = strlen(str) + 1;
 136     nvram_set_string(nvram, addr, str, len);
 137
 138     return addr + len;
 139 }
 140
 141 static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
 142                                     uint32_t end)
 143 {
 144     unsigned int i, sum;
 145
 146     // Length divided by 16
 147     m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
 148     m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
 149     // Checksum
 150     sum = m48t59_read(nvram, start);
 151     for (i = 0; i < 14; i++) {
 152         sum += m48t59_read(nvram, start + 2 + i);
 153         sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
 154     }
 155     m48t59_write(nvram, start + 1, sum & 0xff);
 156 }
 157
 158 extern int nographic;
 159
 160 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
 161                        const char *boot_device, uint32_t RAM_size,
 162                        uint32_t kernel_size,
 163                        int width, int height, int depth,
 164                        int machine_id)
 165 {
 166     unsigned char tmp = 0;
 167     unsigned int i, j;
 168     uint32_t start, end;
 169
 170     // Try to match PPC NVRAM
 171     nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
 172     nvram_set_lword(nvram,  0x10, 0x00000001); /* structure v1 */
 173     // NVRAM_size, arch not applicable
 174     m48t59_write(nvram, 0x2D, smp_cpus & 0xff);
 175     m48t59_write(nvram, 0x2E, 0);
 176     m48t59_write(nvram, 0x2F, nographic & 0xff);
 177     nvram_set_lword(nvram,  0x30, RAM_size);
 178     m48t59_write(nvram, 0x34, boot_device[0] & 0xff);
 179     nvram_set_lword(nvram,  0x38, KERNEL_LOAD_ADDR);
 180     nvram_set_lword(nvram,  0x3C, kernel_size);
 181     if (cmdline) {
 182         strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
 183         nvram_set_lword(nvram,  0x40, CMDLINE_ADDR);
 184         nvram_set_lword(nvram,  0x44, strlen(cmdline));
 185     }
 186     // initrd_image, initrd_size passed differently
 187     nvram_set_word(nvram,   0x54, width);
 188     nvram_set_word(nvram,   0x56, height);
 189     nvram_set_word(nvram,   0x58, depth);
 190
 191     // OpenBIOS nvram variables
 192     // Variable partition
 193     start = 252;
 194     m48t59_write(nvram, start, 0x70);
 195     nvram_set_string(nvram, start + 4, "system", 12);
 196
 197     end = start + 16;
 198     for (i = 0; i < nb_prom_envs; i++)
 199         end = nvram_set_var(nvram, end, prom_envs[i]);
 200
 201     m48t59_write(nvram, end++ , 0);
 202     end = start + ((end - start + 15) & ~15);
 203     nvram_finish_partition(nvram, start, end);
 204
 205     // free partition
 206     start = end;
 207     m48t59_write(nvram, start, 0x7f);
 208     nvram_set_string(nvram, start + 4, "free", 12);
 209
 210     end = 0x1fd0;
 211     nvram_finish_partition(nvram, start, end);
 212
 213     // Sun4m specific use
 214     start = i = 0x1fd8;
 215     m48t59_write(nvram, i++, 0x01);
 216     m48t59_write(nvram, i++, machine_id);
 217     j = 0;
 218     m48t59_write(nvram, i++, macaddr[j++]);
 219     m48t59_write(nvram, i++, macaddr[j++]);
 220     m48t59_write(nvram, i++, macaddr[j++]);
 221     m48t59_write(nvram, i++, macaddr[j++]);
 222     m48t59_write(nvram, i++, macaddr[j++]);
 223     m48t59_write(nvram, i, macaddr[j]);
 224
 225     /* Calculate checksum */
 226     for (i = start; i < start + 15; i++) {
 227         tmp ^= m48t59_read(nvram, i);
 228     }
 229     m48t59_write(nvram, start + 15, tmp);
 230 }
 231
 232 static void *slavio_intctl;
 233
 234 void pic_info()
 235 {
 236     slavio_pic_info(slavio_intctl);
 237 }
 238
 239 void irq_info()
 240 {
 241     slavio_irq_info(slavio_intctl);
 242 }
 243
 244 void cpu_check_irqs(CPUState *env)
 245 {
 246     if (env->pil_in && (env->interrupt_index == 0 ||
 247                         (env->interrupt_index & ~15) == TT_EXTINT)) {
 248         unsigned int i;
 249
 250         for (i = 15; i > 0; i--) {
 251             if (env->pil_in & (1 << i)) {
 252                 int old_interrupt = env->interrupt_index;
 253
 254                 env->interrupt_index = TT_EXTINT | i;
 255                 if (old_interrupt != env->interrupt_index)
 256                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 257                 break;
 258             }
 259         }
 260     } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
 261         env->interrupt_index = 0;
 262         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 263     }
 264 }
 265
 266 static void cpu_set_irq(void *opaque, int irq, int level)
 267 {
 268     CPUState *env = opaque;
 269
 270     if (level) {
 271         DPRINTF("Raise CPU IRQ %d\n", irq);
 272         env->halted = 0;
 273         env->pil_in |= 1 << irq;
 274         cpu_check_irqs(env);
 275     } else {
 276         DPRINTF("Lower CPU IRQ %d\n", irq);
 277         env->pil_in &= ~(1 << irq);
 278         cpu_check_irqs(env);
 279     }
 280 }
 281
 282 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
 283 {
 284 }
 285
 286 static void *slavio_misc;
 287
 288 void qemu_system_powerdown(void)
 289 {
 290     slavio_set_power_fail(slavio_misc, 1);
 291 }
 292
 293 static void main_cpu_reset(void *opaque)
 294 {
 295     CPUState *env = opaque;
 296
 297     cpu_reset(env);
 298     env->halted = 0;
 299 }
 300
 301 static void secondary_cpu_reset(void *opaque)
 302 {
 303     CPUState *env = opaque;
 304
 305     cpu_reset(env);
 306     env->halted = 1;
 307 }
 308
 309 static void *sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
 310                            DisplayState *ds, const char *cpu_model)
 311
 312 {
 313     CPUState *env, *envs[MAX_CPUS];
 314     unsigned int i;
 315     void *iommu, *espdma, *ledma, *main_esp, *nvram;
 316     qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
 317         *espdma_irq, *ledma_irq;
 318     qemu_irq *esp_reset, *le_reset;
 319
 320     /* init CPUs */
 321
 322     for(i = 0; i < smp_cpus; i++) {
 323         env = cpu_init(cpu_model);
 324         if (!env) {
 325             fprintf(stderr, "Unable to find Sparc CPU definition\n");
 326             exit(1);
 327         }
 328         cpu_sparc_set_id(env, i);
 329         envs[i] = env;
 330         if (i == 0) {
 331             qemu_register_reset(main_cpu_reset, env);
 332         } else {
 333             qemu_register_reset(secondary_cpu_reset, env);
 334             env->halted = 1;
 335         }
 336         register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
 337         cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
 338     }
 339
 340     for (i = smp_cpus; i < MAX_CPUS; i++)
 341         cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
 342
 343     /* allocate RAM */
 344     cpu_register_physical_memory(0, RAM_size, 0);
 345
 346     iommu = iommu_init(hwdef->iommu_base);
 347     slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
 348                                        hwdef->intctl_base + 0x10000ULL,
 349                                        &hwdef->intbit_to_level[0],
 350                                        &slavio_irq, &slavio_cpu_irq,
 351                                        cpu_irqs,
 352                                        hwdef->clock_irq);
 353
 354     espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
 355                               iommu, &espdma_irq, &esp_reset);
 356
 357     ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
 358                              slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
 359                              &le_reset);
 360
 361     if (graphic_depth != 8 && graphic_depth != 24) {
 362         fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
 363         exit (1);
 364     }
 365     tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
 366              hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
 367
 368     if (nd_table[0].model == NULL
 369         || strcmp(nd_table[0].model, "lance") == 0) {
 370         lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
 371     } else if (strcmp(nd_table[0].model, "?") == 0) {
 372         fprintf(stderr, "qemu: Supported NICs: lance\n");
 373         exit (1);
 374     } else {
 375         fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 376         exit (1);
 377     }
 378
 379     nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
 380                         hwdef->nvram_size, 8);
 381
 382     slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
 383                           slavio_cpu_irq);
 384
 385     slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]);
 386     // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
 387     // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
 388     slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
 389                        serial_hds[1], serial_hds[0]);
 390
 391     if (hwdef->fd_base != (target_phys_addr_t)-1)
 392         sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd_table);
 393
 394     main_esp = esp_init(bs_table, hwdef->esp_base, espdma, *espdma_irq,
 395                         esp_reset);
 396
 397     for (i = 0; i < MAX_DISKS; i++) {
 398         if (bs_table[i]) {
 399             esp_scsi_attach(main_esp, bs_table[i], i);
 400         }
 401     }
 402
 403     slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->power_base,
 404                                    slavio_irq[hwdef->me_irq]);
 405     if (hwdef->cs_base != (target_phys_addr_t)-1)
 406         cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
 407
 408     return nvram;
 409 }
 410
 411 static void sun4m_load_kernel(long vram_size, int RAM_size,
 412                               const char *boot_device,
 413                               const char *kernel_filename,
 414                               const char *kernel_cmdline,
 415                               const char *initrd_filename,
 416                               int machine_id,
 417                               void *nvram)
 418 {
 419     int ret, linux_boot;
 420     char buf[1024];
 421     unsigned int i;
 422     long prom_offset, initrd_size, kernel_size;
 423
 424     linux_boot = (kernel_filename != NULL);
 425
 426     prom_offset = RAM_size + vram_size;
 427     cpu_register_physical_memory(PROM_PADDR,
 428                                  (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK,
 429                                  prom_offset | IO_MEM_ROM);
 430
 431     if (bios_name == NULL)
 432         bios_name = PROM_FILENAME;
 433     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 434     ret = load_elf(buf, PROM_PADDR - PROM_VADDR, NULL, NULL, NULL);
 435     if (ret < 0 || ret > PROM_SIZE_MAX)
 436         ret = load_image(buf, phys_ram_base + prom_offset);
 437     if (ret < 0 || ret > PROM_SIZE_MAX) {
 438         fprintf(stderr, "qemu: could not load prom '%s'\n",
 439                 buf);
 440         exit(1);
 441     }
 442
 443     kernel_size = 0;
 444     if (linux_boot) {
 445         kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
 446                                NULL);
 447         if (kernel_size < 0)
 448             kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
 449         if (kernel_size < 0)
 450             kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
 451         if (kernel_size < 0) {
 452             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 453                     kernel_filename);
 454             exit(1);
 455         }
 456
 457         /* load initrd */
 458         initrd_size = 0;
 459         if (initrd_filename) {
 460             initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
 461             if (initrd_size < 0) {
 462                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 463                         initrd_filename);
 464                 exit(1);
 465             }
 466         }
 467         if (initrd_size > 0) {
 468             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 469                 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
 470                     == 0x48647253) { // HdrS
 471                     stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 472                     stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
 473                     break;
 474                 }
 475             }
 476         }
 477     }
 478     nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
 479                boot_device, RAM_size, kernel_size, graphic_width,
 480                graphic_height, graphic_depth, machine_id);
 481 }
 482
 483 static const struct hwdef hwdefs[] = {
 484     /* SS-5 */
 485     {
 486         .iommu_base   = 0x10000000,
 487         .tcx_base     = 0x50000000,
 488         .cs_base      = 0x6c000000,
 489         .slavio_base  = 0x70000000,
 490         .ms_kb_base   = 0x71000000,
 491         .serial_base  = 0x71100000,
 492         .nvram_base   = 0x71200000,
 493         .fd_base      = 0x71400000,
 494         .counter_base = 0x71d00000,
 495         .intctl_base  = 0x71e00000,
 496         .dma_base     = 0x78400000,
 497         .esp_base     = 0x78800000,
 498         .le_base      = 0x78c00000,
 499         .power_base   = 0x7a000000,
 500         .vram_size    = 0x00100000,
 501         .nvram_size   = 0x2000,
 502         .esp_irq = 18,
 503         .le_irq = 16,
 504         .clock_irq = 7,
 505         .clock1_irq = 19,
 506         .ms_kb_irq = 14,
 507         .ser_irq = 15,
 508         .fd_irq = 22,
 509         .me_irq = 30,
 510         .cs_irq = 5,
 511         .machine_id = 0x80,
 512         .intbit_to_level = {
 513             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
 514             6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
 515         },
 516     },
 517     /* SS-10 */
 518     {
 519         .iommu_base   = 0xfe0000000ULL,
 520         .tcx_base     = 0xe20000000ULL,
 521         .cs_base      = -1,
 522         .slavio_base  = 0xff0000000ULL,
 523         .ms_kb_base   = 0xff1000000ULL,
 524         .serial_base  = 0xff1100000ULL,
 525         .nvram_base   = 0xff1200000ULL,
 526         .fd_base      = 0xff1700000ULL,
 527         .counter_base = 0xff1300000ULL,
 528         .intctl_base  = 0xff1400000ULL,
 529         .dma_base     = 0xef0400000ULL,
 530         .esp_base     = 0xef0800000ULL,
 531         .le_base      = 0xef0c00000ULL,
 532         .power_base   = 0xefa000000ULL,
 533         .vram_size    = 0x00100000,
 534         .nvram_size   = 0x2000,
 535         .esp_irq = 18,
 536         .le_irq = 16,
 537         .clock_irq = 7,
 538         .clock1_irq = 19,
 539         .ms_kb_irq = 14,
 540         .ser_irq = 15,
 541         .fd_irq = 22,
 542         .me_irq = 30,
 543         .cs_irq = -1,
 544         .machine_id = 0x72,
 545         .intbit_to_level = {
 546             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
 547             6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
 548         },
 549     },
 550     /* SS-600MP */
 551     {
 552         .iommu_base   = 0xfe0000000ULL,
 553         .tcx_base     = 0xe20000000ULL,
 554         .cs_base      = -1,
 555         .slavio_base  = 0xff0000000ULL,
 556         .ms_kb_base   = 0xff1000000ULL,
 557         .serial_base  = 0xff1100000ULL,
 558         .nvram_base   = 0xff1200000ULL,
 559         .fd_base      = -1,
 560         .counter_base = 0xff1300000ULL,
 561         .intctl_base  = 0xff1400000ULL,
 562         .dma_base     = 0xef0081000ULL,
 563         .esp_base     = 0xef0080000ULL,
 564         .le_base      = 0xef0060000ULL,
 565         .power_base   = 0xefa000000ULL,
 566         .vram_size    = 0x00100000,
 567         .nvram_size   = 0x2000,
 568         .esp_irq = 18,
 569         .le_irq = 16,
 570         .clock_irq = 7,
 571         .clock1_irq = 19,
 572         .ms_kb_irq = 14,
 573         .ser_irq = 15,
 574         .fd_irq = 22,
 575         .me_irq = 30,
 576         .cs_irq = -1,
 577         .machine_id = 0x71,
 578         .intbit_to_level = {
 579             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
 580             6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
 581         },
 582     },
 583 };
 584
 585 static void sun4m_common_init(int RAM_size, const char *boot_device, DisplayState *ds,
 586                               const char *kernel_filename, const char *kernel_cmdline,
 587                               const char *initrd_filename, const char *cpu_model,
 588                               unsigned int machine, int max_ram)
 589 {
 590     void *nvram;
 591
 592     if ((unsigned int)RAM_size > (unsigned int)max_ram) {
 593         fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
 594                 (unsigned int)RAM_size / (1024 * 1024),
 595                 (unsigned int)max_ram / (1024 * 1024));
 596         exit(1);
 597     }
 598     nvram = sun4m_hw_init(&hwdefs[machine], RAM_size, ds, cpu_model);
 599
 600     sun4m_load_kernel(hwdefs[machine].vram_size, RAM_size, boot_device,
 601                       kernel_filename, kernel_cmdline, initrd_filename,
 602                       hwdefs[machine].machine_id, nvram);
 603 }
 604
 605 /* SPARCstation 5 hardware initialisation */
 606 static void ss5_init(int RAM_size, int vga_ram_size, const char *boot_device,
 607                        DisplayState *ds, const char **fd_filename, int snapshot,
 608                        const char *kernel_filename, const char *kernel_cmdline,
 609                        const char *initrd_filename, const char *cpu_model)
 610 {
 611     if (cpu_model == NULL)
 612         cpu_model = "Fujitsu MB86904";
 613     sun4m_common_init(RAM_size, boot_device, ds, kernel_filename,
 614                       kernel_cmdline, initrd_filename, cpu_model,
 615                       0, 0x10000000);
 616 }
 617
 618 /* SPARCstation 10 hardware initialisation */
 619 static void ss10_init(int RAM_size, int vga_ram_size, const char *boot_device,
 620                             DisplayState *ds, const char **fd_filename, int snapshot,
 621                             const char *kernel_filename, const char *kernel_cmdline,
 622                             const char *initrd_filename, const char *cpu_model)
 623 {
 624     if (cpu_model == NULL)
 625         cpu_model = "TI SuperSparc II";
 626     sun4m_common_init(RAM_size, boot_device, ds, kernel_filename,
 627                       kernel_cmdline, initrd_filename, cpu_model,
 628                       1, 0xffffffff); // XXX actually first 62GB ok
 629 }
 630
 631 /* SPARCserver 600MP hardware initialisation */
 632 static void ss600mp_init(int RAM_size, int vga_ram_size, const char *boot_device,
 633                          DisplayState *ds, const char **fd_filename, int snapshot,
 634                          const char *kernel_filename, const char *kernel_cmdline,
 635                          const char *initrd_filename, const char *cpu_model)
 636 {
 637     if (cpu_model == NULL)
 638         cpu_model = "TI SuperSparc II";
 639     sun4m_common_init(RAM_size, boot_device, ds, kernel_filename,
 640                       kernel_cmdline, initrd_filename, cpu_model,
 641                       2, 0xffffffff); // XXX actually first 62GB ok
 642 }
 643
 644 QEMUMachine ss5_machine = {
 645     "SS-5",
 646     "Sun4m platform, SPARCstation 5",
 647     ss5_init,
 648 };
 649
 650 QEMUMachine ss10_machine = {
 651     "SS-10",
 652     "Sun4m platform, SPARCstation 10",
 653     ss10_init,
 654 };
 655
 656 QEMUMachine ss600mp_machine = {
 657     "SS-600MP",
 658     "Sun4m platform, SPARCserver 600MP",
 659     ss600mp_init,
 660 };