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1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35
36 //#define DEBUG_IRQ
37
38 /*
39 * Sun4m architecture was used in the following machines:
40 *
41 * SPARCserver 6xxMP/xx
42 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
43 * SPARCstation LX/ZX (4/30)
44 * SPARCstation Voyager
45 * SPARCstation 10/xx, SPARCserver 10/xx
46 * SPARCstation 5, SPARCserver 5
47 * SPARCstation 20/xx, SPARCserver 20
48 * SPARCstation 4
49 *
50 * Sun4d architecture was used in the following machines:
51 *
52 * SPARCcenter 2000
53 * SPARCserver 1000
54 *
55 * Sun4c architecture was used in the following machines:
56 * SPARCstation 1/1+, SPARCserver 1/1+
57 * SPARCstation SLC
58 * SPARCstation IPC
59 * SPARCstation ELC
60 * SPARCstation IPX
61 *
62 * See for example: http://www.sunhelp.org/faq/sunref1.html
63 */
64
65 #ifdef DEBUG_IRQ
66 #define DPRINTF(fmt, args...) \
67 do { printf("CPUIRQ: " fmt , ##args); } while (0)
68 #else
69 #define DPRINTF(fmt, args...)
70 #endif
71
72 #define KERNEL_LOAD_ADDR 0x00004000
73 #define CMDLINE_ADDR 0x007ff000
74 #define INITRD_LOAD_ADDR 0x00800000
75 #define PROM_SIZE_MAX (512 * 1024)
76 #define PROM_VADDR 0xffd00000
77 #define PROM_FILENAME "openbios-sparc32"
78
79 #define MAX_CPUS 16
80 #define MAX_PILS 16
81
82 struct hwdef {
83 target_phys_addr_t iommu_base, slavio_base;
84 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
85 target_phys_addr_t serial_base, fd_base;
86 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
87 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
88 target_phys_addr_t ecc_base;
89 uint32_t ecc_version;
90 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
91 long vram_size, nvram_size;
92 // IRQ numbers are not PIL ones, but master interrupt controller
93 // register bit numbers
94 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
95 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
96 int machine_id; // For NVRAM
97 uint32_t iommu_version;
98 uint32_t intbit_to_level[32];
99 uint64_t max_mem;
100 const char * const default_cpu_model;
101 };
102
103 #define MAX_IOUNITS 5
104
105 struct sun4d_hwdef {
106 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
107 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
108 target_phys_addr_t serial_base;
109 target_phys_addr_t espdma_base, esp_base;
110 target_phys_addr_t ledma_base, le_base;
111 target_phys_addr_t tcx_base;
112 target_phys_addr_t sbi_base;
113 unsigned long vram_size, nvram_size;
114 // IRQ numbers are not PIL ones, but SBI register bit numbers
115 int esp_irq, le_irq, clock_irq, clock1_irq;
116 int ser_irq, ms_kb_irq, me_irq;
117 int machine_id; // For NVRAM
118 uint32_t iounit_version;
119 uint64_t max_mem;
120 const char * const default_cpu_model;
121 };
122
123 /* TSC handling */
124
125 uint64_t cpu_get_tsc()
126 {
127 return qemu_get_clock(vm_clock);
128 }
129
130 int DMA_get_channel_mode (int nchan)
131 {
132 return 0;
133 }
134 int DMA_read_memory (int nchan, void *buf, int pos, int size)
135 {
136 return 0;
137 }
138 int DMA_write_memory (int nchan, void *buf, int pos, int size)
139 {
140 return 0;
141 }
142 void DMA_hold_DREQ (int nchan) {}
143 void DMA_release_DREQ (int nchan) {}
144 void DMA_schedule(int nchan) {}
145 void DMA_run (void) {}
146 void DMA_init (int high_page_enable) {}
147 void DMA_register_channel (int nchan,
148 DMA_transfer_handler transfer_handler,
149 void *opaque)
150 {
151 }
152
153 extern int nographic;
154
155 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
156 const char *boot_devices, uint32_t RAM_size,
157 uint32_t kernel_size,
158 int width, int height, int depth,
159 int machine_id, const char *arch)
160 {
161 unsigned int i;
162 uint32_t start, end;
163 uint8_t image[0x1ff0];
164 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
165 struct sparc_arch_cfg *sparc_header;
166 struct OpenBIOS_nvpart_v1 *part_header;
167
168 memset(image, '\0', sizeof(image));
169
170 // Try to match PPC NVRAM
171 strcpy(header->struct_ident, "QEMU_BIOS");
172 header->struct_version = cpu_to_be32(3); /* structure v3 */
173
174 header->nvram_size = cpu_to_be16(0x2000);
175 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
176 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
177 strcpy(header->arch, arch);
178 header->nb_cpus = smp_cpus & 0xff;
179 header->RAM0_base = 0;
180 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
181 strcpy(header->boot_devices, boot_devices);
182 header->nboot_devices = strlen(boot_devices) & 0xff;
183 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
184 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
185 if (cmdline) {
186 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
187 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
188 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
189 }
190 // XXX add initrd_image, initrd_size
191 header->width = cpu_to_be16(width);
192 header->height = cpu_to_be16(height);
193 header->depth = cpu_to_be16(depth);
194 if (nographic)
195 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
196
197 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
198
199 // Architecture specific header
200 start = sizeof(ohwcfg_v3_t);
201 sparc_header = (struct sparc_arch_cfg *)&image[start];
202 sparc_header->valid = 0;
203 start += sizeof(struct sparc_arch_cfg);
204
205 // OpenBIOS nvram variables
206 // Variable partition
207 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
208 part_header->signature = OPENBIOS_PART_SYSTEM;
209 strcpy(part_header->name, "system");
210
211 end = start + sizeof(struct OpenBIOS_nvpart_v1);
212 for (i = 0; i < nb_prom_envs; i++)
213 end = OpenBIOS_set_var(image, end, prom_envs[i]);
214
215 // End marker
216 image[end++] = '\0';
217
218 end = start + ((end - start + 15) & ~15);
219 OpenBIOS_finish_partition(part_header, end - start);
220
221 // free partition
222 start = end;
223 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
224 part_header->signature = OPENBIOS_PART_FREE;
225 strcpy(part_header->name, "free");
226
227 end = 0x1fd0;
228 OpenBIOS_finish_partition(part_header, end - start);
229
230 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id);
231
232 for (i = 0; i < sizeof(image); i++)
233 m48t59_write(nvram, i, image[i]);
234 }
235
236 static void *slavio_intctl;
237
238 void pic_info()
239 {
240 if (slavio_intctl)
241 slavio_pic_info(slavio_intctl);
242 }
243
244 void irq_info()
245 {
246 if (slavio_intctl)
247 slavio_irq_info(slavio_intctl);
248 }
249
250 void cpu_check_irqs(CPUState *env)
251 {
252 if (env->pil_in && (env->interrupt_index == 0 ||
253 (env->interrupt_index & ~15) == TT_EXTINT)) {
254 unsigned int i;
255
256 for (i = 15; i > 0; i--) {
257 if (env->pil_in & (1 << i)) {
258 int old_interrupt = env->interrupt_index;
259
260 env->interrupt_index = TT_EXTINT | i;
261 if (old_interrupt != env->interrupt_index) {
262 DPRINTF("Set CPU IRQ %d\n", i);
263 cpu_interrupt(env, CPU_INTERRUPT_HARD);
264 }
265 break;
266 }
267 }
268 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
269 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
270 env->interrupt_index = 0;
271 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
272 }
273 }
274
275 static void cpu_set_irq(void *opaque, int irq, int level)
276 {
277 CPUState *env = opaque;
278
279 if (level) {
280 DPRINTF("Raise CPU IRQ %d\n", irq);
281 env->halted = 0;
282 env->pil_in |= 1 << irq;
283 cpu_check_irqs(env);
284 } else {
285 DPRINTF("Lower CPU IRQ %d\n", irq);
286 env->pil_in &= ~(1 << irq);
287 cpu_check_irqs(env);
288 }
289 }
290
291 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
292 {
293 }
294
295 static void *slavio_misc;
296
297 void qemu_system_powerdown(void)
298 {
299 slavio_set_power_fail(slavio_misc, 1);
300 }
301
302 static void main_cpu_reset(void *opaque)
303 {
304 CPUState *env = opaque;
305
306 cpu_reset(env);
307 env->halted = 0;
308 }
309
310 static void secondary_cpu_reset(void *opaque)
311 {
312 CPUState *env = opaque;
313
314 cpu_reset(env);
315 env->halted = 1;
316 }
317
318 static unsigned long sun4m_load_kernel(const char *kernel_filename,
319 const char *kernel_cmdline,
320 const char *initrd_filename)
321 {
322 int linux_boot;
323 unsigned int i;
324 long initrd_size, kernel_size;
325
326 linux_boot = (kernel_filename != NULL);
327
328 kernel_size = 0;
329 if (linux_boot) {
330 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
331 NULL);
332 if (kernel_size < 0)
333 kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
334 if (kernel_size < 0)
335 kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
336 if (kernel_size < 0) {
337 fprintf(stderr, "qemu: could not load kernel '%s'\n",
338 kernel_filename);
339 exit(1);
340 }
341
342 /* load initrd */
343 initrd_size = 0;
344 if (initrd_filename) {
345 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
346 if (initrd_size < 0) {
347 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
348 initrd_filename);
349 exit(1);
350 }
351 }
352 if (initrd_size > 0) {
353 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
354 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
355 == 0x48647253) { // HdrS
356 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
357 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
358 break;
359 }
360 }
361 }
362 }
363 return kernel_size;
364 }
365
366 static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
367 const char *boot_device,
368 DisplayState *ds, const char *kernel_filename,
369 const char *kernel_cmdline,
370 const char *initrd_filename, const char *cpu_model)
371
372 {
373 CPUState *env, *envs[MAX_CPUS];
374 unsigned int i;
375 void *iommu, *espdma, *ledma, *main_esp, *nvram;
376 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
377 *espdma_irq, *ledma_irq;
378 qemu_irq *esp_reset, *le_reset;
379 qemu_irq *fdc_tc;
380 unsigned long prom_offset, kernel_size;
381 int ret;
382 char buf[1024];
383 BlockDriverState *fd[MAX_FD];
384 int index;
385
386 /* init CPUs */
387 if (!cpu_model)
388 cpu_model = hwdef->default_cpu_model;
389
390 for(i = 0; i < smp_cpus; i++) {
391 env = cpu_init(cpu_model);
392 if (!env) {
393 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
394 exit(1);
395 }
396 cpu_sparc_set_id(env, i);
397 envs[i] = env;
398 if (i == 0) {
399 qemu_register_reset(main_cpu_reset, env);
400 } else {
401 qemu_register_reset(secondary_cpu_reset, env);
402 env->halted = 1;
403 }
404 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
405 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
406 env->prom_addr = hwdef->slavio_base;
407 }
408
409 for (i = smp_cpus; i < MAX_CPUS; i++)
410 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
411
412
413 /* allocate RAM */
414 if ((uint64_t)RAM_size > hwdef->max_mem) {
415 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
416 (unsigned int)RAM_size / (1024 * 1024),
417 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
418 exit(1);
419 }
420 cpu_register_physical_memory(0, RAM_size, 0);
421
422 /* load boot prom */
423 prom_offset = RAM_size + hwdef->vram_size;
424 cpu_register_physical_memory(hwdef->slavio_base,
425 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
426 TARGET_PAGE_MASK,
427 prom_offset | IO_MEM_ROM);
428
429 if (bios_name == NULL)
430 bios_name = PROM_FILENAME;
431 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
432 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
433 if (ret < 0 || ret > PROM_SIZE_MAX)
434 ret = load_image(buf, phys_ram_base + prom_offset);
435 if (ret < 0 || ret > PROM_SIZE_MAX) {
436 fprintf(stderr, "qemu: could not load prom '%s'\n",
437 buf);
438 exit(1);
439 }
440 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
441
442 /* set up devices */
443 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
444 hwdef->intctl_base + 0x10000ULL,
445 &hwdef->intbit_to_level[0],
446 &slavio_irq, &slavio_cpu_irq,
447 cpu_irqs,
448 hwdef->clock_irq);
449
450 if (hwdef->idreg_base != (target_phys_addr_t)-1) {
451 stl_raw(phys_ram_base + prom_offset, 0xfe810103);
452
453 cpu_register_physical_memory(hwdef->idreg_base, sizeof(uint32_t),
454 prom_offset | IO_MEM_ROM);
455 }
456
457 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
458 slavio_irq[hwdef->me_irq]);
459
460 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
461 iommu, &espdma_irq, &esp_reset);
462
463 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
464 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
465 &le_reset);
466
467 if (graphic_depth != 8 && graphic_depth != 24) {
468 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
469 exit (1);
470 }
471 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
472 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
473
474 if (nd_table[0].model == NULL
475 || strcmp(nd_table[0].model, "lance") == 0) {
476 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
477 } else if (strcmp(nd_table[0].model, "?") == 0) {
478 fprintf(stderr, "qemu: Supported NICs: lance\n");
479 exit (1);
480 } else {
481 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
482 exit (1);
483 }
484
485 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
486 hwdef->nvram_size, 8);
487
488 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
489 slavio_cpu_irq, smp_cpus);
490
491 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
492 nographic);
493 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
494 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
495 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
496 serial_hds[1], serial_hds[0]);
497
498 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
499 hwdef->aux1_base, hwdef->aux2_base,
500 slavio_irq[hwdef->me_irq], envs[0],
501 &fdc_tc);
502
503 if (hwdef->fd_base != (target_phys_addr_t)-1) {
504 /* there is zero or one floppy drive */
505 memset(fd, 0, sizeof(fd));
506 index = drive_get_index(IF_FLOPPY, 0, 0);
507 if (index != -1)
508 fd[0] = drives_table[index].bdrv;
509
510 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
511 fdc_tc);
512 }
513
514 if (drive_get_max_bus(IF_SCSI) > 0) {
515 fprintf(stderr, "qemu: too many SCSI bus\n");
516 exit(1);
517 }
518
519 main_esp = esp_init(hwdef->esp_base, 2,
520 espdma_memory_read, espdma_memory_write,
521 espdma, *espdma_irq, esp_reset);
522
523 for (i = 0; i < ESP_MAX_DEVS; i++) {
524 index = drive_get_index(IF_SCSI, 0, i);
525 if (index == -1)
526 continue;
527 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
528 }
529
530 if (hwdef->cs_base != (target_phys_addr_t)-1)
531 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
532
533 kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
534 initrd_filename);
535
536 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
537 boot_device, RAM_size, kernel_size, graphic_width,
538 graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
539
540 if (hwdef->ecc_base != (target_phys_addr_t)-1)
541 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
542 hwdef->ecc_version);
543 }
544
545 static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
546 const char *boot_device,
547 DisplayState *ds, const char *kernel_filename,
548 const char *kernel_cmdline,
549 const char *initrd_filename, const char *cpu_model)
550 {
551 CPUState *env;
552 unsigned int i;
553 void *iommu, *espdma, *ledma, *main_esp, *nvram;
554 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
555 qemu_irq *esp_reset, *le_reset;
556 qemu_irq *fdc_tc;
557 unsigned long prom_offset, kernel_size;
558 int ret;
559 char buf[1024];
560 BlockDriverState *fd[MAX_FD];
561 int index;
562
563 /* init CPU */
564 if (!cpu_model)
565 cpu_model = hwdef->default_cpu_model;
566
567 env = cpu_init(cpu_model);
568 if (!env) {
569 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
570 exit(1);
571 }
572
573 cpu_sparc_set_id(env, 0);
574
575 qemu_register_reset(main_cpu_reset, env);
576 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
577 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
578 env->prom_addr = hwdef->slavio_base;
579
580 /* allocate RAM */
581 if ((uint64_t)RAM_size > hwdef->max_mem) {
582 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
583 (unsigned int)RAM_size / (1024 * 1024),
584 (unsigned int)hwdef->max_mem / (1024 * 1024));
585 exit(1);
586 }
587 cpu_register_physical_memory(0, RAM_size, 0);
588
589 /* load boot prom */
590 prom_offset = RAM_size + hwdef->vram_size;
591 cpu_register_physical_memory(hwdef->slavio_base,
592 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
593 TARGET_PAGE_MASK,
594 prom_offset | IO_MEM_ROM);
595
596 if (bios_name == NULL)
597 bios_name = PROM_FILENAME;
598 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
599 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
600 if (ret < 0 || ret > PROM_SIZE_MAX)
601 ret = load_image(buf, phys_ram_base + prom_offset);
602 if (ret < 0 || ret > PROM_SIZE_MAX) {
603 fprintf(stderr, "qemu: could not load prom '%s'\n",
604 buf);
605 exit(1);
606 }
607 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
608
609 /* set up devices */
610 slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
611 &slavio_irq, cpu_irqs);
612
613 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
614 slavio_irq[hwdef->me_irq]);
615
616 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
617 iommu, &espdma_irq, &esp_reset);
618
619 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
620 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
621 &le_reset);
622
623 if (graphic_depth != 8 && graphic_depth != 24) {
624 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
625 exit (1);
626 }
627 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
628 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
629
630 if (nd_table[0].model == NULL
631 || strcmp(nd_table[0].model, "lance") == 0) {
632 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
633 } else if (strcmp(nd_table[0].model, "?") == 0) {
634 fprintf(stderr, "qemu: Supported NICs: lance\n");
635 exit (1);
636 } else {
637 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
638 exit (1);
639 }
640
641 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
642 hwdef->nvram_size, 2);
643
644 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
645 nographic);
646 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
647 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
648 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
649 serial_hds[1], serial_hds[0]);
650
651 slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
652 hwdef->aux1_base, hwdef->aux2_base,
653 slavio_irq[hwdef->me_irq], env, &fdc_tc);
654
655 if (hwdef->fd_base != (target_phys_addr_t)-1) {
656 /* there is zero or one floppy drive */
657 fd[1] = fd[0] = NULL;
658 index = drive_get_index(IF_FLOPPY, 0, 0);
659 if (index != -1)
660 fd[0] = drives_table[index].bdrv;
661
662 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
663 fdc_tc);
664 }
665
666 if (drive_get_max_bus(IF_SCSI) > 0) {
667 fprintf(stderr, "qemu: too many SCSI bus\n");
668 exit(1);
669 }
670
671 main_esp = esp_init(hwdef->esp_base, 2,
672 espdma_memory_read, espdma_memory_write,
673 espdma, *espdma_irq, esp_reset);
674
675 for (i = 0; i < ESP_MAX_DEVS; i++) {
676 index = drive_get_index(IF_SCSI, 0, i);
677 if (index == -1)
678 continue;
679 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
680 }
681
682 kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
683 initrd_filename);
684
685 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
686 boot_device, RAM_size, kernel_size, graphic_width,
687 graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
688 }
689
690 static const struct hwdef hwdefs[] = {
691 /* SS-5 */
692 {
693 .iommu_base = 0x10000000,
694 .tcx_base = 0x50000000,
695 .cs_base = 0x6c000000,
696 .slavio_base = 0x70000000,
697 .ms_kb_base = 0x71000000,
698 .serial_base = 0x71100000,
699 .nvram_base = 0x71200000,
700 .fd_base = 0x71400000,
701 .counter_base = 0x71d00000,
702 .intctl_base = 0x71e00000,
703 .idreg_base = 0x78000000,
704 .dma_base = 0x78400000,
705 .esp_base = 0x78800000,
706 .le_base = 0x78c00000,
707 .apc_base = 0x6a000000,
708 .aux1_base = 0x71900000,
709 .aux2_base = 0x71910000,
710 .ecc_base = -1,
711 .sun4c_intctl_base = -1,
712 .sun4c_counter_base = -1,
713 .vram_size = 0x00100000,
714 .nvram_size = 0x2000,
715 .esp_irq = 18,
716 .le_irq = 16,
717 .clock_irq = 7,
718 .clock1_irq = 19,
719 .ms_kb_irq = 14,
720 .ser_irq = 15,
721 .fd_irq = 22,
722 .me_irq = 30,
723 .cs_irq = 5,
724 .machine_id = 0x80,
725 .iommu_version = 0x05000000,
726 .intbit_to_level = {
727 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
728 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
729 },
730 .max_mem = 0x10000000,
731 .default_cpu_model = "Fujitsu MB86904",
732 },
733 /* SS-10 */
734 {
735 .iommu_base = 0xfe0000000ULL,
736 .tcx_base = 0xe20000000ULL,
737 .cs_base = -1,
738 .slavio_base = 0xff0000000ULL,
739 .ms_kb_base = 0xff1000000ULL,
740 .serial_base = 0xff1100000ULL,
741 .nvram_base = 0xff1200000ULL,
742 .fd_base = 0xff1700000ULL,
743 .counter_base = 0xff1300000ULL,
744 .intctl_base = 0xff1400000ULL,
745 .idreg_base = 0xef0000000ULL,
746 .dma_base = 0xef0400000ULL,
747 .esp_base = 0xef0800000ULL,
748 .le_base = 0xef0c00000ULL,
749 .apc_base = 0xefa000000ULL, // XXX should not exist
750 .aux1_base = 0xff1800000ULL,
751 .aux2_base = 0xff1a01000ULL,
752 .ecc_base = 0xf00000000ULL,
753 .ecc_version = 0x10000000, // version 0, implementation 1
754 .sun4c_intctl_base = -1,
755 .sun4c_counter_base = -1,
756 .vram_size = 0x00100000,
757 .nvram_size = 0x2000,
758 .esp_irq = 18,
759 .le_irq = 16,
760 .clock_irq = 7,
761 .clock1_irq = 19,
762 .ms_kb_irq = 14,
763 .ser_irq = 15,
764 .fd_irq = 22,
765 .me_irq = 30,
766 .cs_irq = -1,
767 .ecc_irq = 28,
768 .machine_id = 0x72,
769 .iommu_version = 0x03000000,
770 .intbit_to_level = {
771 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
772 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
773 },
774 .max_mem = 0xffffffff, // XXX actually first 62GB ok
775 .default_cpu_model = "TI SuperSparc II",
776 },
777 /* SS-600MP */
778 {
779 .iommu_base = 0xfe0000000ULL,
780 .tcx_base = 0xe20000000ULL,
781 .cs_base = -1,
782 .slavio_base = 0xff0000000ULL,
783 .ms_kb_base = 0xff1000000ULL,
784 .serial_base = 0xff1100000ULL,
785 .nvram_base = 0xff1200000ULL,
786 .fd_base = -1,
787 .counter_base = 0xff1300000ULL,
788 .intctl_base = 0xff1400000ULL,
789 .idreg_base = -1,
790 .dma_base = 0xef0081000ULL,
791 .esp_base = 0xef0080000ULL,
792 .le_base = 0xef0060000ULL,
793 .apc_base = 0xefa000000ULL, // XXX should not exist
794 .aux1_base = 0xff1800000ULL,
795 .aux2_base = 0xff1a01000ULL, // XXX should not exist
796 .ecc_base = 0xf00000000ULL,
797 .ecc_version = 0x00000000, // version 0, implementation 0
798 .sun4c_intctl_base = -1,
799 .sun4c_counter_base = -1,
800 .vram_size = 0x00100000,
801 .nvram_size = 0x2000,
802 .esp_irq = 18,
803 .le_irq = 16,
804 .clock_irq = 7,
805 .clock1_irq = 19,
806 .ms_kb_irq = 14,
807 .ser_irq = 15,
808 .fd_irq = 22,
809 .me_irq = 30,
810 .cs_irq = -1,
811 .ecc_irq = 28,
812 .machine_id = 0x71,
813 .iommu_version = 0x01000000,
814 .intbit_to_level = {
815 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
816 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
817 },
818 .max_mem = 0xffffffff, // XXX actually first 62GB ok
819 .default_cpu_model = "TI SuperSparc II",
820 },
821 /* SS-20 */
822 {
823 .iommu_base = 0xfe0000000ULL,
824 .tcx_base = 0xe20000000ULL,
825 .cs_base = -1,
826 .slavio_base = 0xff0000000ULL,
827 .ms_kb_base = 0xff1000000ULL,
828 .serial_base = 0xff1100000ULL,
829 .nvram_base = 0xff1200000ULL,
830 .fd_base = 0xff1700000ULL,
831 .counter_base = 0xff1300000ULL,
832 .intctl_base = 0xff1400000ULL,
833 .idreg_base = 0xef0000000ULL,
834 .dma_base = 0xef0400000ULL,
835 .esp_base = 0xef0800000ULL,
836 .le_base = 0xef0c00000ULL,
837 .apc_base = 0xefa000000ULL, // XXX should not exist
838 .aux1_base = 0xff1800000ULL,
839 .aux2_base = 0xff1a01000ULL,
840 .ecc_base = 0xf00000000ULL,
841 .ecc_version = 0x20000000, // version 0, implementation 2
842 .sun4c_intctl_base = -1,
843 .sun4c_counter_base = -1,
844 .vram_size = 0x00100000,
845 .nvram_size = 0x2000,
846 .esp_irq = 18,
847 .le_irq = 16,
848 .clock_irq = 7,
849 .clock1_irq = 19,
850 .ms_kb_irq = 14,
851 .ser_irq = 15,
852 .fd_irq = 22,
853 .me_irq = 30,
854 .cs_irq = -1,
855 .ecc_irq = 28,
856 .machine_id = 0x72,
857 .iommu_version = 0x13000000,
858 .intbit_to_level = {
859 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
860 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
861 },
862 .max_mem = 0xffffffff, // XXX actually first 62GB ok
863 .default_cpu_model = "TI SuperSparc II",
864 },
865 /* SS-2 */
866 {
867 .iommu_base = 0xf8000000,
868 .tcx_base = 0xfe000000,
869 .cs_base = -1,
870 .slavio_base = 0xf6000000,
871 .ms_kb_base = 0xf0000000,
872 .serial_base = 0xf1000000,
873 .nvram_base = 0xf2000000,
874 .fd_base = 0xf7200000,
875 .counter_base = -1,
876 .intctl_base = -1,
877 .dma_base = 0xf8400000,
878 .esp_base = 0xf8800000,
879 .le_base = 0xf8c00000,
880 .apc_base = -1,
881 .aux1_base = 0xf7400003,
882 .aux2_base = -1,
883 .sun4c_intctl_base = 0xf5000000,
884 .sun4c_counter_base = 0xf3000000,
885 .vram_size = 0x00100000,
886 .nvram_size = 0x800,
887 .esp_irq = 2,
888 .le_irq = 3,
889 .clock_irq = 5,
890 .clock1_irq = 7,
891 .ms_kb_irq = 1,
892 .ser_irq = 1,
893 .fd_irq = 1,
894 .me_irq = 1,
895 .cs_irq = -1,
896 .machine_id = 0x55,
897 .max_mem = 0x10000000,
898 .default_cpu_model = "Cypress CY7C601",
899 },
900 /* Voyager */
901 {
902 .iommu_base = 0x10000000,
903 .tcx_base = 0x50000000,
904 .cs_base = -1,
905 .slavio_base = 0x70000000,
906 .ms_kb_base = 0x71000000,
907 .serial_base = 0x71100000,
908 .nvram_base = 0x71200000,
909 .fd_base = 0x71400000,
910 .counter_base = 0x71d00000,
911 .intctl_base = 0x71e00000,
912 .idreg_base = 0x78000000,
913 .dma_base = 0x78400000,
914 .esp_base = 0x78800000,
915 .le_base = 0x78c00000,
916 .apc_base = 0x71300000, // pmc
917 .aux1_base = 0x71900000,
918 .aux2_base = 0x71910000,
919 .ecc_base = -1,
920 .sun4c_intctl_base = -1,
921 .sun4c_counter_base = -1,
922 .vram_size = 0x00100000,
923 .nvram_size = 0x2000,
924 .esp_irq = 18,
925 .le_irq = 16,
926 .clock_irq = 7,
927 .clock1_irq = 19,
928 .ms_kb_irq = 14,
929 .ser_irq = 15,
930 .fd_irq = 22,
931 .me_irq = 30,
932 .cs_irq = -1,
933 .machine_id = 0x80,
934 .iommu_version = 0x05000000,
935 .intbit_to_level = {
936 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
937 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
938 },
939 .max_mem = 0x10000000,
940 .default_cpu_model = "Fujitsu MB86904",
941 },
942 /* LX */
943 {
944 .iommu_base = 0x10000000,
945 .tcx_base = 0x50000000,
946 .cs_base = -1,
947 .slavio_base = 0x70000000,
948 .ms_kb_base = 0x71000000,
949 .serial_base = 0x71100000,
950 .nvram_base = 0x71200000,
951 .fd_base = 0x71400000,
952 .counter_base = 0x71d00000,
953 .intctl_base = 0x71e00000,
954 .idreg_base = 0x78000000,
955 .dma_base = 0x78400000,
956 .esp_base = 0x78800000,
957 .le_base = 0x78c00000,
958 .apc_base = -1,
959 .aux1_base = 0x71900000,
960 .aux2_base = 0x71910000,
961 .ecc_base = -1,
962 .sun4c_intctl_base = -1,
963 .sun4c_counter_base = -1,
964 .vram_size = 0x00100000,
965 .nvram_size = 0x2000,
966 .esp_irq = 18,
967 .le_irq = 16,
968 .clock_irq = 7,
969 .clock1_irq = 19,
970 .ms_kb_irq = 14,
971 .ser_irq = 15,
972 .fd_irq = 22,
973 .me_irq = 30,
974 .cs_irq = -1,
975 .machine_id = 0x80,
976 .iommu_version = 0x04000000,
977 .intbit_to_level = {
978 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
979 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
980 },
981 .max_mem = 0x10000000,
982 .default_cpu_model = "TI MicroSparc I",
983 },
984 /* SS-4 */
985 {
986 .iommu_base = 0x10000000,
987 .tcx_base = 0x50000000,
988 .cs_base = 0x6c000000,
989 .slavio_base = 0x70000000,
990 .ms_kb_base = 0x71000000,
991 .serial_base = 0x71100000,
992 .nvram_base = 0x71200000,
993 .fd_base = 0x71400000,
994 .counter_base = 0x71d00000,
995 .intctl_base = 0x71e00000,
996 .idreg_base = 0x78000000,
997 .dma_base = 0x78400000,
998 .esp_base = 0x78800000,
999 .le_base = 0x78c00000,
1000 .apc_base = 0x6a000000,
1001 .aux1_base = 0x71900000,
1002 .aux2_base = 0x71910000,
1003 .ecc_base = -1,
1004 .sun4c_intctl_base = -1,
1005 .sun4c_counter_base = -1,
1006 .vram_size = 0x00100000,
1007 .nvram_size = 0x2000,
1008 .esp_irq = 18,
1009 .le_irq = 16,
1010 .clock_irq = 7,
1011 .clock1_irq = 19,
1012 .ms_kb_irq = 14,
1013 .ser_irq = 15,
1014 .fd_irq = 22,
1015 .me_irq = 30,
1016 .cs_irq = 5,
1017 .machine_id = 0x80,
1018 .iommu_version = 0x05000000,
1019 .intbit_to_level = {
1020 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1021 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1022 },
1023 .max_mem = 0x10000000,
1024 .default_cpu_model = "Fujitsu MB86904",
1025 },
1026 /* SPARCClassic */
1027 {
1028 .iommu_base = 0x10000000,
1029 .tcx_base = 0x50000000,
1030 .cs_base = -1,
1031 .slavio_base = 0x70000000,
1032 .ms_kb_base = 0x71000000,
1033 .serial_base = 0x71100000,
1034 .nvram_base = 0x71200000,
1035 .fd_base = 0x71400000,
1036 .counter_base = 0x71d00000,
1037 .intctl_base = 0x71e00000,
1038 .idreg_base = 0x78000000,
1039 .dma_base = 0x78400000,
1040 .esp_base = 0x78800000,
1041 .le_base = 0x78c00000,
1042 .apc_base = 0x6a000000,
1043 .aux1_base = 0x71900000,
1044 .aux2_base = 0x71910000,
1045 .ecc_base = -1,
1046 .sun4c_intctl_base = -1,
1047 .sun4c_counter_base = -1,
1048 .vram_size = 0x00100000,
1049 .nvram_size = 0x2000,
1050 .esp_irq = 18,
1051 .le_irq = 16,
1052 .clock_irq = 7,
1053 .clock1_irq = 19,
1054 .ms_kb_irq = 14,
1055 .ser_irq = 15,
1056 .fd_irq = 22,
1057 .me_irq = 30,
1058 .cs_irq = -1,
1059 .machine_id = 0x80,
1060 .iommu_version = 0x05000000,
1061 .intbit_to_level = {
1062 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1063 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1064 },
1065 .max_mem = 0x10000000,
1066 .default_cpu_model = "TI MicroSparc I",
1067 },
1068 /* SPARCbook */
1069 {
1070 .iommu_base = 0x10000000,
1071 .tcx_base = 0x50000000, // XXX
1072 .cs_base = -1,
1073 .slavio_base = 0x70000000,
1074 .ms_kb_base = 0x71000000,
1075 .serial_base = 0x71100000,
1076 .nvram_base = 0x71200000,
1077 .fd_base = 0x71400000,
1078 .counter_base = 0x71d00000,
1079 .intctl_base = 0x71e00000,
1080 .idreg_base = 0x78000000,
1081 .dma_base = 0x78400000,
1082 .esp_base = 0x78800000,
1083 .le_base = 0x78c00000,
1084 .apc_base = 0x6a000000,
1085 .aux1_base = 0x71900000,
1086 .aux2_base = 0x71910000,
1087 .ecc_base = -1,
1088 .sun4c_intctl_base = -1,
1089 .sun4c_counter_base = -1,
1090 .vram_size = 0x00100000,
1091 .nvram_size = 0x2000,
1092 .esp_irq = 18,
1093 .le_irq = 16,
1094 .clock_irq = 7,
1095 .clock1_irq = 19,
1096 .ms_kb_irq = 14,
1097 .ser_irq = 15,
1098 .fd_irq = 22,
1099 .me_irq = 30,
1100 .cs_irq = -1,
1101 .machine_id = 0x80,
1102 .iommu_version = 0x05000000,
1103 .intbit_to_level = {
1104 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1105 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1106 },
1107 .max_mem = 0x10000000,
1108 .default_cpu_model = "TI MicroSparc I",
1109 },
1110 };
1111
1112 /* SPARCstation 5 hardware initialisation */
1113 static void ss5_init(int RAM_size, int vga_ram_size,
1114 const char *boot_device, DisplayState *ds,
1115 const char *kernel_filename, const char *kernel_cmdline,
1116 const char *initrd_filename, const char *cpu_model)
1117 {
1118 sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1119 kernel_cmdline, initrd_filename, cpu_model);
1120 }
1121
1122 /* SPARCstation 10 hardware initialisation */
1123 static void ss10_init(int RAM_size, int vga_ram_size,
1124 const char *boot_device, DisplayState *ds,
1125 const char *kernel_filename, const char *kernel_cmdline,
1126 const char *initrd_filename, const char *cpu_model)
1127 {
1128 sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1129 kernel_cmdline, initrd_filename, cpu_model);
1130 }
1131
1132 /* SPARCserver 600MP hardware initialisation */
1133 static void ss600mp_init(int RAM_size, int vga_ram_size,
1134 const char *boot_device, DisplayState *ds,
1135 const char *kernel_filename, const char *kernel_cmdline,
1136 const char *initrd_filename, const char *cpu_model)
1137 {
1138 sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
1139 kernel_cmdline, initrd_filename, cpu_model);
1140 }
1141
1142 /* SPARCstation 20 hardware initialisation */
1143 static void ss20_init(int RAM_size, int vga_ram_size,
1144 const char *boot_device, DisplayState *ds,
1145 const char *kernel_filename, const char *kernel_cmdline,
1146 const char *initrd_filename, const char *cpu_model)
1147 {
1148 sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
1149 kernel_cmdline, initrd_filename, cpu_model);
1150 }
1151
1152 /* SPARCstation 2 hardware initialisation */
1153 static void ss2_init(int RAM_size, int vga_ram_size,
1154 const char *boot_device, DisplayState *ds,
1155 const char *kernel_filename, const char *kernel_cmdline,
1156 const char *initrd_filename, const char *cpu_model)
1157 {
1158 sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
1159 kernel_cmdline, initrd_filename, cpu_model);
1160 }
1161
1162 /* SPARCstation Voyager hardware initialisation */
1163 static void vger_init(int RAM_size, int vga_ram_size,
1164 const char *boot_device, DisplayState *ds,
1165 const char *kernel_filename, const char *kernel_cmdline,
1166 const char *initrd_filename, const char *cpu_model)
1167 {
1168 sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
1169 kernel_cmdline, initrd_filename, cpu_model);
1170 }
1171
1172 /* SPARCstation LX hardware initialisation */
1173 static void ss_lx_init(int RAM_size, int vga_ram_size,
1174 const char *boot_device, DisplayState *ds,
1175 const char *kernel_filename, const char *kernel_cmdline,
1176 const char *initrd_filename, const char *cpu_model)
1177 {
1178 sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
1179 kernel_cmdline, initrd_filename, cpu_model);
1180 }
1181
1182 /* SPARCstation 4 hardware initialisation */
1183 static void ss4_init(int RAM_size, int vga_ram_size,
1184 const char *boot_device, DisplayState *ds,
1185 const char *kernel_filename, const char *kernel_cmdline,
1186 const char *initrd_filename, const char *cpu_model)
1187 {
1188 sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
1189 kernel_cmdline, initrd_filename, cpu_model);
1190 }
1191
1192 /* SPARCClassic hardware initialisation */
1193 static void scls_init(int RAM_size, int vga_ram_size,
1194 const char *boot_device, DisplayState *ds,
1195 const char *kernel_filename, const char *kernel_cmdline,
1196 const char *initrd_filename, const char *cpu_model)
1197 {
1198 sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
1199 kernel_cmdline, initrd_filename, cpu_model);
1200 }
1201
1202 /* SPARCbook hardware initialisation */
1203 static void sbook_init(int RAM_size, int vga_ram_size,
1204 const char *boot_device, DisplayState *ds,
1205 const char *kernel_filename, const char *kernel_cmdline,
1206 const char *initrd_filename, const char *cpu_model)
1207 {
1208 sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
1209 kernel_cmdline, initrd_filename, cpu_model);
1210 }
1211
1212 QEMUMachine ss5_machine = {
1213 "SS-5",
1214 "Sun4m platform, SPARCstation 5",
1215 ss5_init,
1216 };
1217
1218 QEMUMachine ss10_machine = {
1219 "SS-10",
1220 "Sun4m platform, SPARCstation 10",
1221 ss10_init,
1222 };
1223
1224 QEMUMachine ss600mp_machine = {
1225 "SS-600MP",
1226 "Sun4m platform, SPARCserver 600MP",
1227 ss600mp_init,
1228 };
1229
1230 QEMUMachine ss20_machine = {
1231 "SS-20",
1232 "Sun4m platform, SPARCstation 20",
1233 ss20_init,
1234 };
1235
1236 QEMUMachine ss2_machine = {
1237 "SS-2",
1238 "Sun4c platform, SPARCstation 2",
1239 ss2_init,
1240 };
1241
1242 QEMUMachine voyager_machine = {
1243 "Voyager",
1244 "Sun4m platform, SPARCstation Voyager",
1245 vger_init,
1246 };
1247
1248 QEMUMachine ss_lx_machine = {
1249 "LX",
1250 "Sun4m platform, SPARCstation LX",
1251 ss_lx_init,
1252 };
1253
1254 QEMUMachine ss4_machine = {
1255 "SS-4",
1256 "Sun4m platform, SPARCstation 4",
1257 ss4_init,
1258 };
1259
1260 QEMUMachine scls_machine = {
1261 "SPARCClassic",
1262 "Sun4m platform, SPARCClassic",
1263 scls_init,
1264 };
1265
1266 QEMUMachine sbook_machine = {
1267 "SPARCbook",
1268 "Sun4m platform, SPARCbook",
1269 sbook_init,
1270 };
1271
1272 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1273 /* SS-1000 */
1274 {
1275 .iounit_bases = {
1276 0xfe0200000ULL,
1277 0xfe1200000ULL,
1278 0xfe2200000ULL,
1279 0xfe3200000ULL,
1280 -1,
1281 },
1282 .tcx_base = 0x820000000ULL,
1283 .slavio_base = 0xf00000000ULL,
1284 .ms_kb_base = 0xf00240000ULL,
1285 .serial_base = 0xf00200000ULL,
1286 .nvram_base = 0xf00280000ULL,
1287 .counter_base = 0xf00300000ULL,
1288 .espdma_base = 0x800081000ULL,
1289 .esp_base = 0x800080000ULL,
1290 .ledma_base = 0x800040000ULL,
1291 .le_base = 0x800060000ULL,
1292 .sbi_base = 0xf02800000ULL,
1293 .vram_size = 0x00100000,
1294 .nvram_size = 0x2000,
1295 .esp_irq = 3,
1296 .le_irq = 4,
1297 .clock_irq = 14,
1298 .clock1_irq = 10,
1299 .ms_kb_irq = 12,
1300 .ser_irq = 12,
1301 .machine_id = 0x80,
1302 .iounit_version = 0x03000000,
1303 .max_mem = 0xffffffff, // XXX actually first 62GB ok
1304 .default_cpu_model = "TI SuperSparc II",
1305 },
1306 /* SS-2000 */
1307 {
1308 .iounit_bases = {
1309 0xfe0200000ULL,
1310 0xfe1200000ULL,
1311 0xfe2200000ULL,
1312 0xfe3200000ULL,
1313 0xfe4200000ULL,
1314 },
1315 .tcx_base = 0x820000000ULL,
1316 .slavio_base = 0xf00000000ULL,
1317 .ms_kb_base = 0xf00240000ULL,
1318 .serial_base = 0xf00200000ULL,
1319 .nvram_base = 0xf00280000ULL,
1320 .counter_base = 0xf00300000ULL,
1321 .espdma_base = 0x800081000ULL,
1322 .esp_base = 0x800080000ULL,
1323 .ledma_base = 0x800040000ULL,
1324 .le_base = 0x800060000ULL,
1325 .sbi_base = 0xf02800000ULL,
1326 .vram_size = 0x00100000,
1327 .nvram_size = 0x2000,
1328 .esp_irq = 3,
1329 .le_irq = 4,
1330 .clock_irq = 14,
1331 .clock1_irq = 10,
1332 .ms_kb_irq = 12,
1333 .ser_irq = 12,
1334 .machine_id = 0x80,
1335 .iounit_version = 0x03000000,
1336 .max_mem = 0xffffffff, // XXX actually first 62GB ok
1337 .default_cpu_model = "TI SuperSparc II",
1338 },
1339 };
1340
1341 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, int RAM_size,
1342 const char *boot_device,
1343 DisplayState *ds, const char *kernel_filename,
1344 const char *kernel_cmdline,
1345 const char *initrd_filename, const char *cpu_model)
1346 {
1347 CPUState *env, *envs[MAX_CPUS];
1348 unsigned int i;
1349 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1350 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1351 *espdma_irq, *ledma_irq;
1352 qemu_irq *esp_reset, *le_reset;
1353 unsigned long prom_offset, kernel_size;
1354 int ret;
1355 char buf[1024];
1356 int index;
1357
1358 /* init CPUs */
1359 if (!cpu_model)
1360 cpu_model = hwdef->default_cpu_model;
1361
1362 for (i = 0; i < smp_cpus; i++) {
1363 env = cpu_init(cpu_model);
1364 if (!env) {
1365 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1366 exit(1);
1367 }
1368 cpu_sparc_set_id(env, i);
1369 envs[i] = env;
1370 if (i == 0) {
1371 qemu_register_reset(main_cpu_reset, env);
1372 } else {
1373 qemu_register_reset(secondary_cpu_reset, env);
1374 env->halted = 1;
1375 }
1376 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
1377 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1378 env->prom_addr = hwdef->slavio_base;
1379 }
1380
1381 for (i = smp_cpus; i < MAX_CPUS; i++)
1382 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1383
1384 /* allocate RAM */
1385 if ((uint64_t)RAM_size > hwdef->max_mem) {
1386 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
1387 (unsigned int)RAM_size / (1024 * 1024),
1388 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1389 exit(1);
1390 }
1391 cpu_register_physical_memory(0, RAM_size, 0);
1392
1393 /* load boot prom */
1394 prom_offset = RAM_size + hwdef->vram_size;
1395 cpu_register_physical_memory(hwdef->slavio_base,
1396 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1397 TARGET_PAGE_MASK,
1398 prom_offset | IO_MEM_ROM);
1399
1400 if (bios_name == NULL)
1401 bios_name = PROM_FILENAME;
1402 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1403 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1404 if (ret < 0 || ret > PROM_SIZE_MAX)
1405 ret = load_image(buf, phys_ram_base + prom_offset);
1406 if (ret < 0 || ret > PROM_SIZE_MAX) {
1407 fprintf(stderr, "qemu: could not load prom '%s'\n",
1408 buf);
1409 exit(1);
1410 }
1411
1412 /* set up devices */
1413 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1414
1415 for (i = 0; i < MAX_IOUNITS; i++)
1416 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1417 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1418 hwdef->iounit_version,
1419 sbi_irq[hwdef->me_irq]);
1420
1421 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1422 iounits[0], &espdma_irq, &esp_reset);
1423
1424 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1425 iounits[0], &ledma_irq, &le_reset);
1426
1427 if (graphic_depth != 8 && graphic_depth != 24) {
1428 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1429 exit (1);
1430 }
1431 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1432 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1433
1434 if (nd_table[0].model == NULL
1435 || strcmp(nd_table[0].model, "lance") == 0) {
1436 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1437 } else if (strcmp(nd_table[0].model, "?") == 0) {
1438 fprintf(stderr, "qemu: Supported NICs: lance\n");
1439 exit (1);
1440 } else {
1441 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1442 exit (1);
1443 }
1444
1445 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1446 hwdef->nvram_size, 8);
1447
1448 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1449 sbi_cpu_irq, smp_cpus);
1450
1451 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1452 nographic);
1453 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1454 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1455 slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1456 serial_hds[1], serial_hds[0]);
1457
1458 if (drive_get_max_bus(IF_SCSI) > 0) {
1459 fprintf(stderr, "qemu: too many SCSI bus\n");
1460 exit(1);
1461 }
1462
1463 main_esp = esp_init(hwdef->esp_base, 2,
1464 espdma_memory_read, espdma_memory_write,
1465 espdma, *espdma_irq, esp_reset);
1466
1467 for (i = 0; i < ESP_MAX_DEVS; i++) {
1468 index = drive_get_index(IF_SCSI, 0, i);
1469 if (index == -1)
1470 continue;
1471 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
1472 }
1473
1474 kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
1475 initrd_filename);
1476
1477 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1478 boot_device, RAM_size, kernel_size, graphic_width,
1479 graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
1480 }
1481
1482 /* SPARCserver 1000 hardware initialisation */
1483 static void ss1000_init(int RAM_size, int vga_ram_size,
1484 const char *boot_device, DisplayState *ds,
1485 const char *kernel_filename, const char *kernel_cmdline,
1486 const char *initrd_filename, const char *cpu_model)
1487 {
1488 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1489 kernel_cmdline, initrd_filename, cpu_model);
1490 }
1491
1492 /* SPARCcenter 2000 hardware initialisation */
1493 static void ss2000_init(int RAM_size, int vga_ram_size,
1494 const char *boot_device, DisplayState *ds,
1495 const char *kernel_filename, const char *kernel_cmdline,
1496 const char *initrd_filename, const char *cpu_model)
1497 {
1498 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1499 kernel_cmdline, initrd_filename, cpu_model);
1500 }
1501
1502 QEMUMachine ss1000_machine = {
1503 "SS-1000",
1504 "Sun4d platform, SPARCserver 1000",
1505 ss1000_init,
1506 };
1507
1508 QEMUMachine ss2000_machine = {
1509 "SS-2000",
1510 "Sun4d platform, SPARCcenter 2000",
1511 ss2000_init,
1512 };
Qemu copy for testing