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Sparc32: convert slavio_misc to qdev
[mirror_qemu.git] / hw / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39
40 //#define DEBUG_IRQ
41
42 /*
43 * Sun4m architecture was used in the following machines:
44 *
45 * SPARCserver 6xxMP/xx
46 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
47 * SPARCclassic X (4/10)
48 * SPARCstation LX/ZX (4/30)
49 * SPARCstation Voyager
50 * SPARCstation 10/xx, SPARCserver 10/xx
51 * SPARCstation 5, SPARCserver 5
52 * SPARCstation 20/xx, SPARCserver 20
53 * SPARCstation 4
54 *
55 * Sun4d architecture was used in the following machines:
56 *
57 * SPARCcenter 2000
58 * SPARCserver 1000
59 *
60 * Sun4c architecture was used in the following machines:
61 * SPARCstation 1/1+, SPARCserver 1/1+
62 * SPARCstation SLC
63 * SPARCstation IPC
64 * SPARCstation ELC
65 * SPARCstation IPX
66 *
67 * See for example: http://www.sunhelp.org/faq/sunref1.html
68 */
69
70 #ifdef DEBUG_IRQ
71 #define DPRINTF(fmt, ...) \
72 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
73 #else
74 #define DPRINTF(fmt, ...)
75 #endif
76
77 #define KERNEL_LOAD_ADDR 0x00004000
78 #define CMDLINE_ADDR 0x007ff000
79 #define INITRD_LOAD_ADDR 0x00800000
80 #define PROM_SIZE_MAX (1024 * 1024)
81 #define PROM_VADDR 0xffd00000
82 #define PROM_FILENAME "openbios-sparc32"
83 #define CFG_ADDR 0xd00000510ULL
84 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
85
86 #define MAX_CPUS 16
87 #define MAX_PILS 16
88
89 #define ESCC_CLOCK 4915200
90
91 struct sun4m_hwdef {
92 target_phys_addr_t iommu_base, slavio_base;
93 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94 target_phys_addr_t serial_base, fd_base;
95 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
96 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 target_phys_addr_t ecc_base;
98 uint32_t ecc_version;
99 long vram_size, nvram_size;
100 // IRQ numbers are not PIL ones, but master interrupt controller
101 // register bit numbers
102 int esp_irq, le_irq, clock_irq, clock1_irq;
103 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104 uint8_t nvram_machine_id;
105 uint16_t machine_id;
106 uint32_t iommu_version;
107 uint32_t intbit_to_level[32];
108 uint64_t max_mem;
109 const char * const default_cpu_model;
110 };
111
112 #define MAX_IOUNITS 5
113
114 struct sun4d_hwdef {
115 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117 target_phys_addr_t serial_base;
118 target_phys_addr_t espdma_base, esp_base;
119 target_phys_addr_t ledma_base, le_base;
120 target_phys_addr_t tcx_base;
121 target_phys_addr_t sbi_base;
122 unsigned long vram_size, nvram_size;
123 // IRQ numbers are not PIL ones, but SBI register bit numbers
124 int esp_irq, le_irq, clock_irq, clock1_irq;
125 int ser_irq, ms_kb_irq, me_irq;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 struct sun4c_hwdef {
134 target_phys_addr_t iommu_base, slavio_base;
135 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136 target_phys_addr_t serial_base, fd_base;
137 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138 target_phys_addr_t tcx_base, aux1_base;
139 long vram_size, nvram_size;
140 // IRQ numbers are not PIL ones, but master interrupt controller
141 // register bit numbers
142 int esp_irq, le_irq, clock_irq, clock1_irq;
143 int ser_irq, ms_kb_irq, fd_irq, me_irq;
144 uint8_t nvram_machine_id;
145 uint16_t machine_id;
146 uint32_t iommu_version;
147 uint32_t intbit_to_level[32];
148 uint64_t max_mem;
149 const char * const default_cpu_model;
150 };
151
152 int DMA_get_channel_mode (int nchan)
153 {
154 return 0;
155 }
156 int DMA_read_memory (int nchan, void *buf, int pos, int size)
157 {
158 return 0;
159 }
160 int DMA_write_memory (int nchan, void *buf, int pos, int size)
161 {
162 return 0;
163 }
164 void DMA_hold_DREQ (int nchan) {}
165 void DMA_release_DREQ (int nchan) {}
166 void DMA_schedule(int nchan) {}
167 void DMA_init (int high_page_enable) {}
168 void DMA_register_channel (int nchan,
169 DMA_transfer_handler transfer_handler,
170 void *opaque)
171 {
172 }
173
174 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
175 {
176 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
177 return 0;
178 }
179
180 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
181 const char *boot_devices, ram_addr_t RAM_size,
182 uint32_t kernel_size,
183 int width, int height, int depth,
184 int nvram_machine_id, const char *arch)
185 {
186 unsigned int i;
187 uint32_t start, end;
188 uint8_t image[0x1ff0];
189 struct OpenBIOS_nvpart_v1 *part_header;
190
191 memset(image, '\0', sizeof(image));
192
193 start = 0;
194
195 // OpenBIOS nvram variables
196 // Variable partition
197 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
198 part_header->signature = OPENBIOS_PART_SYSTEM;
199 pstrcpy(part_header->name, sizeof(part_header->name), "system");
200
201 end = start + sizeof(struct OpenBIOS_nvpart_v1);
202 for (i = 0; i < nb_prom_envs; i++)
203 end = OpenBIOS_set_var(image, end, prom_envs[i]);
204
205 // End marker
206 image[end++] = '\0';
207
208 end = start + ((end - start + 15) & ~15);
209 OpenBIOS_finish_partition(part_header, end - start);
210
211 // free partition
212 start = end;
213 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
214 part_header->signature = OPENBIOS_PART_FREE;
215 pstrcpy(part_header->name, sizeof(part_header->name), "free");
216
217 end = 0x1fd0;
218 OpenBIOS_finish_partition(part_header, end - start);
219
220 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
221 nvram_machine_id);
222
223 for (i = 0; i < sizeof(image); i++)
224 m48t59_write(nvram, i, image[i]);
225 }
226
227 static void *slavio_intctl;
228
229 void pic_info(Monitor *mon)
230 {
231 if (slavio_intctl)
232 slavio_pic_info(mon, slavio_intctl);
233 }
234
235 void irq_info(Monitor *mon)
236 {
237 if (slavio_intctl)
238 slavio_irq_info(mon, slavio_intctl);
239 }
240
241 void cpu_check_irqs(CPUState *env)
242 {
243 if (env->pil_in && (env->interrupt_index == 0 ||
244 (env->interrupt_index & ~15) == TT_EXTINT)) {
245 unsigned int i;
246
247 for (i = 15; i > 0; i--) {
248 if (env->pil_in & (1 << i)) {
249 int old_interrupt = env->interrupt_index;
250
251 env->interrupt_index = TT_EXTINT | i;
252 if (old_interrupt != env->interrupt_index) {
253 DPRINTF("Set CPU IRQ %d\n", i);
254 cpu_interrupt(env, CPU_INTERRUPT_HARD);
255 }
256 break;
257 }
258 }
259 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
260 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
261 env->interrupt_index = 0;
262 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
263 }
264 }
265
266 static void cpu_set_irq(void *opaque, int irq, int level)
267 {
268 CPUState *env = opaque;
269
270 if (level) {
271 DPRINTF("Raise CPU IRQ %d\n", irq);
272 env->halted = 0;
273 env->pil_in |= 1 << irq;
274 cpu_check_irqs(env);
275 } else {
276 DPRINTF("Lower CPU IRQ %d\n", irq);
277 env->pil_in &= ~(1 << irq);
278 cpu_check_irqs(env);
279 }
280 }
281
282 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
283 {
284 }
285
286 static void *slavio_misc;
287
288 void qemu_system_powerdown(void)
289 {
290 slavio_set_power_fail(slavio_misc, 1);
291 }
292
293 static void main_cpu_reset(void *opaque)
294 {
295 CPUState *env = opaque;
296
297 cpu_reset(env);
298 env->halted = 0;
299 }
300
301 static void secondary_cpu_reset(void *opaque)
302 {
303 CPUState *env = opaque;
304
305 cpu_reset(env);
306 env->halted = 1;
307 }
308
309 static void cpu_halt_signal(void *opaque, int irq, int level)
310 {
311 if (level && cpu_single_env)
312 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
313 }
314
315 static unsigned long sun4m_load_kernel(const char *kernel_filename,
316 const char *initrd_filename,
317 ram_addr_t RAM_size)
318 {
319 int linux_boot;
320 unsigned int i;
321 long initrd_size, kernel_size;
322
323 linux_boot = (kernel_filename != NULL);
324
325 kernel_size = 0;
326 if (linux_boot) {
327 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
328 NULL);
329 if (kernel_size < 0)
330 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
331 RAM_size - KERNEL_LOAD_ADDR);
332 if (kernel_size < 0)
333 kernel_size = load_image_targphys(kernel_filename,
334 KERNEL_LOAD_ADDR,
335 RAM_size - KERNEL_LOAD_ADDR);
336 if (kernel_size < 0) {
337 fprintf(stderr, "qemu: could not load kernel '%s'\n",
338 kernel_filename);
339 exit(1);
340 }
341
342 /* load initrd */
343 initrd_size = 0;
344 if (initrd_filename) {
345 initrd_size = load_image_targphys(initrd_filename,
346 INITRD_LOAD_ADDR,
347 RAM_size - INITRD_LOAD_ADDR);
348 if (initrd_size < 0) {
349 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
350 initrd_filename);
351 exit(1);
352 }
353 }
354 if (initrd_size > 0) {
355 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
356 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
357 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
358 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
359 break;
360 }
361 }
362 }
363 }
364 return kernel_size;
365 }
366
367 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
368 void *dma_opaque, qemu_irq irq, qemu_irq *reset)
369 {
370 DeviceState *dev;
371 SysBusDevice *s;
372
373 qemu_check_nic_model(&nd_table[0], "lance");
374
375 dev = qdev_create(NULL, "lance");
376 qdev_set_netdev(dev, nd);
377 qdev_set_prop_ptr(dev, "dma", dma_opaque);
378 qdev_init(dev);
379 s = sysbus_from_qdev(dev);
380 sysbus_mmio_map(s, 0, leaddr);
381 sysbus_connect_irq(s, 0, irq);
382 *reset = qdev_get_gpio_in(dev, 0);
383 }
384
385 /* NCR89C100/MACIO Internal ID register */
386 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
387
388 static void idreg_init(target_phys_addr_t addr)
389 {
390 DeviceState *dev;
391 SysBusDevice *s;
392
393 dev = qdev_create(NULL, "macio_idreg");
394 qdev_init(dev);
395 s = sysbus_from_qdev(dev);
396
397 sysbus_mmio_map(s, 0, addr);
398 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
399 }
400
401 static void idreg_init1(SysBusDevice *dev)
402 {
403 ram_addr_t idreg_offset;
404
405 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
406 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
407 }
408
409 static SysBusDeviceInfo idreg_info = {
410 .init = idreg_init1,
411 .qdev.name = "macio_idreg",
412 .qdev.size = sizeof(SysBusDevice),
413 .qdev.props = (DevicePropList[]) {
414 {.name = NULL}
415 }
416 };
417
418 static void idreg_register_devices(void)
419 {
420 sysbus_register_withprop(&idreg_info);
421 }
422
423 device_init(idreg_register_devices);
424
425 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
426 const char *boot_device,
427 const char *kernel_filename,
428 const char *kernel_cmdline,
429 const char *initrd_filename, const char *cpu_model)
430
431 {
432 CPUState *env, *envs[MAX_CPUS];
433 unsigned int i;
434 void *iommu, *espdma, *ledma, *nvram;
435 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
436 *espdma_irq, *ledma_irq;
437 qemu_irq *esp_reset, *le_reset;
438 qemu_irq fdc_tc;
439 qemu_irq *cpu_halt;
440 ram_addr_t ram_offset, prom_offset;
441 unsigned long kernel_size;
442 int ret;
443 char *filename;
444 BlockDriverState *fd[MAX_FD];
445 int drive_index;
446 void *fw_cfg;
447
448 /* init CPUs */
449 if (!cpu_model)
450 cpu_model = hwdef->default_cpu_model;
451
452 for(i = 0; i < smp_cpus; i++) {
453 env = cpu_init(cpu_model);
454 if (!env) {
455 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
456 exit(1);
457 }
458 cpu_sparc_set_id(env, i);
459 envs[i] = env;
460 if (i == 0) {
461 qemu_register_reset(main_cpu_reset, env);
462 } else {
463 qemu_register_reset(secondary_cpu_reset, env);
464 env->halted = 1;
465 }
466 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
467 env->prom_addr = hwdef->slavio_base;
468 }
469
470 for (i = smp_cpus; i < MAX_CPUS; i++)
471 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
472
473
474 /* allocate RAM */
475 if ((uint64_t)RAM_size > hwdef->max_mem) {
476 fprintf(stderr,
477 "qemu: Too much memory for this machine: %d, maximum %d\n",
478 (unsigned int)(RAM_size / (1024 * 1024)),
479 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
480 exit(1);
481 }
482 ram_offset = qemu_ram_alloc(RAM_size);
483 cpu_register_physical_memory(0, RAM_size, ram_offset);
484
485 /* load boot prom */
486 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
487 cpu_register_physical_memory(hwdef->slavio_base,
488 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
489 TARGET_PAGE_MASK,
490 prom_offset | IO_MEM_ROM);
491
492 if (bios_name == NULL)
493 bios_name = PROM_FILENAME;
494 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
495 if (filename) {
496 ret = load_elf(filename, hwdef->slavio_base - PROM_VADDR,
497 NULL, NULL, NULL);
498 if (ret < 0 || ret > PROM_SIZE_MAX)
499 ret = load_image_targphys(filename, hwdef->slavio_base,
500 PROM_SIZE_MAX);
501 qemu_free(filename);
502 } else {
503 ret = -1;
504 }
505 if (ret < 0 || ret > PROM_SIZE_MAX) {
506 fprintf(stderr, "qemu: could not load prom '%s'\n",
507 bios_name);
508 exit(1);
509 }
510
511 /* set up devices */
512 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
513 hwdef->intctl_base + 0x10000ULL,
514 &hwdef->intbit_to_level[0],
515 &slavio_irq, &slavio_cpu_irq,
516 cpu_irqs,
517 hwdef->clock_irq);
518
519 if (hwdef->idreg_base) {
520 idreg_init(hwdef->idreg_base);
521 }
522
523 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
524 slavio_irq[hwdef->me_irq]);
525
526 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
527 iommu, &espdma_irq, &esp_reset);
528
529 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
530 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
531 &le_reset);
532
533 if (graphic_depth != 8 && graphic_depth != 24) {
534 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
535 exit (1);
536 }
537 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
538 graphic_depth);
539
540 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
541
542 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
543 hwdef->nvram_size, 8);
544
545 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
546 slavio_cpu_irq, smp_cpus);
547
548 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
549 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
550 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
551 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
552 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq],
553 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
554
555 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
556 slavio_misc = slavio_misc_init(hwdef->slavio_base,
557 hwdef->aux1_base, hwdef->aux2_base,
558 slavio_irq[hwdef->me_irq], fdc_tc);
559 if (hwdef->apc_base) {
560 apc_init(hwdef->apc_base, cpu_halt[0]);
561 }
562
563 if (hwdef->fd_base) {
564 /* there is zero or one floppy drive */
565 memset(fd, 0, sizeof(fd));
566 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
567 if (drive_index != -1)
568 fd[0] = drives_table[drive_index].bdrv;
569
570 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
571 &fdc_tc);
572 }
573
574 if (drive_get_max_bus(IF_SCSI) > 0) {
575 fprintf(stderr, "qemu: too many SCSI bus\n");
576 exit(1);
577 }
578
579 esp_init(hwdef->esp_base, 2,
580 espdma_memory_read, espdma_memory_write,
581 espdma, *espdma_irq, esp_reset);
582
583 if (hwdef->cs_base)
584 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
585
586 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
587 RAM_size);
588
589 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
590 boot_device, RAM_size, kernel_size, graphic_width,
591 graphic_height, graphic_depth, hwdef->nvram_machine_id,
592 "Sun4m");
593
594 if (hwdef->ecc_base)
595 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
596 hwdef->ecc_version);
597
598 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
599 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
600 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
601 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
602 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
603 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
604 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
605 if (kernel_cmdline) {
606 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
607 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
608 } else {
609 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
610 }
611 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
612 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
613 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
614 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
615 }
616
617 enum {
618 ss2_id = 0,
619 ss5_id = 32,
620 vger_id,
621 lx_id,
622 ss4_id,
623 scls_id,
624 sbook_id,
625 ss10_id = 64,
626 ss20_id,
627 ss600mp_id,
628 ss1000_id = 96,
629 ss2000_id,
630 };
631
632 static const struct sun4m_hwdef sun4m_hwdefs[] = {
633 /* SS-5 */
634 {
635 .iommu_base = 0x10000000,
636 .tcx_base = 0x50000000,
637 .cs_base = 0x6c000000,
638 .slavio_base = 0x70000000,
639 .ms_kb_base = 0x71000000,
640 .serial_base = 0x71100000,
641 .nvram_base = 0x71200000,
642 .fd_base = 0x71400000,
643 .counter_base = 0x71d00000,
644 .intctl_base = 0x71e00000,
645 .idreg_base = 0x78000000,
646 .dma_base = 0x78400000,
647 .esp_base = 0x78800000,
648 .le_base = 0x78c00000,
649 .apc_base = 0x6a000000,
650 .aux1_base = 0x71900000,
651 .aux2_base = 0x71910000,
652 .vram_size = 0x00100000,
653 .nvram_size = 0x2000,
654 .esp_irq = 18,
655 .le_irq = 16,
656 .clock_irq = 7,
657 .clock1_irq = 19,
658 .ms_kb_irq = 14,
659 .ser_irq = 15,
660 .fd_irq = 22,
661 .me_irq = 30,
662 .cs_irq = 5,
663 .nvram_machine_id = 0x80,
664 .machine_id = ss5_id,
665 .iommu_version = 0x05000000,
666 .intbit_to_level = {
667 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
668 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
669 },
670 .max_mem = 0x10000000,
671 .default_cpu_model = "Fujitsu MB86904",
672 },
673 /* SS-10 */
674 {
675 .iommu_base = 0xfe0000000ULL,
676 .tcx_base = 0xe20000000ULL,
677 .slavio_base = 0xff0000000ULL,
678 .ms_kb_base = 0xff1000000ULL,
679 .serial_base = 0xff1100000ULL,
680 .nvram_base = 0xff1200000ULL,
681 .fd_base = 0xff1700000ULL,
682 .counter_base = 0xff1300000ULL,
683 .intctl_base = 0xff1400000ULL,
684 .idreg_base = 0xef0000000ULL,
685 .dma_base = 0xef0400000ULL,
686 .esp_base = 0xef0800000ULL,
687 .le_base = 0xef0c00000ULL,
688 .apc_base = 0xefa000000ULL, // XXX should not exist
689 .aux1_base = 0xff1800000ULL,
690 .aux2_base = 0xff1a01000ULL,
691 .ecc_base = 0xf00000000ULL,
692 .ecc_version = 0x10000000, // version 0, implementation 1
693 .vram_size = 0x00100000,
694 .nvram_size = 0x2000,
695 .esp_irq = 18,
696 .le_irq = 16,
697 .clock_irq = 7,
698 .clock1_irq = 19,
699 .ms_kb_irq = 14,
700 .ser_irq = 15,
701 .fd_irq = 22,
702 .me_irq = 30,
703 .ecc_irq = 28,
704 .nvram_machine_id = 0x72,
705 .machine_id = ss10_id,
706 .iommu_version = 0x03000000,
707 .intbit_to_level = {
708 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
709 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
710 },
711 .max_mem = 0xf00000000ULL,
712 .default_cpu_model = "TI SuperSparc II",
713 },
714 /* SS-600MP */
715 {
716 .iommu_base = 0xfe0000000ULL,
717 .tcx_base = 0xe20000000ULL,
718 .slavio_base = 0xff0000000ULL,
719 .ms_kb_base = 0xff1000000ULL,
720 .serial_base = 0xff1100000ULL,
721 .nvram_base = 0xff1200000ULL,
722 .counter_base = 0xff1300000ULL,
723 .intctl_base = 0xff1400000ULL,
724 .dma_base = 0xef0081000ULL,
725 .esp_base = 0xef0080000ULL,
726 .le_base = 0xef0060000ULL,
727 .apc_base = 0xefa000000ULL, // XXX should not exist
728 .aux1_base = 0xff1800000ULL,
729 .aux2_base = 0xff1a01000ULL, // XXX should not exist
730 .ecc_base = 0xf00000000ULL,
731 .ecc_version = 0x00000000, // version 0, implementation 0
732 .vram_size = 0x00100000,
733 .nvram_size = 0x2000,
734 .esp_irq = 18,
735 .le_irq = 16,
736 .clock_irq = 7,
737 .clock1_irq = 19,
738 .ms_kb_irq = 14,
739 .ser_irq = 15,
740 .fd_irq = 22,
741 .me_irq = 30,
742 .ecc_irq = 28,
743 .nvram_machine_id = 0x71,
744 .machine_id = ss600mp_id,
745 .iommu_version = 0x01000000,
746 .intbit_to_level = {
747 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
748 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
749 },
750 .max_mem = 0xf00000000ULL,
751 .default_cpu_model = "TI SuperSparc II",
752 },
753 /* SS-20 */
754 {
755 .iommu_base = 0xfe0000000ULL,
756 .tcx_base = 0xe20000000ULL,
757 .slavio_base = 0xff0000000ULL,
758 .ms_kb_base = 0xff1000000ULL,
759 .serial_base = 0xff1100000ULL,
760 .nvram_base = 0xff1200000ULL,
761 .fd_base = 0xff1700000ULL,
762 .counter_base = 0xff1300000ULL,
763 .intctl_base = 0xff1400000ULL,
764 .idreg_base = 0xef0000000ULL,
765 .dma_base = 0xef0400000ULL,
766 .esp_base = 0xef0800000ULL,
767 .le_base = 0xef0c00000ULL,
768 .apc_base = 0xefa000000ULL, // XXX should not exist
769 .aux1_base = 0xff1800000ULL,
770 .aux2_base = 0xff1a01000ULL,
771 .ecc_base = 0xf00000000ULL,
772 .ecc_version = 0x20000000, // version 0, implementation 2
773 .vram_size = 0x00100000,
774 .nvram_size = 0x2000,
775 .esp_irq = 18,
776 .le_irq = 16,
777 .clock_irq = 7,
778 .clock1_irq = 19,
779 .ms_kb_irq = 14,
780 .ser_irq = 15,
781 .fd_irq = 22,
782 .me_irq = 30,
783 .ecc_irq = 28,
784 .nvram_machine_id = 0x72,
785 .machine_id = ss20_id,
786 .iommu_version = 0x13000000,
787 .intbit_to_level = {
788 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
789 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
790 },
791 .max_mem = 0xf00000000ULL,
792 .default_cpu_model = "TI SuperSparc II",
793 },
794 /* Voyager */
795 {
796 .iommu_base = 0x10000000,
797 .tcx_base = 0x50000000,
798 .slavio_base = 0x70000000,
799 .ms_kb_base = 0x71000000,
800 .serial_base = 0x71100000,
801 .nvram_base = 0x71200000,
802 .fd_base = 0x71400000,
803 .counter_base = 0x71d00000,
804 .intctl_base = 0x71e00000,
805 .idreg_base = 0x78000000,
806 .dma_base = 0x78400000,
807 .esp_base = 0x78800000,
808 .le_base = 0x78c00000,
809 .apc_base = 0x71300000, // pmc
810 .aux1_base = 0x71900000,
811 .aux2_base = 0x71910000,
812 .vram_size = 0x00100000,
813 .nvram_size = 0x2000,
814 .esp_irq = 18,
815 .le_irq = 16,
816 .clock_irq = 7,
817 .clock1_irq = 19,
818 .ms_kb_irq = 14,
819 .ser_irq = 15,
820 .fd_irq = 22,
821 .me_irq = 30,
822 .nvram_machine_id = 0x80,
823 .machine_id = vger_id,
824 .iommu_version = 0x05000000,
825 .intbit_to_level = {
826 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
827 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
828 },
829 .max_mem = 0x10000000,
830 .default_cpu_model = "Fujitsu MB86904",
831 },
832 /* LX */
833 {
834 .iommu_base = 0x10000000,
835 .tcx_base = 0x50000000,
836 .slavio_base = 0x70000000,
837 .ms_kb_base = 0x71000000,
838 .serial_base = 0x71100000,
839 .nvram_base = 0x71200000,
840 .fd_base = 0x71400000,
841 .counter_base = 0x71d00000,
842 .intctl_base = 0x71e00000,
843 .idreg_base = 0x78000000,
844 .dma_base = 0x78400000,
845 .esp_base = 0x78800000,
846 .le_base = 0x78c00000,
847 .aux1_base = 0x71900000,
848 .aux2_base = 0x71910000,
849 .vram_size = 0x00100000,
850 .nvram_size = 0x2000,
851 .esp_irq = 18,
852 .le_irq = 16,
853 .clock_irq = 7,
854 .clock1_irq = 19,
855 .ms_kb_irq = 14,
856 .ser_irq = 15,
857 .fd_irq = 22,
858 .me_irq = 30,
859 .nvram_machine_id = 0x80,
860 .machine_id = lx_id,
861 .iommu_version = 0x04000000,
862 .intbit_to_level = {
863 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
864 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
865 },
866 .max_mem = 0x10000000,
867 .default_cpu_model = "TI MicroSparc I",
868 },
869 /* SS-4 */
870 {
871 .iommu_base = 0x10000000,
872 .tcx_base = 0x50000000,
873 .cs_base = 0x6c000000,
874 .slavio_base = 0x70000000,
875 .ms_kb_base = 0x71000000,
876 .serial_base = 0x71100000,
877 .nvram_base = 0x71200000,
878 .fd_base = 0x71400000,
879 .counter_base = 0x71d00000,
880 .intctl_base = 0x71e00000,
881 .idreg_base = 0x78000000,
882 .dma_base = 0x78400000,
883 .esp_base = 0x78800000,
884 .le_base = 0x78c00000,
885 .apc_base = 0x6a000000,
886 .aux1_base = 0x71900000,
887 .aux2_base = 0x71910000,
888 .vram_size = 0x00100000,
889 .nvram_size = 0x2000,
890 .esp_irq = 18,
891 .le_irq = 16,
892 .clock_irq = 7,
893 .clock1_irq = 19,
894 .ms_kb_irq = 14,
895 .ser_irq = 15,
896 .fd_irq = 22,
897 .me_irq = 30,
898 .cs_irq = 5,
899 .nvram_machine_id = 0x80,
900 .machine_id = ss4_id,
901 .iommu_version = 0x05000000,
902 .intbit_to_level = {
903 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
904 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
905 },
906 .max_mem = 0x10000000,
907 .default_cpu_model = "Fujitsu MB86904",
908 },
909 /* SPARCClassic */
910 {
911 .iommu_base = 0x10000000,
912 .tcx_base = 0x50000000,
913 .slavio_base = 0x70000000,
914 .ms_kb_base = 0x71000000,
915 .serial_base = 0x71100000,
916 .nvram_base = 0x71200000,
917 .fd_base = 0x71400000,
918 .counter_base = 0x71d00000,
919 .intctl_base = 0x71e00000,
920 .idreg_base = 0x78000000,
921 .dma_base = 0x78400000,
922 .esp_base = 0x78800000,
923 .le_base = 0x78c00000,
924 .apc_base = 0x6a000000,
925 .aux1_base = 0x71900000,
926 .aux2_base = 0x71910000,
927 .vram_size = 0x00100000,
928 .nvram_size = 0x2000,
929 .esp_irq = 18,
930 .le_irq = 16,
931 .clock_irq = 7,
932 .clock1_irq = 19,
933 .ms_kb_irq = 14,
934 .ser_irq = 15,
935 .fd_irq = 22,
936 .me_irq = 30,
937 .nvram_machine_id = 0x80,
938 .machine_id = scls_id,
939 .iommu_version = 0x05000000,
940 .intbit_to_level = {
941 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
942 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
943 },
944 .max_mem = 0x10000000,
945 .default_cpu_model = "TI MicroSparc I",
946 },
947 /* SPARCbook */
948 {
949 .iommu_base = 0x10000000,
950 .tcx_base = 0x50000000, // XXX
951 .slavio_base = 0x70000000,
952 .ms_kb_base = 0x71000000,
953 .serial_base = 0x71100000,
954 .nvram_base = 0x71200000,
955 .fd_base = 0x71400000,
956 .counter_base = 0x71d00000,
957 .intctl_base = 0x71e00000,
958 .idreg_base = 0x78000000,
959 .dma_base = 0x78400000,
960 .esp_base = 0x78800000,
961 .le_base = 0x78c00000,
962 .apc_base = 0x6a000000,
963 .aux1_base = 0x71900000,
964 .aux2_base = 0x71910000,
965 .vram_size = 0x00100000,
966 .nvram_size = 0x2000,
967 .esp_irq = 18,
968 .le_irq = 16,
969 .clock_irq = 7,
970 .clock1_irq = 19,
971 .ms_kb_irq = 14,
972 .ser_irq = 15,
973 .fd_irq = 22,
974 .me_irq = 30,
975 .nvram_machine_id = 0x80,
976 .machine_id = sbook_id,
977 .iommu_version = 0x05000000,
978 .intbit_to_level = {
979 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
980 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
981 },
982 .max_mem = 0x10000000,
983 .default_cpu_model = "TI MicroSparc I",
984 },
985 };
986
987 /* SPARCstation 5 hardware initialisation */
988 static void ss5_init(ram_addr_t RAM_size,
989 const char *boot_device,
990 const char *kernel_filename, const char *kernel_cmdline,
991 const char *initrd_filename, const char *cpu_model)
992 {
993 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
994 kernel_cmdline, initrd_filename, cpu_model);
995 }
996
997 /* SPARCstation 10 hardware initialisation */
998 static void ss10_init(ram_addr_t RAM_size,
999 const char *boot_device,
1000 const char *kernel_filename, const char *kernel_cmdline,
1001 const char *initrd_filename, const char *cpu_model)
1002 {
1003 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1004 kernel_cmdline, initrd_filename, cpu_model);
1005 }
1006
1007 /* SPARCserver 600MP hardware initialisation */
1008 static void ss600mp_init(ram_addr_t RAM_size,
1009 const char *boot_device,
1010 const char *kernel_filename,
1011 const char *kernel_cmdline,
1012 const char *initrd_filename, const char *cpu_model)
1013 {
1014 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1015 kernel_cmdline, initrd_filename, cpu_model);
1016 }
1017
1018 /* SPARCstation 20 hardware initialisation */
1019 static void ss20_init(ram_addr_t RAM_size,
1020 const char *boot_device,
1021 const char *kernel_filename, const char *kernel_cmdline,
1022 const char *initrd_filename, const char *cpu_model)
1023 {
1024 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1025 kernel_cmdline, initrd_filename, cpu_model);
1026 }
1027
1028 /* SPARCstation Voyager hardware initialisation */
1029 static void vger_init(ram_addr_t RAM_size,
1030 const char *boot_device,
1031 const char *kernel_filename, const char *kernel_cmdline,
1032 const char *initrd_filename, const char *cpu_model)
1033 {
1034 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1035 kernel_cmdline, initrd_filename, cpu_model);
1036 }
1037
1038 /* SPARCstation LX hardware initialisation */
1039 static void ss_lx_init(ram_addr_t RAM_size,
1040 const char *boot_device,
1041 const char *kernel_filename, const char *kernel_cmdline,
1042 const char *initrd_filename, const char *cpu_model)
1043 {
1044 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1045 kernel_cmdline, initrd_filename, cpu_model);
1046 }
1047
1048 /* SPARCstation 4 hardware initialisation */
1049 static void ss4_init(ram_addr_t RAM_size,
1050 const char *boot_device,
1051 const char *kernel_filename, const char *kernel_cmdline,
1052 const char *initrd_filename, const char *cpu_model)
1053 {
1054 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1055 kernel_cmdline, initrd_filename, cpu_model);
1056 }
1057
1058 /* SPARCClassic hardware initialisation */
1059 static void scls_init(ram_addr_t RAM_size,
1060 const char *boot_device,
1061 const char *kernel_filename, const char *kernel_cmdline,
1062 const char *initrd_filename, const char *cpu_model)
1063 {
1064 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1065 kernel_cmdline, initrd_filename, cpu_model);
1066 }
1067
1068 /* SPARCbook hardware initialisation */
1069 static void sbook_init(ram_addr_t RAM_size,
1070 const char *boot_device,
1071 const char *kernel_filename, const char *kernel_cmdline,
1072 const char *initrd_filename, const char *cpu_model)
1073 {
1074 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1075 kernel_cmdline, initrd_filename, cpu_model);
1076 }
1077
1078 static QEMUMachine ss5_machine = {
1079 .name = "SS-5",
1080 .desc = "Sun4m platform, SPARCstation 5",
1081 .init = ss5_init,
1082 .use_scsi = 1,
1083 .is_default = 1,
1084 };
1085
1086 static QEMUMachine ss10_machine = {
1087 .name = "SS-10",
1088 .desc = "Sun4m platform, SPARCstation 10",
1089 .init = ss10_init,
1090 .use_scsi = 1,
1091 .max_cpus = 4,
1092 };
1093
1094 static QEMUMachine ss600mp_machine = {
1095 .name = "SS-600MP",
1096 .desc = "Sun4m platform, SPARCserver 600MP",
1097 .init = ss600mp_init,
1098 .use_scsi = 1,
1099 .max_cpus = 4,
1100 };
1101
1102 static QEMUMachine ss20_machine = {
1103 .name = "SS-20",
1104 .desc = "Sun4m platform, SPARCstation 20",
1105 .init = ss20_init,
1106 .use_scsi = 1,
1107 .max_cpus = 4,
1108 };
1109
1110 static QEMUMachine voyager_machine = {
1111 .name = "Voyager",
1112 .desc = "Sun4m platform, SPARCstation Voyager",
1113 .init = vger_init,
1114 .use_scsi = 1,
1115 };
1116
1117 static QEMUMachine ss_lx_machine = {
1118 .name = "LX",
1119 .desc = "Sun4m platform, SPARCstation LX",
1120 .init = ss_lx_init,
1121 .use_scsi = 1,
1122 };
1123
1124 static QEMUMachine ss4_machine = {
1125 .name = "SS-4",
1126 .desc = "Sun4m platform, SPARCstation 4",
1127 .init = ss4_init,
1128 .use_scsi = 1,
1129 };
1130
1131 static QEMUMachine scls_machine = {
1132 .name = "SPARCClassic",
1133 .desc = "Sun4m platform, SPARCClassic",
1134 .init = scls_init,
1135 .use_scsi = 1,
1136 };
1137
1138 static QEMUMachine sbook_machine = {
1139 .name = "SPARCbook",
1140 .desc = "Sun4m platform, SPARCbook",
1141 .init = sbook_init,
1142 .use_scsi = 1,
1143 };
1144
1145 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1146 /* SS-1000 */
1147 {
1148 .iounit_bases = {
1149 0xfe0200000ULL,
1150 0xfe1200000ULL,
1151 0xfe2200000ULL,
1152 0xfe3200000ULL,
1153 -1,
1154 },
1155 .tcx_base = 0x820000000ULL,
1156 .slavio_base = 0xf00000000ULL,
1157 .ms_kb_base = 0xf00240000ULL,
1158 .serial_base = 0xf00200000ULL,
1159 .nvram_base = 0xf00280000ULL,
1160 .counter_base = 0xf00300000ULL,
1161 .espdma_base = 0x800081000ULL,
1162 .esp_base = 0x800080000ULL,
1163 .ledma_base = 0x800040000ULL,
1164 .le_base = 0x800060000ULL,
1165 .sbi_base = 0xf02800000ULL,
1166 .vram_size = 0x00100000,
1167 .nvram_size = 0x2000,
1168 .esp_irq = 3,
1169 .le_irq = 4,
1170 .clock_irq = 14,
1171 .clock1_irq = 10,
1172 .ms_kb_irq = 12,
1173 .ser_irq = 12,
1174 .nvram_machine_id = 0x80,
1175 .machine_id = ss1000_id,
1176 .iounit_version = 0x03000000,
1177 .max_mem = 0xf00000000ULL,
1178 .default_cpu_model = "TI SuperSparc II",
1179 },
1180 /* SS-2000 */
1181 {
1182 .iounit_bases = {
1183 0xfe0200000ULL,
1184 0xfe1200000ULL,
1185 0xfe2200000ULL,
1186 0xfe3200000ULL,
1187 0xfe4200000ULL,
1188 },
1189 .tcx_base = 0x820000000ULL,
1190 .slavio_base = 0xf00000000ULL,
1191 .ms_kb_base = 0xf00240000ULL,
1192 .serial_base = 0xf00200000ULL,
1193 .nvram_base = 0xf00280000ULL,
1194 .counter_base = 0xf00300000ULL,
1195 .espdma_base = 0x800081000ULL,
1196 .esp_base = 0x800080000ULL,
1197 .ledma_base = 0x800040000ULL,
1198 .le_base = 0x800060000ULL,
1199 .sbi_base = 0xf02800000ULL,
1200 .vram_size = 0x00100000,
1201 .nvram_size = 0x2000,
1202 .esp_irq = 3,
1203 .le_irq = 4,
1204 .clock_irq = 14,
1205 .clock1_irq = 10,
1206 .ms_kb_irq = 12,
1207 .ser_irq = 12,
1208 .nvram_machine_id = 0x80,
1209 .machine_id = ss2000_id,
1210 .iounit_version = 0x03000000,
1211 .max_mem = 0xf00000000ULL,
1212 .default_cpu_model = "TI SuperSparc II",
1213 },
1214 };
1215
1216 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1217 const char *boot_device,
1218 const char *kernel_filename,
1219 const char *kernel_cmdline,
1220 const char *initrd_filename, const char *cpu_model)
1221 {
1222 CPUState *env, *envs[MAX_CPUS];
1223 unsigned int i;
1224 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi;
1225 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1226 *espdma_irq, *ledma_irq;
1227 qemu_irq *esp_reset, *le_reset;
1228 ram_addr_t ram_offset, prom_offset;
1229 unsigned long kernel_size;
1230 int ret;
1231 char *filename;
1232 void *fw_cfg;
1233
1234 /* init CPUs */
1235 if (!cpu_model)
1236 cpu_model = hwdef->default_cpu_model;
1237
1238 for (i = 0; i < smp_cpus; i++) {
1239 env = cpu_init(cpu_model);
1240 if (!env) {
1241 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1242 exit(1);
1243 }
1244 cpu_sparc_set_id(env, i);
1245 envs[i] = env;
1246 if (i == 0) {
1247 qemu_register_reset(main_cpu_reset, env);
1248 } else {
1249 qemu_register_reset(secondary_cpu_reset, env);
1250 env->halted = 1;
1251 }
1252 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1253 env->prom_addr = hwdef->slavio_base;
1254 }
1255
1256 for (i = smp_cpus; i < MAX_CPUS; i++)
1257 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1258
1259 /* allocate RAM */
1260 if ((uint64_t)RAM_size > hwdef->max_mem) {
1261 fprintf(stderr,
1262 "qemu: Too much memory for this machine: %d, maximum %d\n",
1263 (unsigned int)(RAM_size / (1024 * 1024)),
1264 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1265 exit(1);
1266 }
1267 ram_offset = qemu_ram_alloc(RAM_size);
1268 cpu_register_physical_memory(0, RAM_size, ram_offset);
1269
1270 /* load boot prom */
1271 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1272 cpu_register_physical_memory(hwdef->slavio_base,
1273 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1274 TARGET_PAGE_MASK,
1275 prom_offset | IO_MEM_ROM);
1276
1277 if (bios_name == NULL)
1278 bios_name = PROM_FILENAME;
1279 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1280 if (filename) {
1281 ret = load_elf(filename, hwdef->slavio_base - PROM_VADDR,
1282 NULL, NULL, NULL);
1283 if (ret < 0 || ret > PROM_SIZE_MAX)
1284 ret = load_image_targphys(filename, hwdef->slavio_base,
1285 PROM_SIZE_MAX);
1286 qemu_free(filename);
1287 } else {
1288 ret = -1;
1289 }
1290 if (ret < 0 || ret > PROM_SIZE_MAX) {
1291 fprintf(stderr, "qemu: could not load prom '%s'\n",
1292 bios_name);
1293 exit(1);
1294 }
1295
1296 /* set up devices */
1297 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1298
1299 for (i = 0; i < MAX_IOUNITS; i++)
1300 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1301 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1302 hwdef->iounit_version,
1303 sbi_irq[hwdef->me_irq]);
1304
1305 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1306 iounits[0], &espdma_irq, &esp_reset);
1307
1308 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1309 iounits[0], &ledma_irq, &le_reset);
1310
1311 if (graphic_depth != 8 && graphic_depth != 24) {
1312 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1313 exit (1);
1314 }
1315 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1316 graphic_depth);
1317
1318 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1319
1320 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1321 hwdef->nvram_size, 8);
1322
1323 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1324 sbi_cpu_irq, smp_cpus);
1325
1326 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1327 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1328 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1329 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1330 escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq],
1331 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1332
1333 if (drive_get_max_bus(IF_SCSI) > 0) {
1334 fprintf(stderr, "qemu: too many SCSI bus\n");
1335 exit(1);
1336 }
1337
1338 esp_init(hwdef->esp_base, 2,
1339 espdma_memory_read, espdma_memory_write,
1340 espdma, *espdma_irq, esp_reset);
1341
1342 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1343 RAM_size);
1344
1345 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1346 boot_device, RAM_size, kernel_size, graphic_width,
1347 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1348 "Sun4d");
1349
1350 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1351 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1352 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1353 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1354 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1355 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1356 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1357 if (kernel_cmdline) {
1358 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1359 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1360 } else {
1361 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1362 }
1363 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1364 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1365 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1366 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1367 }
1368
1369 /* SPARCserver 1000 hardware initialisation */
1370 static void ss1000_init(ram_addr_t RAM_size,
1371 const char *boot_device,
1372 const char *kernel_filename, const char *kernel_cmdline,
1373 const char *initrd_filename, const char *cpu_model)
1374 {
1375 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1376 kernel_cmdline, initrd_filename, cpu_model);
1377 }
1378
1379 /* SPARCcenter 2000 hardware initialisation */
1380 static void ss2000_init(ram_addr_t RAM_size,
1381 const char *boot_device,
1382 const char *kernel_filename, const char *kernel_cmdline,
1383 const char *initrd_filename, const char *cpu_model)
1384 {
1385 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1386 kernel_cmdline, initrd_filename, cpu_model);
1387 }
1388
1389 static QEMUMachine ss1000_machine = {
1390 .name = "SS-1000",
1391 .desc = "Sun4d platform, SPARCserver 1000",
1392 .init = ss1000_init,
1393 .use_scsi = 1,
1394 .max_cpus = 8,
1395 };
1396
1397 static QEMUMachine ss2000_machine = {
1398 .name = "SS-2000",
1399 .desc = "Sun4d platform, SPARCcenter 2000",
1400 .init = ss2000_init,
1401 .use_scsi = 1,
1402 .max_cpus = 20,
1403 };
1404
1405 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1406 /* SS-2 */
1407 {
1408 .iommu_base = 0xf8000000,
1409 .tcx_base = 0xfe000000,
1410 .slavio_base = 0xf6000000,
1411 .intctl_base = 0xf5000000,
1412 .counter_base = 0xf3000000,
1413 .ms_kb_base = 0xf0000000,
1414 .serial_base = 0xf1000000,
1415 .nvram_base = 0xf2000000,
1416 .fd_base = 0xf7200000,
1417 .dma_base = 0xf8400000,
1418 .esp_base = 0xf8800000,
1419 .le_base = 0xf8c00000,
1420 .aux1_base = 0xf7400003,
1421 .vram_size = 0x00100000,
1422 .nvram_size = 0x800,
1423 .esp_irq = 2,
1424 .le_irq = 3,
1425 .clock_irq = 5,
1426 .clock1_irq = 7,
1427 .ms_kb_irq = 1,
1428 .ser_irq = 1,
1429 .fd_irq = 1,
1430 .me_irq = 1,
1431 .nvram_machine_id = 0x55,
1432 .machine_id = ss2_id,
1433 .max_mem = 0x10000000,
1434 .default_cpu_model = "Cypress CY7C601",
1435 },
1436 };
1437
1438 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1439 const char *boot_device,
1440 const char *kernel_filename,
1441 const char *kernel_cmdline,
1442 const char *initrd_filename, const char *cpu_model)
1443 {
1444 CPUState *env;
1445 void *iommu, *espdma, *ledma, *nvram;
1446 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
1447 qemu_irq *esp_reset, *le_reset;
1448 qemu_irq fdc_tc;
1449 ram_addr_t ram_offset, prom_offset;
1450 unsigned long kernel_size;
1451 int ret;
1452 char *filename;
1453 BlockDriverState *fd[MAX_FD];
1454 int drive_index;
1455 void *fw_cfg;
1456
1457 /* init CPU */
1458 if (!cpu_model)
1459 cpu_model = hwdef->default_cpu_model;
1460
1461 env = cpu_init(cpu_model);
1462 if (!env) {
1463 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1464 exit(1);
1465 }
1466
1467 cpu_sparc_set_id(env, 0);
1468
1469 qemu_register_reset(main_cpu_reset, env);
1470 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1471 env->prom_addr = hwdef->slavio_base;
1472
1473 /* allocate RAM */
1474 if ((uint64_t)RAM_size > hwdef->max_mem) {
1475 fprintf(stderr,
1476 "qemu: Too much memory for this machine: %d, maximum %d\n",
1477 (unsigned int)(RAM_size / (1024 * 1024)),
1478 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1479 exit(1);
1480 }
1481 ram_offset = qemu_ram_alloc(RAM_size);
1482 cpu_register_physical_memory(0, RAM_size, ram_offset);
1483
1484 /* load boot prom */
1485 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1486 cpu_register_physical_memory(hwdef->slavio_base,
1487 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1488 TARGET_PAGE_MASK,
1489 prom_offset | IO_MEM_ROM);
1490
1491 if (bios_name == NULL)
1492 bios_name = PROM_FILENAME;
1493 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1494 if (filename) {
1495 ret = load_elf(filename, hwdef->slavio_base - PROM_VADDR,
1496 NULL, NULL, NULL);
1497 if (ret < 0 || ret > PROM_SIZE_MAX)
1498 ret = load_image_targphys(filename, hwdef->slavio_base,
1499 PROM_SIZE_MAX);
1500 qemu_free(filename);
1501 } else {
1502 ret = -1;
1503 }
1504 if (ret < 0 || ret > PROM_SIZE_MAX) {
1505 fprintf(stderr, "qemu: could not load prom '%s'\n",
1506 filename);
1507 exit(1);
1508 }
1509
1510 /* set up devices */
1511 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1512 &slavio_irq, cpu_irqs);
1513
1514 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1515 slavio_irq[hwdef->me_irq]);
1516
1517 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1518 iommu, &espdma_irq, &esp_reset);
1519
1520 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1521 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1522 &le_reset);
1523
1524 if (graphic_depth != 8 && graphic_depth != 24) {
1525 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1526 exit (1);
1527 }
1528 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1529 graphic_depth);
1530
1531 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1532
1533 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1534 hwdef->nvram_size, 2);
1535
1536 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1537 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1538 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1539 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1540 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1541 slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1],
1542 ESCC_CLOCK, 1);
1543
1544 slavio_misc = slavio_misc_init(0, hwdef->aux1_base, 0,
1545 slavio_irq[hwdef->me_irq], fdc_tc);
1546
1547 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1548 /* there is zero or one floppy drive */
1549 memset(fd, 0, sizeof(fd));
1550 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1551 if (drive_index != -1)
1552 fd[0] = drives_table[drive_index].bdrv;
1553
1554 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1555 &fdc_tc);
1556 }
1557
1558 if (drive_get_max_bus(IF_SCSI) > 0) {
1559 fprintf(stderr, "qemu: too many SCSI bus\n");
1560 exit(1);
1561 }
1562
1563 esp_init(hwdef->esp_base, 2,
1564 espdma_memory_read, espdma_memory_write,
1565 espdma, *espdma_irq, esp_reset);
1566
1567 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1568 RAM_size);
1569
1570 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1571 boot_device, RAM_size, kernel_size, graphic_width,
1572 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1573 "Sun4c");
1574
1575 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1576 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1577 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1578 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1579 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1580 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1581 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1582 if (kernel_cmdline) {
1583 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1584 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1585 } else {
1586 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1587 }
1588 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1589 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1590 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1591 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1592 }
1593
1594 /* SPARCstation 2 hardware initialisation */
1595 static void ss2_init(ram_addr_t RAM_size,
1596 const char *boot_device,
1597 const char *kernel_filename, const char *kernel_cmdline,
1598 const char *initrd_filename, const char *cpu_model)
1599 {
1600 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1601 kernel_cmdline, initrd_filename, cpu_model);
1602 }
1603
1604 static QEMUMachine ss2_machine = {
1605 .name = "SS-2",
1606 .desc = "Sun4c platform, SPARCstation 2",
1607 .init = ss2_init,
1608 .use_scsi = 1,
1609 };
1610
1611 static void ss2_machine_init(void)
1612 {
1613 qemu_register_machine(&ss5_machine);
1614 qemu_register_machine(&ss10_machine);
1615 qemu_register_machine(&ss600mp_machine);
1616 qemu_register_machine(&ss20_machine);
1617 qemu_register_machine(&voyager_machine);
1618 qemu_register_machine(&ss_lx_machine);
1619 qemu_register_machine(&ss4_machine);
1620 qemu_register_machine(&scls_machine);
1621 qemu_register_machine(&sbook_machine);
1622 qemu_register_machine(&ss1000_machine);
1623 qemu_register_machine(&ss2000_machine);
1624 qemu_register_machine(&ss2_machine);
1625 }
1626
1627 machine_init(ss2_machine_init);
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