hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pc.h"
  27 #include "nvram.h"
  28 #include "fdc.h"
  29 #include "net.h"
  30 #include "qemu-timer.h"
  31 #include "sysemu.h"
  32 #include "boards.h"
  33 #include "firmware_abi.h"
  34 #include "fw_cfg.h"
  35 #include "sysbus.h"
  36
  37 //#define DEBUG_IRQ
  38
  39 #ifdef DEBUG_IRQ
  40 #define DPRINTF(fmt, ...)                                       \
  41     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...)
  44 #endif
  45
  46 #define KERNEL_LOAD_ADDR     0x00404000
  47 #define CMDLINE_ADDR         0x003ff000
  48 #define INITRD_LOAD_ADDR     0x00300000
  49 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  50 #define PROM_VADDR           0x000ffd00000ULL
  51 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  52 #define APB_MEM_BASE         0x1ff00000000ULL
  53 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  54 #define PROM_FILENAME        "openbios-sparc64"
  55 #define NVRAM_SIZE           0x2000
  56 #define MAX_IDE_BUS          2
  57 #define BIOS_CFG_IOPORT      0x510
  58
  59 #define MAX_PILS 16
  60
  61 #define TICK_INT_DIS         0x8000000000000000ULL
  62 #define TICK_MAX             0x7fffffffffffffffULL
  63
  64 struct hwdef {
  65     const char * const default_cpu_model;
  66     uint16_t machine_id;
  67     uint64_t prom_addr;
  68     uint64_t console_serial_base;
  69 };
  70
  71 int DMA_get_channel_mode (int nchan)
  72 {
  73     return 0;
  74 }
  75 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  76 {
  77     return 0;
  78 }
  79 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  80 {
  81     return 0;
  82 }
  83 void DMA_hold_DREQ (int nchan) {}
  84 void DMA_release_DREQ (int nchan) {}
  85 void DMA_schedule(int nchan) {}
  86 void DMA_init (int high_page_enable) {}
  87 void DMA_register_channel (int nchan,
  88                            DMA_transfer_handler transfer_handler,
  89                            void *opaque)
  90 {
  91 }
  92
  93 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
  94 {
  95     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  96     return 0;
  97 }
  98
  99 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
 100                                    const char *arch,
 101                                    ram_addr_t RAM_size,
 102                                    const char *boot_devices,
 103                                    uint32_t kernel_image, uint32_t kernel_size,
 104                                    const char *cmdline,
 105                                    uint32_t initrd_image, uint32_t initrd_size,
 106                                    uint32_t NVRAM_image,
 107                                    int width, int height, int depth,
 108                                    const uint8_t *macaddr)
 109 {
 110     unsigned int i;
 111     uint32_t start, end;
 112     uint8_t image[0x1ff0];
 113     struct OpenBIOS_nvpart_v1 *part_header;
 114
 115     memset(image, '\0', sizeof(image));
 116
 117     start = 0;
 118
 119     // OpenBIOS nvram variables
 120     // Variable partition
 121     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 122     part_header->signature = OPENBIOS_PART_SYSTEM;
 123     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 124
 125     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 126     for (i = 0; i < nb_prom_envs; i++)
 127         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 128
 129     // End marker
 130     image[end++] = '\0';
 131
 132     end = start + ((end - start + 15) & ~15);
 133     OpenBIOS_finish_partition(part_header, end - start);
 134
 135     // free partition
 136     start = end;
 137     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 138     part_header->signature = OPENBIOS_PART_FREE;
 139     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 140
 141     end = 0x1fd0;
 142     OpenBIOS_finish_partition(part_header, end - start);
 143
 144     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 145
 146     for (i = 0; i < sizeof(image); i++)
 147         m48t59_write(nvram, i, image[i]);
 148
 149     return 0;
 150 }
 151 static unsigned long sun4u_load_kernel(const char *kernel_filename,
 152                                        const char *initrd_filename,
 153                                        ram_addr_t RAM_size, long *initrd_size)
 154 {
 155     int linux_boot;
 156     unsigned int i;
 157     long kernel_size;
 158
 159     linux_boot = (kernel_filename != NULL);
 160
 161     kernel_size = 0;
 162     if (linux_boot) {
 163         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
 164         if (kernel_size < 0)
 165             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 166                                     RAM_size - KERNEL_LOAD_ADDR);
 167         if (kernel_size < 0)
 168             kernel_size = load_image_targphys(kernel_filename,
 169                                               KERNEL_LOAD_ADDR,
 170                                               RAM_size - KERNEL_LOAD_ADDR);
 171         if (kernel_size < 0) {
 172             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 173                     kernel_filename);
 174             exit(1);
 175         }
 176
 177         /* load initrd */
 178         *initrd_size = 0;
 179         if (initrd_filename) {
 180             *initrd_size = load_image_targphys(initrd_filename,
 181                                                INITRD_LOAD_ADDR,
 182                                                RAM_size - INITRD_LOAD_ADDR);
 183             if (*initrd_size < 0) {
 184                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 185                         initrd_filename);
 186                 exit(1);
 187             }
 188         }
 189         if (*initrd_size > 0) {
 190             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 191                 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
 192                     stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 193                     stl_phys(KERNEL_LOAD_ADDR + i + 20, *initrd_size);
 194                     break;
 195                 }
 196             }
 197         }
 198     }
 199     return kernel_size;
 200 }
 201
 202 void pic_info(Monitor *mon)
 203 {
 204 }
 205
 206 void irq_info(Monitor *mon)
 207 {
 208 }
 209
 210 void cpu_check_irqs(CPUState *env)
 211 {
 212     uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
 213         ((env->softint & SOFTINT_TIMER) << 14);
 214
 215     if (pil && (env->interrupt_index == 0 ||
 216                 (env->interrupt_index & ~15) == TT_EXTINT)) {
 217         unsigned int i;
 218
 219         for (i = 15; i > 0; i--) {
 220             if (pil & (1 << i)) {
 221                 int old_interrupt = env->interrupt_index;
 222
 223                 env->interrupt_index = TT_EXTINT | i;
 224                 if (old_interrupt != env->interrupt_index) {
 225                     DPRINTF("Set CPU IRQ %d\n", i);
 226                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 227                 }
 228                 break;
 229             }
 230         }
 231     } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
 232         DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
 233         env->interrupt_index = 0;
 234         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 235     }
 236 }
 237
 238 static void cpu_set_irq(void *opaque, int irq, int level)
 239 {
 240     CPUState *env = opaque;
 241
 242     if (level) {
 243         DPRINTF("Raise CPU IRQ %d\n", irq);
 244         env->halted = 0;
 245         env->pil_in |= 1 << irq;
 246         cpu_check_irqs(env);
 247     } else {
 248         DPRINTF("Lower CPU IRQ %d\n", irq);
 249         env->pil_in &= ~(1 << irq);
 250         cpu_check_irqs(env);
 251     }
 252 }
 253
 254 void qemu_system_powerdown(void)
 255 {
 256 }
 257
 258 typedef struct ResetData {
 259     CPUState *env;
 260     uint64_t reset_addr;
 261 } ResetData;
 262
 263 static void main_cpu_reset(void *opaque)
 264 {
 265     ResetData *s = (ResetData *)opaque;
 266     CPUState *env = s->env;
 267
 268     cpu_reset(env);
 269     env->tick_cmpr = TICK_INT_DIS | 0;
 270     ptimer_set_limit(env->tick, TICK_MAX, 1);
 271     ptimer_run(env->tick, 1);
 272     env->stick_cmpr = TICK_INT_DIS | 0;
 273     ptimer_set_limit(env->stick, TICK_MAX, 1);
 274     ptimer_run(env->stick, 1);
 275     env->hstick_cmpr = TICK_INT_DIS | 0;
 276     ptimer_set_limit(env->hstick, TICK_MAX, 1);
 277     ptimer_run(env->hstick, 1);
 278     env->gregs[1] = 0; // Memory start
 279     env->gregs[2] = ram_size; // Memory size
 280     env->gregs[3] = 0; // Machine description XXX
 281     env->pc = s->reset_addr;
 282     env->npc = env->pc + 4;
 283 }
 284
 285 static void tick_irq(void *opaque)
 286 {
 287     CPUState *env = opaque;
 288
 289     if (!(env->tick_cmpr & TICK_INT_DIS)) {
 290         env->softint |= SOFTINT_TIMER;
 291         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 292     }
 293 }
 294
 295 static void stick_irq(void *opaque)
 296 {
 297     CPUState *env = opaque;
 298
 299     if (!(env->stick_cmpr & TICK_INT_DIS)) {
 300         env->softint |= SOFTINT_STIMER;
 301         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 302     }
 303 }
 304
 305 static void hstick_irq(void *opaque)
 306 {
 307     CPUState *env = opaque;
 308
 309     if (!(env->hstick_cmpr & TICK_INT_DIS)) {
 310         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 311     }
 312 }
 313
 314 void cpu_tick_set_count(void *opaque, uint64_t count)
 315 {
 316     ptimer_set_count(opaque, -count);
 317 }
 318
 319 uint64_t cpu_tick_get_count(void *opaque)
 320 {
 321     return -ptimer_get_count(opaque);
 322 }
 323
 324 void cpu_tick_set_limit(void *opaque, uint64_t limit)
 325 {
 326     ptimer_set_limit(opaque, -limit, 0);
 327 }
 328
 329 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 330 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 331 static const int ide_irq[2] = { 14, 15 };
 332
 333 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 334 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 335
 336 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 337 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 338
 339 static fdctrl_t *floppy_controller;
 340
 341 static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
 342                               uint32_t addr, uint32_t size, int type)
 343 {
 344     DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
 345     switch (region_num) {
 346     case 0:
 347         isa_mmio_init(addr, 0x1000000);
 348         break;
 349     case 1:
 350         isa_mmio_init(addr, 0x800000);
 351         break;
 352     }
 353 }
 354
 355 /* EBUS (Eight bit bus) bridge */
 356 static void
 357 pci_ebus_init(PCIBus *bus, int devfn)
 358 {
 359     pci_create_simple(bus, devfn, "ebus");
 360 }
 361
 362 static void
 363 pci_ebus_init1(PCIDevice *s)
 364 {
 365     pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
 366     pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
 367     s->config[0x04] = 0x06; // command = bus master, pci mem
 368     s->config[0x05] = 0x00;
 369     s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 370     s->config[0x07] = 0x03; // status = medium devsel
 371     s->config[0x08] = 0x01; // revision
 372     s->config[0x09] = 0x00; // programming i/f
 373     pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
 374     s->config[0x0D] = 0x0a; // latency_timer
 375     s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 376
 377     pci_register_bar(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM,
 378                            ebus_mmio_mapfunc);
 379     pci_register_bar(s, 1, 0x800000,  PCI_ADDRESS_SPACE_MEM,
 380                            ebus_mmio_mapfunc);
 381 }
 382
 383 static PCIDeviceInfo ebus_info = {
 384     .qdev.name = "ebus",
 385     .qdev.size = sizeof(PCIDevice),
 386     .init = pci_ebus_init1,
 387 };
 388
 389 static void pci_ebus_register(void)
 390 {
 391     pci_qdev_register(&ebus_info);
 392 }
 393
 394 device_init(pci_ebus_register);
 395
 396 /* Boot PROM (OpenBIOS) */
 397 static void prom_init(target_phys_addr_t addr, const char *bios_name)
 398 {
 399     DeviceState *dev;
 400     SysBusDevice *s;
 401     char *filename;
 402     int ret;
 403
 404     dev = qdev_create(NULL, "openprom");
 405     qdev_init(dev);
 406     s = sysbus_from_qdev(dev);
 407
 408     sysbus_mmio_map(s, 0, addr);
 409
 410     /* load boot prom */
 411     if (bios_name == NULL) {
 412         bios_name = PROM_FILENAME;
 413     }
 414     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 415     if (filename) {
 416         ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL);
 417         if (ret < 0 || ret > PROM_SIZE_MAX) {
 418             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 419         }
 420         qemu_free(filename);
 421     } else {
 422         ret = -1;
 423     }
 424     if (ret < 0 || ret > PROM_SIZE_MAX) {
 425         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 426         exit(1);
 427     }
 428 }
 429
 430 static void prom_init1(SysBusDevice *dev)
 431 {
 432     ram_addr_t prom_offset;
 433
 434     prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
 435     sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
 436 }
 437
 438 static SysBusDeviceInfo prom_info = {
 439     .init = prom_init1,
 440     .qdev.name  = "openprom",
 441     .qdev.size  = sizeof(SysBusDevice),
 442     .qdev.props = (Property[]) {
 443         {/* end of property list */}
 444     }
 445 };
 446
 447 static void prom_register_devices(void)
 448 {
 449     sysbus_register_withprop(&prom_info);
 450 }
 451
 452 device_init(prom_register_devices);
 453
 454
 455 typedef struct RamDevice
 456 {
 457     SysBusDevice busdev;
 458     uint64_t size;
 459 } RamDevice;
 460
 461 /* System RAM */
 462 static void ram_init1(SysBusDevice *dev)
 463 {
 464     ram_addr_t RAM_size, ram_offset;
 465     RamDevice *d = FROM_SYSBUS(RamDevice, dev);
 466
 467     RAM_size = d->size;
 468
 469     ram_offset = qemu_ram_alloc(RAM_size);
 470     sysbus_init_mmio(dev, RAM_size, ram_offset);
 471 }
 472
 473 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
 474 {
 475     DeviceState *dev;
 476     SysBusDevice *s;
 477     RamDevice *d;
 478
 479     /* allocate RAM */
 480     dev = qdev_create(NULL, "memory");
 481     s = sysbus_from_qdev(dev);
 482
 483     d = FROM_SYSBUS(RamDevice, s);
 484     d->size = RAM_size;
 485     qdev_init(dev);
 486
 487     sysbus_mmio_map(s, 0, addr);
 488 }
 489
 490 static SysBusDeviceInfo ram_info = {
 491     .init = ram_init1,
 492     .qdev.name  = "memory",
 493     .qdev.size  = sizeof(RamDevice),
 494     .qdev.props = (Property[]) {
 495         {
 496             .name = "size",
 497             .info = &qdev_prop_uint64,
 498             .offset = offsetof(RamDevice, size),
 499         },
 500         {/* end of property list */}
 501     }
 502 };
 503
 504 static void ram_register_devices(void)
 505 {
 506     sysbus_register_withprop(&ram_info);
 507 }
 508
 509 device_init(ram_register_devices);
 510
 511 static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 512 {
 513     CPUState *env;
 514     QEMUBH *bh;
 515     ResetData *reset_info;
 516
 517     if (!cpu_model)
 518         cpu_model = hwdef->default_cpu_model;
 519     env = cpu_init(cpu_model);
 520     if (!env) {
 521         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 522         exit(1);
 523     }
 524     bh = qemu_bh_new(tick_irq, env);
 525     env->tick = ptimer_init(bh);
 526     ptimer_set_period(env->tick, 1ULL);
 527
 528     bh = qemu_bh_new(stick_irq, env);
 529     env->stick = ptimer_init(bh);
 530     ptimer_set_period(env->stick, 1ULL);
 531
 532     bh = qemu_bh_new(hstick_irq, env);
 533     env->hstick = ptimer_init(bh);
 534     ptimer_set_period(env->hstick, 1ULL);
 535
 536     reset_info = qemu_mallocz(sizeof(ResetData));
 537     reset_info->env = env;
 538     reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
 539     qemu_register_reset(main_cpu_reset, reset_info);
 540     main_cpu_reset(reset_info);
 541     // Override warm reset address with cold start address
 542     env->pc = hwdef->prom_addr + 0x20ULL;
 543     env->npc = env->pc + 4;
 544
 545     return env;
 546 }
 547
 548 static void sun4uv_init(ram_addr_t RAM_size,
 549                         const char *boot_devices,
 550                         const char *kernel_filename, const char *kernel_cmdline,
 551                         const char *initrd_filename, const char *cpu_model,
 552                         const struct hwdef *hwdef)
 553 {
 554     CPUState *env;
 555     m48t59_t *nvram;
 556     unsigned int i;
 557     long initrd_size, kernel_size;
 558     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 559     qemu_irq *irq;
 560     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 561     BlockDriverState *fd[MAX_FD];
 562     void *fw_cfg;
 563     DriveInfo *dinfo;
 564
 565     /* init CPUs */
 566     env = cpu_devinit(cpu_model, hwdef);
 567
 568     /* set up devices */
 569     ram_init(0, RAM_size);
 570
 571     prom_init(hwdef->prom_addr, bios_name);
 572
 573
 574     irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
 575     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
 576                            &pci_bus3);
 577     isa_mem_base = VGA_BASE;
 578     pci_vga_init(pci_bus, 0, 0);
 579
 580     // XXX Should be pci_bus3
 581     pci_ebus_init(pci_bus, -1);
 582
 583     i = 0;
 584     if (hwdef->console_serial_base) {
 585         serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
 586                        serial_hds[i], 1);
 587         i++;
 588     }
 589     for(; i < MAX_SERIAL_PORTS; i++) {
 590         if (serial_hds[i]) {
 591             serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
 592                         serial_hds[i]);
 593         }
 594     }
 595
 596     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 597         if (parallel_hds[i]) {
 598             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
 599                           parallel_hds[i]);
 600         }
 601     }
 602
 603     for(i = 0; i < nb_nics; i++)
 604         pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
 605
 606     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 607         fprintf(stderr, "qemu: too many IDE bus\n");
 608         exit(1);
 609     }
 610     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 611         dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS,
 612                           i % MAX_IDE_DEVS);
 613         hd[i] = dinfo ? dinfo->bdrv : NULL;
 614     }
 615
 616     pci_cmd646_ide_init(pci_bus, hd, 1);
 617
 618     /* FIXME: wire up interrupts.  */
 619     i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
 620     for(i = 0; i < MAX_FD; i++) {
 621         dinfo = drive_get(IF_FLOPPY, 0, i);
 622         fd[i] = dinfo ? dinfo->bdrv : NULL;
 623     }
 624     floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
 625     nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
 626
 627     initrd_size = 0;
 628     kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
 629                                     ram_size, &initrd_size);
 630
 631     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 632                            KERNEL_LOAD_ADDR, kernel_size,
 633                            kernel_cmdline,
 634                            INITRD_LOAD_ADDR, initrd_size,
 635                            /* XXX: need an option to load a NVRAM image */
 636                            0,
 637                            graphic_width, graphic_height, graphic_depth,
 638                            (uint8_t *)&nd_table[0].macaddr);
 639
 640     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 641     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 642     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 643     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 644     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
 645     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 646     if (kernel_cmdline) {
 647         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 648         pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 649     } else {
 650         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 651     }
 652     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
 653     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 654     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
 655     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 656 }
 657
 658 enum {
 659     sun4u_id = 0,
 660     sun4v_id = 64,
 661     niagara_id,
 662 };
 663
 664 static const struct hwdef hwdefs[] = {
 665     /* Sun4u generic PC-like machine */
 666     {
 667         .default_cpu_model = "TI UltraSparc II",
 668         .machine_id = sun4u_id,
 669         .prom_addr = 0x1fff0000000ULL,
 670         .console_serial_base = 0,
 671     },
 672     /* Sun4v generic PC-like machine */
 673     {
 674         .default_cpu_model = "Sun UltraSparc T1",
 675         .machine_id = sun4v_id,
 676         .prom_addr = 0x1fff0000000ULL,
 677         .console_serial_base = 0,
 678     },
 679     /* Sun4v generic Niagara machine */
 680     {
 681         .default_cpu_model = "Sun UltraSparc T1",
 682         .machine_id = niagara_id,
 683         .prom_addr = 0xfff0000000ULL,
 684         .console_serial_base = 0xfff0c2c000ULL,
 685     },
 686 };
 687
 688 /* Sun4u hardware initialisation */
 689 static void sun4u_init(ram_addr_t RAM_size,
 690                        const char *boot_devices,
 691                        const char *kernel_filename, const char *kernel_cmdline,
 692                        const char *initrd_filename, const char *cpu_model)
 693 {
 694     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 695                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 696 }
 697
 698 /* Sun4v hardware initialisation */
 699 static void sun4v_init(ram_addr_t RAM_size,
 700                        const char *boot_devices,
 701                        const char *kernel_filename, const char *kernel_cmdline,
 702                        const char *initrd_filename, const char *cpu_model)
 703 {
 704     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 705                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 706 }
 707
 708 /* Niagara hardware initialisation */
 709 static void niagara_init(ram_addr_t RAM_size,
 710                          const char *boot_devices,
 711                          const char *kernel_filename, const char *kernel_cmdline,
 712                          const char *initrd_filename, const char *cpu_model)
 713 {
 714     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 715                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 716 }
 717
 718 static QEMUMachine sun4u_machine = {
 719     .name = "sun4u",
 720     .desc = "Sun4u platform",
 721     .init = sun4u_init,
 722     .max_cpus = 1, // XXX for now
 723     .is_default = 1,
 724 };
 725
 726 static QEMUMachine sun4v_machine = {
 727     .name = "sun4v",
 728     .desc = "Sun4v platform",
 729     .init = sun4v_init,
 730     .max_cpus = 1, // XXX for now
 731 };
 732
 733 static QEMUMachine niagara_machine = {
 734     .name = "Niagara",
 735     .desc = "Sun4v platform, Niagara",
 736     .init = niagara_init,
 737     .max_cpus = 1, // XXX for now
 738 };
 739
 740 static void sun4u_machine_init(void)
 741 {
 742     qemu_register_machine(&sun4u_machine);
 743     qemu_register_machine(&sun4v_machine);
 744     qemu_register_machine(&niagara_machine);
 745 }
 746
 747 machine_init(sun4u_machine_init);