hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "apb_pci.h"
  27 #include "pc.h"
  28 #include "nvram.h"
  29 #include "fdc.h"
  30 #include "net.h"
  31 #include "qemu-timer.h"
  32 #include "sysemu.h"
  33 #include "boards.h"
  34 #include "firmware_abi.h"
  35 #include "fw_cfg.h"
  36 #include "sysbus.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "elf.h"
  40 #include "blockdev.h"
  41 #include "exec-memory.h"
  42
  43 //#define DEBUG_IRQ
  44 //#define DEBUG_EBUS
  45 //#define DEBUG_TIMER
  46
  47 #ifdef DEBUG_IRQ
  48 #define CPUIRQ_DPRINTF(fmt, ...)                                \
  49     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  50 #else
  51 #define CPUIRQ_DPRINTF(fmt, ...)
  52 #endif
  53
  54 #ifdef DEBUG_EBUS
  55 #define EBUS_DPRINTF(fmt, ...)                                  \
  56     do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
  57 #else
  58 #define EBUS_DPRINTF(fmt, ...)
  59 #endif
  60
  61 #ifdef DEBUG_TIMER
  62 #define TIMER_DPRINTF(fmt, ...)                                  \
  63     do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
  64 #else
  65 #define TIMER_DPRINTF(fmt, ...)
  66 #endif
  67
  68 #define KERNEL_LOAD_ADDR     0x00404000
  69 #define CMDLINE_ADDR         0x003ff000
  70 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  71 #define PROM_VADDR           0x000ffd00000ULL
  72 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  73 #define APB_MEM_BASE         0x1ff00000000ULL
  74 #define APB_PCI_IO_BASE      (APB_SPECIAL_BASE + 0x02000000ULL)
  75 #define PROM_FILENAME        "openbios-sparc64"
  76 #define NVRAM_SIZE           0x2000
  77 #define MAX_IDE_BUS          2
  78 #define BIOS_CFG_IOPORT      0x510
  79 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  80 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  81 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  82
  83 #define IVEC_MAX             0x30
  84
  85 #define TICK_MAX             0x7fffffffffffffffULL
  86
  87 struct hwdef {
  88     const char * const default_cpu_model;
  89     uint16_t machine_id;
  90     uint64_t prom_addr;
  91     uint64_t console_serial_base;
  92 };
  93
  94 typedef struct EbusState {
  95     PCIDevice pci_dev;
  96     MemoryRegion bar0;
  97     MemoryRegion bar1;
  98 } EbusState;
  99
 100 int DMA_get_channel_mode (int nchan)
 101 {
 102     return 0;
 103 }
 104 int DMA_read_memory (int nchan, void *buf, int pos, int size)
 105 {
 106     return 0;
 107 }
 108 int DMA_write_memory (int nchan, void *buf, int pos, int size)
 109 {
 110     return 0;
 111 }
 112 void DMA_hold_DREQ (int nchan) {}
 113 void DMA_release_DREQ (int nchan) {}
 114 void DMA_schedule(int nchan) {}
 115
 116 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
 117 {
 118 }
 119
 120 void DMA_register_channel (int nchan,
 121                            DMA_transfer_handler transfer_handler,
 122                            void *opaque)
 123 {
 124 }
 125
 126 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 127 {
 128     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 129     return 0;
 130 }
 131
 132 static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
 133                                   const char *arch, ram_addr_t RAM_size,
 134                                   const char *boot_devices,
 135                                   uint32_t kernel_image, uint32_t kernel_size,
 136                                   const char *cmdline,
 137                                   uint32_t initrd_image, uint32_t initrd_size,
 138                                   uint32_t NVRAM_image,
 139                                   int width, int height, int depth,
 140                                   const uint8_t *macaddr)
 141 {
 142     unsigned int i;
 143     uint32_t start, end;
 144     uint8_t image[0x1ff0];
 145     struct OpenBIOS_nvpart_v1 *part_header;
 146
 147     memset(image, '\0', sizeof(image));
 148
 149     start = 0;
 150
 151     // OpenBIOS nvram variables
 152     // Variable partition
 153     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 154     part_header->signature = OPENBIOS_PART_SYSTEM;
 155     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 156
 157     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 158     for (i = 0; i < nb_prom_envs; i++)
 159         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 160
 161     // End marker
 162     image[end++] = '\0';
 163
 164     end = start + ((end - start + 15) & ~15);
 165     OpenBIOS_finish_partition(part_header, end - start);
 166
 167     // free partition
 168     start = end;
 169     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 170     part_header->signature = OPENBIOS_PART_FREE;
 171     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 172
 173     end = 0x1fd0;
 174     OpenBIOS_finish_partition(part_header, end - start);
 175
 176     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 177
 178     for (i = 0; i < sizeof(image); i++)
 179         m48t59_write(nvram, i, image[i]);
 180
 181     return 0;
 182 }
 183
 184 static uint64_t sun4u_load_kernel(const char *kernel_filename,
 185                                   const char *initrd_filename,
 186                                   ram_addr_t RAM_size, uint64_t *initrd_size,
 187                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
 188                                   uint64_t *kernel_entry)
 189 {
 190     int linux_boot;
 191     unsigned int i;
 192     long kernel_size;
 193     uint8_t *ptr;
 194     uint64_t kernel_top;
 195
 196     linux_boot = (kernel_filename != NULL);
 197
 198     kernel_size = 0;
 199     if (linux_boot) {
 200         int bswap_needed;
 201
 202 #ifdef BSWAP_NEEDED
 203         bswap_needed = 1;
 204 #else
 205         bswap_needed = 0;
 206 #endif
 207         kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
 208                                kernel_addr, &kernel_top, 1, ELF_MACHINE, 0);
 209         if (kernel_size < 0) {
 210             *kernel_addr = KERNEL_LOAD_ADDR;
 211             *kernel_entry = KERNEL_LOAD_ADDR;
 212             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 213                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 214                                     TARGET_PAGE_SIZE);
 215         }
 216         if (kernel_size < 0) {
 217             kernel_size = load_image_targphys(kernel_filename,
 218                                               KERNEL_LOAD_ADDR,
 219                                               RAM_size - KERNEL_LOAD_ADDR);
 220         }
 221         if (kernel_size < 0) {
 222             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 223                     kernel_filename);
 224             exit(1);
 225         }
 226         /* load initrd above kernel */
 227         *initrd_size = 0;
 228         if (initrd_filename) {
 229             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
 230
 231             *initrd_size = load_image_targphys(initrd_filename,
 232                                                *initrd_addr,
 233                                                RAM_size - *initrd_addr);
 234             if ((int)*initrd_size < 0) {
 235                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 236                         initrd_filename);
 237                 exit(1);
 238             }
 239         }
 240         if (*initrd_size > 0) {
 241             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 242                 ptr = rom_ptr(*kernel_addr + i);
 243                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 244                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
 245                     stl_p(ptr + 28, *initrd_size);
 246                     break;
 247                 }
 248             }
 249         }
 250     }
 251     return kernel_size;
 252 }
 253
 254 void cpu_check_irqs(CPUSPARCState *env)
 255 {
 256     uint32_t pil = env->pil_in |
 257                   (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
 258
 259     /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
 260     if (env->ivec_status & 0x20) {
 261         return;
 262     }
 263     /* check if TM or SM in SOFTINT are set
 264        setting these also causes interrupt 14 */
 265     if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
 266         pil |= 1 << 14;
 267     }
 268
 269     /* The bit corresponding to psrpil is (1<< psrpil), the next bit
 270        is (2 << psrpil). */
 271     if (pil < (2 << env->psrpil)){
 272         if (env->interrupt_request & CPU_INTERRUPT_HARD) {
 273             CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
 274                            env->interrupt_index);
 275             env->interrupt_index = 0;
 276             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 277         }
 278         return;
 279     }
 280
 281     if (cpu_interrupts_enabled(env)) {
 282
 283         unsigned int i;
 284
 285         for (i = 15; i > env->psrpil; i--) {
 286             if (pil & (1 << i)) {
 287                 int old_interrupt = env->interrupt_index;
 288                 int new_interrupt = TT_EXTINT | i;
 289
 290                 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
 291                   && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
 292                     CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
 293                                    "current %x >= pending %x\n",
 294                                    env->tl, cpu_tsptr(env)->tt, new_interrupt);
 295                 } else if (old_interrupt != new_interrupt) {
 296                     env->interrupt_index = new_interrupt;
 297                     CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
 298                                    old_interrupt, new_interrupt);
 299                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 300                 }
 301                 break;
 302             }
 303         }
 304     } else if (env->interrupt_request & CPU_INTERRUPT_HARD) {
 305         CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
 306                        "current interrupt %x\n",
 307                        pil, env->pil_in, env->softint, env->interrupt_index);
 308         env->interrupt_index = 0;
 309         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 310     }
 311 }
 312
 313 static void cpu_kick_irq(SPARCCPU *cpu)
 314 {
 315     CPUSPARCState *env = &cpu->env;
 316
 317     env->halted = 0;
 318     cpu_check_irqs(env);
 319     qemu_cpu_kick(env);
 320 }
 321
 322 static void cpu_set_ivec_irq(void *opaque, int irq, int level)
 323 {
 324     SPARCCPU *cpu = opaque;
 325     CPUSPARCState *env = &cpu->env;
 326
 327     if (level) {
 328         if (!(env->ivec_status & 0x20)) {
 329             CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
 330             env->halted = 0;
 331             env->interrupt_index = TT_IVEC;
 332             env->ivec_status |= 0x20;
 333             env->ivec_data[0] = (0x1f << 6) | irq;
 334             env->ivec_data[1] = 0;
 335             env->ivec_data[2] = 0;
 336             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 337         }
 338     } else {
 339         if (env->ivec_status & 0x20) {
 340             CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
 341             env->ivec_status &= ~0x20;
 342             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 343         }
 344     }
 345 }
 346
 347 typedef struct ResetData {
 348     SPARCCPU *cpu;
 349     uint64_t prom_addr;
 350 } ResetData;
 351
 352 void cpu_put_timer(QEMUFile *f, CPUTimer *s)
 353 {
 354     qemu_put_be32s(f, &s->frequency);
 355     qemu_put_be32s(f, &s->disabled);
 356     qemu_put_be64s(f, &s->disabled_mask);
 357     qemu_put_sbe64s(f, &s->clock_offset);
 358
 359     qemu_put_timer(f, s->qtimer);
 360 }
 361
 362 void cpu_get_timer(QEMUFile *f, CPUTimer *s)
 363 {
 364     qemu_get_be32s(f, &s->frequency);
 365     qemu_get_be32s(f, &s->disabled);
 366     qemu_get_be64s(f, &s->disabled_mask);
 367     qemu_get_sbe64s(f, &s->clock_offset);
 368
 369     qemu_get_timer(f, s->qtimer);
 370 }
 371
 372 static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
 373                                   QEMUBHFunc *cb, uint32_t frequency,
 374                                   uint64_t disabled_mask)
 375 {
 376     CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
 377
 378     timer->name = name;
 379     timer->frequency = frequency;
 380     timer->disabled_mask = disabled_mask;
 381
 382     timer->disabled = 1;
 383     timer->clock_offset = qemu_get_clock_ns(vm_clock);
 384
 385     timer->qtimer = qemu_new_timer_ns(vm_clock, cb, cpu);
 386
 387     return timer;
 388 }
 389
 390 static void cpu_timer_reset(CPUTimer *timer)
 391 {
 392     timer->disabled = 1;
 393     timer->clock_offset = qemu_get_clock_ns(vm_clock);
 394
 395     qemu_del_timer(timer->qtimer);
 396 }
 397
 398 static void main_cpu_reset(void *opaque)
 399 {
 400     ResetData *s = (ResetData *)opaque;
 401     CPUSPARCState *env = &s->cpu->env;
 402     static unsigned int nr_resets;
 403
 404     cpu_reset(CPU(s->cpu));
 405
 406     cpu_timer_reset(env->tick);
 407     cpu_timer_reset(env->stick);
 408     cpu_timer_reset(env->hstick);
 409
 410     env->gregs[1] = 0; // Memory start
 411     env->gregs[2] = ram_size; // Memory size
 412     env->gregs[3] = 0; // Machine description XXX
 413     if (nr_resets++ == 0) {
 414         /* Power on reset */
 415         env->pc = s->prom_addr + 0x20ULL;
 416     } else {
 417         env->pc = s->prom_addr + 0x40ULL;
 418     }
 419     env->npc = env->pc + 4;
 420 }
 421
 422 static void tick_irq(void *opaque)
 423 {
 424     SPARCCPU *cpu = opaque;
 425     CPUSPARCState *env = &cpu->env;
 426
 427     CPUTimer* timer = env->tick;
 428
 429     if (timer->disabled) {
 430         CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
 431         return;
 432     } else {
 433         CPUIRQ_DPRINTF("tick: fire\n");
 434     }
 435
 436     env->softint |= SOFTINT_TIMER;
 437     cpu_kick_irq(cpu);
 438 }
 439
 440 static void stick_irq(void *opaque)
 441 {
 442     SPARCCPU *cpu = opaque;
 443     CPUSPARCState *env = &cpu->env;
 444
 445     CPUTimer* timer = env->stick;
 446
 447     if (timer->disabled) {
 448         CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
 449         return;
 450     } else {
 451         CPUIRQ_DPRINTF("stick: fire\n");
 452     }
 453
 454     env->softint |= SOFTINT_STIMER;
 455     cpu_kick_irq(cpu);
 456 }
 457
 458 static void hstick_irq(void *opaque)
 459 {
 460     SPARCCPU *cpu = opaque;
 461     CPUSPARCState *env = &cpu->env;
 462
 463     CPUTimer* timer = env->hstick;
 464
 465     if (timer->disabled) {
 466         CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
 467         return;
 468     } else {
 469         CPUIRQ_DPRINTF("hstick: fire\n");
 470     }
 471
 472     env->softint |= SOFTINT_STIMER;
 473     cpu_kick_irq(cpu);
 474 }
 475
 476 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
 477 {
 478     return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
 479 }
 480
 481 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
 482 {
 483     return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
 484 }
 485
 486 void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
 487 {
 488     uint64_t real_count = count & ~timer->disabled_mask;
 489     uint64_t disabled_bit = count & timer->disabled_mask;
 490
 491     int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) -
 492                     cpu_to_timer_ticks(real_count, timer->frequency);
 493
 494     TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
 495                   timer->name, real_count,
 496                   timer->disabled?"disabled":"enabled", timer);
 497
 498     timer->disabled = disabled_bit ? 1 : 0;
 499     timer->clock_offset = vm_clock_offset;
 500 }
 501
 502 uint64_t cpu_tick_get_count(CPUTimer *timer)
 503 {
 504     uint64_t real_count = timer_to_cpu_ticks(
 505                     qemu_get_clock_ns(vm_clock) - timer->clock_offset,
 506                     timer->frequency);
 507
 508     TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
 509            timer->name, real_count,
 510            timer->disabled?"disabled":"enabled", timer);
 511
 512     if (timer->disabled)
 513         real_count |= timer->disabled_mask;
 514
 515     return real_count;
 516 }
 517
 518 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
 519 {
 520     int64_t now = qemu_get_clock_ns(vm_clock);
 521
 522     uint64_t real_limit = limit & ~timer->disabled_mask;
 523     timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
 524
 525     int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
 526                     timer->clock_offset;
 527
 528     if (expires < now) {
 529         expires = now + 1;
 530     }
 531
 532     TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
 533                   "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
 534                   timer->name, real_limit,
 535                   timer->disabled?"disabled":"enabled",
 536                   timer, limit,
 537                   timer_to_cpu_ticks(now - timer->clock_offset,
 538                                      timer->frequency),
 539                   timer_to_cpu_ticks(expires - now, timer->frequency));
 540
 541     if (!real_limit) {
 542         TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
 543                 timer->name);
 544         qemu_del_timer(timer->qtimer);
 545     } else if (timer->disabled) {
 546         qemu_del_timer(timer->qtimer);
 547     } else {
 548         qemu_mod_timer(timer->qtimer, expires);
 549     }
 550 }
 551
 552 static void isa_irq_handler(void *opaque, int n, int level)
 553 {
 554     static const int isa_irq_to_ivec[16] = {
 555         [1] = 0x29, /* keyboard */
 556         [4] = 0x2b, /* serial */
 557         [6] = 0x27, /* floppy */
 558         [7] = 0x22, /* parallel */
 559         [12] = 0x2a, /* mouse */
 560     };
 561     qemu_irq *irqs = opaque;
 562     int ivec;
 563
 564     assert(n < 16);
 565     ivec = isa_irq_to_ivec[n];
 566     EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec);
 567     if (ivec) {
 568         qemu_set_irq(irqs[ivec], level);
 569     }
 570 }
 571
 572 /* EBUS (Eight bit bus) bridge */
 573 static ISABus *
 574 pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
 575 {
 576     qemu_irq *isa_irq;
 577     PCIDevice *pci_dev;
 578     ISABus *isa_bus;
 579
 580     pci_dev = pci_create_simple(bus, devfn, "ebus");
 581     isa_bus = DO_UPCAST(ISABus, qbus,
 582                         qdev_get_child_bus(&pci_dev->qdev, "isa.0"));
 583     isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
 584     isa_bus_irqs(isa_bus, isa_irq);
 585     return isa_bus;
 586 }
 587
 588 static int
 589 pci_ebus_init1(PCIDevice *pci_dev)
 590 {
 591     EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
 592
 593     isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev));
 594
 595     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 596     pci_dev->config[0x05] = 0x00;
 597     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 598     pci_dev->config[0x07] = 0x03; // status = medium devsel
 599     pci_dev->config[0x09] = 0x00; // programming i/f
 600     pci_dev->config[0x0D] = 0x0a; // latency_timer
 601
 602     isa_mmio_setup(&s->bar0, 0x1000000);
 603     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 604     isa_mmio_setup(&s->bar1, 0x800000);
 605     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
 606     return 0;
 607 }
 608
 609 static void ebus_class_init(ObjectClass *klass, void *data)
 610 {
 611     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 612
 613     k->init = pci_ebus_init1;
 614     k->vendor_id = PCI_VENDOR_ID_SUN;
 615     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 616     k->revision = 0x01;
 617     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 618 }
 619
 620 static TypeInfo ebus_info = {
 621     .name          = "ebus",
 622     .parent        = TYPE_PCI_DEVICE,
 623     .instance_size = sizeof(EbusState),
 624     .class_init    = ebus_class_init,
 625 };
 626
 627 typedef struct PROMState {
 628     SysBusDevice busdev;
 629     MemoryRegion prom;
 630 } PROMState;
 631
 632 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 633 {
 634     target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
 635     return addr + *base_addr - PROM_VADDR;
 636 }
 637
 638 /* Boot PROM (OpenBIOS) */
 639 static void prom_init(target_phys_addr_t addr, const char *bios_name)
 640 {
 641     DeviceState *dev;
 642     SysBusDevice *s;
 643     char *filename;
 644     int ret;
 645
 646     dev = qdev_create(NULL, "openprom");
 647     qdev_init_nofail(dev);
 648     s = sysbus_from_qdev(dev);
 649
 650     sysbus_mmio_map(s, 0, addr);
 651
 652     /* load boot prom */
 653     if (bios_name == NULL) {
 654         bios_name = PROM_FILENAME;
 655     }
 656     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 657     if (filename) {
 658         ret = load_elf(filename, translate_prom_address, &addr,
 659                        NULL, NULL, NULL, 1, ELF_MACHINE, 0);
 660         if (ret < 0 || ret > PROM_SIZE_MAX) {
 661             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 662         }
 663         g_free(filename);
 664     } else {
 665         ret = -1;
 666     }
 667     if (ret < 0 || ret > PROM_SIZE_MAX) {
 668         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 669         exit(1);
 670     }
 671 }
 672
 673 static int prom_init1(SysBusDevice *dev)
 674 {
 675     PROMState *s = FROM_SYSBUS(PROMState, dev);
 676
 677     memory_region_init_ram(&s->prom, "sun4u.prom", PROM_SIZE_MAX);
 678     vmstate_register_ram_global(&s->prom);
 679     memory_region_set_readonly(&s->prom, true);
 680     sysbus_init_mmio(dev, &s->prom);
 681     return 0;
 682 }
 683
 684 static Property prom_properties[] = {
 685     {/* end of property list */},
 686 };
 687
 688 static void prom_class_init(ObjectClass *klass, void *data)
 689 {
 690     DeviceClass *dc = DEVICE_CLASS(klass);
 691     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 692
 693     k->init = prom_init1;
 694     dc->props = prom_properties;
 695 }
 696
 697 static TypeInfo prom_info = {
 698     .name          = "openprom",
 699     .parent        = TYPE_SYS_BUS_DEVICE,
 700     .instance_size = sizeof(PROMState),
 701     .class_init    = prom_class_init,
 702 };
 703
 704
 705 typedef struct RamDevice
 706 {
 707     SysBusDevice busdev;
 708     MemoryRegion ram;
 709     uint64_t size;
 710 } RamDevice;
 711
 712 /* System RAM */
 713 static int ram_init1(SysBusDevice *dev)
 714 {
 715     RamDevice *d = FROM_SYSBUS(RamDevice, dev);
 716
 717     memory_region_init_ram(&d->ram, "sun4u.ram", d->size);
 718     vmstate_register_ram_global(&d->ram);
 719     sysbus_init_mmio(dev, &d->ram);
 720     return 0;
 721 }
 722
 723 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
 724 {
 725     DeviceState *dev;
 726     SysBusDevice *s;
 727     RamDevice *d;
 728
 729     /* allocate RAM */
 730     dev = qdev_create(NULL, "memory");
 731     s = sysbus_from_qdev(dev);
 732
 733     d = FROM_SYSBUS(RamDevice, s);
 734     d->size = RAM_size;
 735     qdev_init_nofail(dev);
 736
 737     sysbus_mmio_map(s, 0, addr);
 738 }
 739
 740 static Property ram_properties[] = {
 741     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 742     DEFINE_PROP_END_OF_LIST(),
 743 };
 744
 745 static void ram_class_init(ObjectClass *klass, void *data)
 746 {
 747     DeviceClass *dc = DEVICE_CLASS(klass);
 748     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 749
 750     k->init = ram_init1;
 751     dc->props = ram_properties;
 752 }
 753
 754 static TypeInfo ram_info = {
 755     .name          = "memory",
 756     .parent        = TYPE_SYS_BUS_DEVICE,
 757     .instance_size = sizeof(RamDevice),
 758     .class_init    = ram_class_init,
 759 };
 760
 761 static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 762 {
 763     SPARCCPU *cpu;
 764     CPUSPARCState *env;
 765     ResetData *reset_info;
 766
 767     uint32_t   tick_frequency = 100*1000000;
 768     uint32_t  stick_frequency = 100*1000000;
 769     uint32_t hstick_frequency = 100*1000000;
 770
 771     if (cpu_model == NULL) {
 772         cpu_model = hwdef->default_cpu_model;
 773     }
 774     cpu = cpu_sparc_init(cpu_model);
 775     if (cpu == NULL) {
 776         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 777         exit(1);
 778     }
 779     env = &cpu->env;
 780
 781     env->tick = cpu_timer_create("tick", cpu, tick_irq,
 782                                   tick_frequency, TICK_NPT_MASK);
 783
 784     env->stick = cpu_timer_create("stick", cpu, stick_irq,
 785                                    stick_frequency, TICK_INT_DIS);
 786
 787     env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
 788                                     hstick_frequency, TICK_INT_DIS);
 789
 790     reset_info = g_malloc0(sizeof(ResetData));
 791     reset_info->cpu = cpu;
 792     reset_info->prom_addr = hwdef->prom_addr;
 793     qemu_register_reset(main_cpu_reset, reset_info);
 794
 795     return cpu;
 796 }
 797
 798 static void sun4uv_init(MemoryRegion *address_space_mem,
 799                         ram_addr_t RAM_size,
 800                         const char *boot_devices,
 801                         const char *kernel_filename, const char *kernel_cmdline,
 802                         const char *initrd_filename, const char *cpu_model,
 803                         const struct hwdef *hwdef)
 804 {
 805     SPARCCPU *cpu;
 806     M48t59State *nvram;
 807     unsigned int i;
 808     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
 809     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 810     ISABus *isa_bus;
 811     qemu_irq *ivec_irqs, *pbm_irqs;
 812     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 813     DriveInfo *fd[MAX_FD];
 814     void *fw_cfg;
 815
 816     /* init CPUs */
 817     cpu = cpu_devinit(cpu_model, hwdef);
 818
 819     /* set up devices */
 820     ram_init(0, RAM_size);
 821
 822     prom_init(hwdef->prom_addr, bios_name);
 823
 824     ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX);
 825     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2,
 826                            &pci_bus3, &pbm_irqs);
 827     pci_vga_init(pci_bus);
 828
 829     // XXX Should be pci_bus3
 830     isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
 831
 832     i = 0;
 833     if (hwdef->console_serial_base) {
 834         serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
 835                        NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
 836         i++;
 837     }
 838     for(; i < MAX_SERIAL_PORTS; i++) {
 839         if (serial_hds[i]) {
 840             serial_isa_init(isa_bus, i, serial_hds[i]);
 841         }
 842     }
 843
 844     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 845         if (parallel_hds[i]) {
 846             parallel_init(isa_bus, i, parallel_hds[i]);
 847         }
 848     }
 849
 850     for(i = 0; i < nb_nics; i++)
 851         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 852
 853     ide_drive_get(hd, MAX_IDE_BUS);
 854
 855     pci_cmd646_ide_init(pci_bus, hd, 1);
 856
 857     isa_create_simple(isa_bus, "i8042");
 858     for(i = 0; i < MAX_FD; i++) {
 859         fd[i] = drive_get(IF_FLOPPY, 0, i);
 860     }
 861     fdctrl_init_isa(isa_bus, fd);
 862     nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
 863
 864     initrd_size = 0;
 865     initrd_addr = 0;
 866     kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
 867                                     ram_size, &initrd_size, &initrd_addr,
 868                                     &kernel_addr, &kernel_entry);
 869
 870     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 871                            kernel_addr, kernel_size,
 872                            kernel_cmdline,
 873                            initrd_addr, initrd_size,
 874                            /* XXX: need an option to load a NVRAM image */
 875                            0,
 876                            graphic_width, graphic_height, graphic_depth,
 877                            (uint8_t *)&nd_table[0].macaddr);
 878
 879     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 880     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 881     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 882     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 883     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
 884     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 885     if (kernel_cmdline) {
 886         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 887                        strlen(kernel_cmdline) + 1);
 888         fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 889                          (uint8_t*)strdup(kernel_cmdline),
 890                          strlen(kernel_cmdline) + 1);
 891     } else {
 892         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 893     }
 894     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 895     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 896     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
 897
 898     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 899     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 900     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 901
 902     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 903 }
 904
 905 enum {
 906     sun4u_id = 0,
 907     sun4v_id = 64,
 908     niagara_id,
 909 };
 910
 911 static const struct hwdef hwdefs[] = {
 912     /* Sun4u generic PC-like machine */
 913     {
 914         .default_cpu_model = "TI UltraSparc IIi",
 915         .machine_id = sun4u_id,
 916         .prom_addr = 0x1fff0000000ULL,
 917         .console_serial_base = 0,
 918     },
 919     /* Sun4v generic PC-like machine */
 920     {
 921         .default_cpu_model = "Sun UltraSparc T1",
 922         .machine_id = sun4v_id,
 923         .prom_addr = 0x1fff0000000ULL,
 924         .console_serial_base = 0,
 925     },
 926     /* Sun4v generic Niagara machine */
 927     {
 928         .default_cpu_model = "Sun UltraSparc T1",
 929         .machine_id = niagara_id,
 930         .prom_addr = 0xfff0000000ULL,
 931         .console_serial_base = 0xfff0c2c000ULL,
 932     },
 933 };
 934
 935 /* Sun4u hardware initialisation */
 936 static void sun4u_init(ram_addr_t RAM_size,
 937                        const char *boot_devices,
 938                        const char *kernel_filename, const char *kernel_cmdline,
 939                        const char *initrd_filename, const char *cpu_model)
 940 {
 941     sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
 942                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 943 }
 944
 945 /* Sun4v hardware initialisation */
 946 static void sun4v_init(ram_addr_t RAM_size,
 947                        const char *boot_devices,
 948                        const char *kernel_filename, const char *kernel_cmdline,
 949                        const char *initrd_filename, const char *cpu_model)
 950 {
 951     sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
 952                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 953 }
 954
 955 /* Niagara hardware initialisation */
 956 static void niagara_init(ram_addr_t RAM_size,
 957                          const char *boot_devices,
 958                          const char *kernel_filename, const char *kernel_cmdline,
 959                          const char *initrd_filename, const char *cpu_model)
 960 {
 961     sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
 962                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 963 }
 964
 965 static QEMUMachine sun4u_machine = {
 966     .name = "sun4u",
 967     .desc = "Sun4u platform",
 968     .init = sun4u_init,
 969     .max_cpus = 1, // XXX for now
 970     .is_default = 1,
 971 };
 972
 973 static QEMUMachine sun4v_machine = {
 974     .name = "sun4v",
 975     .desc = "Sun4v platform",
 976     .init = sun4v_init,
 977     .max_cpus = 1, // XXX for now
 978 };
 979
 980 static QEMUMachine niagara_machine = {
 981     .name = "Niagara",
 982     .desc = "Sun4v platform, Niagara",
 983     .init = niagara_init,
 984     .max_cpus = 1, // XXX for now
 985 };
 986
 987 static void sun4u_register_types(void)
 988 {
 989     type_register_static(&ebus_info);
 990     type_register_static(&prom_info);
 991     type_register_static(&ram_info);
 992 }
 993
 994 static void sun4u_machine_init(void)
 995 {
 996     qemu_register_machine(&sun4u_machine);
 997     qemu_register_machine(&sun4v_machine);
 998     qemu_register_machine(&niagara_machine);
 999 }
1000
1001 type_init(sun4u_register_types)
1002 machine_init(sun4u_machine_init);